JPH1082802A - Wave-form memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the noises from a memory address bus by using a gray code so that the hamming distance of the address numerical value becomes 1 before and after a change every time the memory address proceeds by 1. SOLUTION: The input signal of a CH1 is set to a proper amplitude through an attenuator 1 and an amplifier 3, it is converted by an ADD-converter 5 at the timing of the clock signal D from a time base circuit 10, and it is stored in a memory 7 by the write signal E from the time base circuit 10. A gray code memory address counter circuit 9 counts up based on the address counter clock signal F from the time base circuit 10, memory addresses A are inputted to a memory address bus in sequence, and the AD-converted wave-form data are stored in different addresses of a memory 8 in sequence. The memory addresses A are outputted in a gray code, and only one bit is changed every time one address proceeds. The occurrence of noises can be sharply suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a storage method of a waveform storage device such as a digital oscilloscope in a memory.

[0002]

2. Description of the Related Art FIG. 4 shows a prior art example. FIG. 1 is a block diagram showing a part of a two-channel input waveform storage device.

[0003] 1 and 2 are attenuator circuits, 3 and 4 are amplifiers, 5 and 6 are A / D converters, 7 and 8 are memories, 10 is a time base circuit, and 11 is a memory address counter circuit. The input signal of ch1 is attenuator 1, amplifier 3
Through the A / D converter 5 at a timing according to the clock signal D output from the time base 10 to obtain waveform data. Similarly, the write signal E output from the time base 10 is stored in the memory 7. At this time, the memory address counter circuit 11 counts up by the clock signal F for the address counter from the time base circuit 10 and sequentially outputs the memory addresses A via the bus. The D-converted waveform data is sequentially stored.

At this time, the memory address output from the memory address counter 11 is output in a binary code.

[0005]

The above-mentioned prior art includes the following:
There is a drawback that the bit of the address of the memory during the storage of the waveform data changes drastically, and more bits change simultaneously.

FIG. 3 shows a time chart of the memory address A on the address bus. 0 in binary code
When sequentially counting up from, if all bits change at the same time as indicated by the solid-line arrows, all but one bit change at the same time as indicated by the dashed-line arrows. In this example, only four bits are described for the sake of explanation. However, as the memory capacity increases, the number of address bits increases, and large noise occurs at the same time as changing. Since the number of changing bits varies depending on the timing, the amount of noise varies from large to small. This noise is a high-sensitivity analog circuit (attenuator 1, 2, amplifier 3,
4. It jumps into the A / D converters 5 and 6) and has an adverse effect.

Further, since this address signal changes frequently, there is a disadvantage that the current consumption for driving the input capacitance of the memory address increases. Generally, in a CMOS circuit, there is almost no static current consumption, and the driving current for charging / discharging the load capacitance at the change point of the logic level occupies most of the current consumption.

Although FIG. 2 shows two channels, the current consumption increases as the number of channels increases and the number of memories driven in parallel increases.

A first object of the present invention is to reduce noise from a memory address bus. A second object of the present invention is to reduce current consumption of a memory address driving circuit.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method in which a hamming distance of an address value before and after a memory address changes by one is set to one.
Gray code is used instead of binary code.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a diagram showing an embodiment of the present invention corresponding to FIG. 4 of the prior art described above, and the same reference numerals as those in FIG. 4 denote the same components.

Next, this operation will be described.

The input signal of ch1 has an appropriate amplitude through the attenuator 1 and the amplifier 3 and is digitally converted by the A / D converter 5 at the timing of the clock signal D output from the time base 10.
Is stored in the memory 7 by a write signal E output from the memory 7. The gray code memory address counter circuit 9 is different from the memory address counter 11 in FIG. At this time, the gray code memory address counter circuit 9 counts up by the clock signal F for the address counter from the time base circuit 10, sequentially outputs the memory addresses A to the memory address bus, and outputs A to different addresses of the memory. The / D-converted waveform data is sequentially stored.

The output memory address A is output in the gray code shown in FIG. In this embodiment, for simplicity of explanation, an example of address designation by 4 bits is shown as in FIG.

In the embodiment described above, as shown in the time chart of FIG. 2, the change of the memory address changes only one bit every time the address advances. In this way, the memory address changes only one bit at any time. If the number of addresses is n bits, simultaneous change of up to n bits occurs in the binary code address counter of the prior art which performs the address change of FIG. Since there is no such simultaneous change, the generation of noise is suppressed to 1 / n at the maximum.

Looking at the change of the address signal,
In the example of FIG. 3 of the related art, the logic levels of the four address signals are changed at 30 locations from address 0 to 15 after returning to 0, but in the example of FIG. 2 applied in the present embodiment. Then only 16 locations have changed. When driving the load capacitance of the address input of the memory, the frequency of charging and discharging the load capacitance increases as the number of signal changes per unit time increases, resulting in an increase in power consumption. In this example, the power consumption can be reduced by about １ ／.

[0018]

According to the memory storage device of the present invention, only one bit of the address indicating bit changes at any time. Therefore, generation of noise can be greatly suppressed, and adverse effects on analog circuits can be prevented. Therefore, if such a waveform storage device is applied to a measuring instrument such as a digital oscilloscope, the reliability of the device is improved.

Further, as described above, any one of the bits indicating the address changes at any time.
The frequency of charging and discharging the load capacity is reduced, and power consumption can be significantly reduced. Therefore, when used in a battery-driven digital oscilloscope or the like, there is a very great effect, and the usable time can be greatly extended.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart for explaining a change in a memory address in the embodiment of the present invention.

FIG. 3 is a time chart showing a change in a memory address in the related art.

FIG. 4 is a block diagram illustrating the operation of the related art.

[Explanation of symbols]

1,2 attenuator circuit, 3,4 amplifier, 5,6
A / D converter, 7, 8 memory, 9 Gray code memory address counter circuit, 10: time base circuit, 1
1: Memory address counter circuit

Claims (2)

[Claims] 1. A waveform storage device in which an input signal is AD-converted and stored in a memory, wherein each time the memory stores data of one address, a gray code memory in which a hamming distance of preceding and succeeding address values becomes one. A waveform storage device wherein addresses are sequentially generated and stored in a memory in the order of the addresses. 2. An attenuator circuit for level-converting an input signal and an amplifier at the next stage, an A / D converter for converting the input signal converted to the arbitrary level into digital data, and conversion by the A / D converter. A memory for storing the waveform data of the input signal, a memory address counter for generating an address of the memory, a memory address counter, the A / D converter, and a time base circuit for supplying a clock to the memory. In the waveform storage device, each time the memory stores data of one address, the memory address counter sequentially generates a gray code memory address in which the hamming distance of the preceding and following address numerical values becomes 1, and stores the waveform data in the order of the addresses. A waveform storage device storing the data in the memory.