JP3156152B2 - Amplitude probability distribution measurement device - Google Patents

Amplitude probability distribution measurement device

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Publication number
JP3156152B2
JP3156152B2 JP34064396A JP34064396A JP3156152B2 JP 3156152 B2 JP3156152 B2 JP 3156152B2 JP 34064396 A JP34064396 A JP 34064396A JP 34064396 A JP34064396 A JP 34064396A JP 3156152 B2 JP3156152 B2 JP 3156152B2
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data
output
measurement
converter
means
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JPH10170574A (en
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政治 内野
晴彦 細谷
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アンリツ株式会社
株式会社環境電磁技術研究所
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Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scale for statistically evaluating an electromagnetic environment, which is an amplitude probability distribution (hereinafter referred to as APD) of an electric field strength of an interference wave or the like. The present invention relates to a technique for simplifying the configuration of an amplitude probability distribution measuring device for measuring a time rate at which the level of an envelope of a signal is equal to or higher than a preset threshold value and for efficiently performing the measurement.

[0002]

2. Description of the Related Art In a conventional electromagnetic environment measurement, a carrier frequency of 1
In order to evaluate the effect of the frequency band below GHz on analog communication, a quasi-peak value, an average value, and the like of a signal envelope were measured. However, in order to evaluate the influence of an interfering wave on wideband digital communication in a frequency band exceeding 1 GHz, which is expected to increase in the future, it is necessary to measure a statistical parameter of an interfering wave envelope.

The above-mentioned APD is one of the statistical parameters, and the following equation P (e i ) = (1 / T) Σt k (e i ) (t k (e i ) is a threshold voltage e i Over time,
T is a measurement time).

In order to measure the APD, conventionally,
An envelope signal of an interference wave detected by a spectrum analyzer, a field strength meter, or the like is input to an APD measuring device 10 shown in FIG.

The APD measuring device 10 comprises a measuring unit 11 and an arithmetic processing unit 18.
Includes a signal V inputted from the input terminal 11a, the threshold voltages e 1, e 2 having different values output from the threshold voltage generating circuit 12, ..., each voltage comparator and e m 13 1 ~ 13
Each is compared by m . Each voltage comparator 13 1 to 1
3 m, only then outputs the count enable signal to the binary counter 14 1 to 14 m while the input signal V exceeds the respective threshold, the binary counter 14 1 to 14 m is the count enable signal While receiving the clock signal, a clock signal having a constant period Tc output from the clock signal generator 15 is counted.

Therefore, the counting result of each of the binary counters 14 1 to 14 m after the lapse of the measuring time T is determined by the input signal V
There threshold voltages e 1, e 2 between the time T, ... would represent respectively the sum of time that exceeds the e m.

[0007] The output of the binary counter 14 1 to 14 m is
The data is connected to the data bus 16 in parallel and output to the interface circuit 17.

[0008] The interface circuit 17 is connected to an arithmetic processing unit 18 constituted by a personal computer or the like. The arithmetic processing unit 18 controls the measurement of the measuring unit 11, reads out the measurement result, calculates and displays the APD.

That is, the arithmetic processing unit 18 causes the measuring unit 11 to measure the measuring time T, and when the measurement is completed, each of the binary counters 14 1 to 14 connected to the data bus 16. The counting results of m are sequentially read out, the ratio of each counting result to the time T is obtained, converted to display data, and displayed on a display screen (not shown) as a graph to enable evaluation of the electromagnetic environment.

[0010]

However, when the conventional APD measuring apparatus as described above attempts to achieve high amplitude resolution and time resolution, the following problems occur.

That is, in order to increase the amplitude resolution in the above-mentioned conventional APD measuring apparatus, when the difference between the threshold voltages is reduced and the number of thresholds is increased, the voltage comparator and the binary counter are correspondingly increased. Must be increased. For example, when setting the threshold value in 100 steps, it is necessary to provide 100 voltage comparators and 100 binary counters. This not only increases the configuration of the measuring unit but also increases power consumption. For example, it is difficult to realize a portable APD measuring device.

Further, if the 100 binary counters are connected to the common data bus as described above, the capacitance of the bus may increase abnormally, and the measurement data may be read out normally. It becomes impossible or the reading speed becomes extremely slow.

In order to increase the time resolution in the above-mentioned conventional APD measuring apparatus, not only a high-speed voltage comparator but also a high-speed counter having a large number of digits must be used. For example, if the cycle Tc of the clock signal is 20 nanoseconds, even if the measurement time T is 1 second, the number of times of sampling is 5 × 10 7 times, which is necessary for counting up to 5 × 10 7. A binary counter of digits is required. However, in such a counter having a large number of digits, a delay that is a multiple of the delay time of each digit occurs in the entire counter, and this delay limits the operation speed of the entire device. Realizing the operation speed is extremely difficult at present.

Further, in the above-mentioned conventional APD measuring apparatus, the next measurement cannot be started until all the measurement data is read out, and the interference wave generated while reading out the measurement data is overlooked. Problem.

SUMMARY OF THE INVENTION The present invention has been made to solve these problems, and it is possible to measure a high amplitude resolution with a small size and low power consumption, and an amplitude probability that enables a measurement with an extremely high time resolution. It is an object to provide a distribution measuring device.

[0016]

To achieve the above object, an amplitude probability distribution measuring apparatus according to claim 1 of the present invention comprises: 2 m storage circuits capable of storing and changing n-bit data; A which samples an input signal, converts it into m-bit parallel data, and sequentially outputs the converted data as data for selecting one of the 2 m storage circuits.
/ D converter and the A / D converter of the 2 m storage circuits.
Data transition means for transitioning the data stored in the storage circuit selected by the output data of the D converter to the next stage data by a linear logic circuit corresponding to an n-th primitive polynomial, and the A / D converter Measurement data reading means for sequentially reading data stored in the 2 m storage circuits as measurement data after sampling has been performed for a predetermined measurement time; and pre-determined reference data in a transition process of the n-th primitive polynomial. Therefore, the transition count output which stores the data at the time of the transition and the transition count value from the reference data in association with each other, and sequentially outputs the transition count value corresponding to the measurement data read by the measurement data reading means. Based on the number of transition times for each storage circuit output from the number-of-transitions output means.
An amplitude probability distribution of the input signal with respect to a threshold voltage of the D converter is obtained.

According to a fourth aspect of the present invention, there is provided an amplitude probability distribution measuring apparatus capable of storing and changing n-bit data.
and m storage circuits, converts the input signal to the sampled m-bit parallel data, the converted A / D converter for sequentially outputting as data for selecting one of the 2 m storage circuit data And the data stored in the storage circuit selected by the output data of the A / D converter among the 2 m storage circuits, from the power of 2 to 1
The subtracted value (2 ni -1) is relatively prime to become and the sum (n 1 + n 2 + ... + n r) is divided into equal numbers of bits of data to the number n, the number of bits of the respective divided data A plurality of linear logic circuits corresponding to primitive polynomials each having an order of: data transition means for transitioning to the next stage of data, and the 2 m pieces of data after the A / D converter performs sampling for a predetermined measurement time. A measurement data reading means for sequentially reading data stored in the storage circuit as measurement data; and data obtained by previously shifting predetermined reference data in accordance with the transition process of each primitive polynomial, and a transition time from the reference data. Numerical values are stored in association with each other, and a plurality of transition count values respectively corresponding to the divided data of the measurement data read by the measurement data reading means are stored. Based on a plurality of transition count values output from the transition count output unit, the storage circuit storing the measurement data that is the basis of the transition count is used for the predetermined measurement time. Frequency calculation means for calculating the number of times selected by the output data of the A / D converter as frequency data corresponding to the storage circuit, and based on the frequency data calculated by the frequency calculation means, An amplitude probability distribution of the input signal with respect to a threshold voltage of the A / D converter is obtained.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating a configuration of an APD measurement device 20 according to a first embodiment that achieves high amplitude resolution with a simple configuration. In FIG. 1, the APD measuring device 20 includes a measuring unit 21 and an arithmetic processing unit 40.

A short signal V (hereinafter, referred to as a signal V) detected by a spectrum analyzer or a receiver for measuring electric field strength is input to an A / D converter via an input terminal 21a of a measuring section 21.
Input to the converter 22. The A / D converter 22 samples the signal V in synchronization with a clock signal C output at a predetermined period Ts (for example, 20 nanoseconds) from the clock signal generator 23, and has a predetermined amplitude resolution of 2 m (for example, m = 8). ) Is converted into parallel data A and sequentially output. A / D
The width of quantization of the transducer 22 and .DELTA.e, when a voltage when sampled signal V to M-th and E M, the data A output from the A / D converter 22 when dividing E M at .DELTA.e (Remainder is truncated) is represented by a binary number.

The m-bit data output from the A / D converter 22 is supplied to the memory 2 via a data switch 24.
5 is input to the address terminal Ad.

The data changeover switch 24 is, for example, 2: 1
Of the A / D converter 22 during measurement by switching control from the arithmetic processing unit 40.
Is input to the address terminal Ad of the memory 25, and when the measurement is completed and the measurement data is read, the address data from the arithmetic processing unit 40 is input to the address terminal Ad.

The memory 25 constitutes the storage circuit of this embodiment, and is an I / O separated type static RAM having a data output terminal O and a data input terminal I which are independent from each other, in addition to the address terminal Ad. Composed,
A storage circuit for storing n-bit (for example, 26-bit) data includes a set corresponding to at least the amplitude resolution of the A / D converter 22 (for example, if the resolution is 8 bits, 25
6 sets).

When the read signal R is input, the memory 25 outputs the data stored at the address selected by the data input to the address terminal Ad at that time from the data output terminal O in parallel, and writes the data. When the signal W is input, the data input to the data input terminal I is written to the address selected by the data input to the address terminal Ad at that time.

Between the data output terminal O and the data input terminal I of the memory 25, n output from the data output terminal O
A data conversion circuit 2 that converts bit data into different n-bit data and inputs the data to a data input terminal I of the memory 25
6 are connected.

The data conversion circuit 26 forms a data transition means of this embodiment together with a rewrite control circuit 31 described later, and converts the n-bit data output from the memory 25 into Gn = 1 + h 1 x + h 2 x 2 + .. + H n-1 x n-1 + x n (1) (where the coefficients h 1 to h n-1 are 0 or 1) are converted into different data at the next stage determined by the n-th primitive polynomial. Output.

Before explaining the details of the data conversion circuit 26, the principle of data conversion using primitive polynomials will be described.

The input n-bit data D is a column vector D = (d 1 , d 2 ,..., D n ), and the converted data D ′ is a column vector D ′ = (d 1 ′, d 2 ′, …,
d n ′), the column vectors D and D ′ are square matrices Q with the first and second coefficients of the second and subsequent items of the above equation (1).
n ′, D ′ = Qn · D, that is, the following equation (2)

(Equation 1) Is converted so as to satisfy the relationship. Here, the converted data d 1 ′ to d n ′ are the results of a matrix operation modulo 2 (0 when the sum is even, 1 when the sum is odd).

When such data conversion is performed, input data and output data have a one-to-one relationship unless data of all n bits is 0, and the type of the data is two.
n− 1. Then, if as the converted data is input as the next input data for column vector D 0 of the initial data, the column vector D k obtained by the conversion of the k-th, depending Qn k · D 0 can get.

If the column vector D 0 of the initial data is known, the conversion results D 1 , D 2 ,..., Ds up to k = 1, k = 2,..., K = 2 n −1 (= s) are also obtained. I know in advance. Therefore, the conversion results D 0 , D 1 , D 2 ,.
If s is stored in a table in advance, and the value of k corresponding to the data in the memory 25 after the measurement is completed is read from the table, the number of times each address of the memory 25 is selected can be determined.
The amplitude frequency of the signal V input to the A / D converter 22 is known.

Assuming that n is 26, for example, as described above, the primitive polynomial is given by Gn = 1 + x 2 + x 6 + x 26. The capacity of the table corresponding to this primitive polynomial is about 210 Mbytes or more. Therefore, it is difficult to configure the memory with a normal memory. Therefore, in this embodiment, a value (2 ni −1) obtained by subtracting 1 from a power of 2 in n-bit data is relatively prime, and the sum (n 1 + n) is obtained.
2 +... + N r ) is divided into data of the number of bits where n is equal to n. For example, 26-bit data is converted into 7-bit (n
1 = 7), 9 bits (n 2 = 9), 10 bits (n 3 =
The data is divided into the data of 10) to reduce the capacity of the table. However, in the case of such division, frequency data cannot be obtained by simply reading the value of k corresponding to the 7-bit, 9-bit, and 10-bit data read from the memory 25 after measurement from each table. ,
As described above, since the value obtained by subtracting 1 from the power of 2 is relatively prime for the number of bits of each divided data, the frequency data can be obtained by a method called the remainder number system or the Chinese remainder theorem.

Hereinafter, a specific example of the data conversion circuit 26 will be described with reference to FIG.
It will be described based on. The data conversion circuit 25 includes a 7th-order primitive polynomial (1 + x + x 7 ) and a 9th-order primitive polynomial (1 + x
4 + x 9 ) and three sets of linear logic circuits 27 to 29 corresponding to the tenth-order primitive polynomial (1 + x 3 + x 10 ) respectively perform 26-bit data conversion.

That is, the linear logic circuit 27 converts 7-bit input data based on the 7th-order primitive polynomial (1 + x + x 7 ).
7-bit data up to the 7th bit (d 0, d 1, ... , D
6 ) is latched by the latch circuit 27a, and the latch data d 0 and d 1 of the first bit and the second bit are EXOR circuit 2
Type and 7b and the output converted data d 6 of the 7-bit ', second to seventh bits of the latched data d 1, d
, ... , D 6 are shifted by 1 bit, respectively.
Bit conversion data d 0, d 1, ... , D 5 ′,
The data is input to the first to seventh bits of the data input terminal I of the memory 25.

In the linear logic circuit 27, the first row corresponds to the coefficient of the seventh-order primitive polynomial (1 + x + x 7 ) (1000
Will be doing the conversion of data using the square matrix Q 7 serving as 001), by entering the converted data as the next input data, 7-bit whole excluding the data of 0 (2 7 -1 7) Different types of 7-bit data are generated in a predetermined order.

The linear logic circuit 28 converts 9-bit input data based on a ninth-order primitive polynomial (1 + x 4 + x 9 ).
9-bit data up to the 16th bit (d 7, d 9, ...)
, d 15 ) are latched by a latch circuit 28 a, and the eighth and twelfth bit latch data d 7 and d 11 are EXORed.
The output was the first 16-bit conversion data d 15 'is input to the circuit 28b, the ninth to 16-bit latch data d
8, d 9, ... , D 15 are shifted by 1 bit each
To the 15th bit of conversion data d 7, d 8, .
, d 14 ′, and the eighth through eighth data input terminals I of the memory 25.
Input to the 16th bit.

In this linear logic circuit 28, the first row corresponds to the coefficient of the ninth-order primitive polynomial (1 + x 4 + x 9 ) (000).
Will be doing the conversion of data using the square matrix Q 9 to be 100001), by configuring to enter the converted data as the next input data,
(2 9 -1) generated in the order determined different types of 9-bit data.

Similarly, the linear logic circuit 29 converts 10-bit input data based on the 10th-order primitive polynomial (1 + x 3 + x 10 ), and converts the 17-th to 26-th bits output from the memory 25. 10-bit data (d 16,
d 17, ..., and latches the d 25) in the latch circuit 29a, the first
7-bit and 20-bit latch data d 16 and d 19
The Enter the EXOR circuit 29b and its output and the 26-bit conversion data d 25 ', latch data d 17 of the first 18 to second 26 bits, d 18, ..., the shifting each one bit of the d 25 17 To the 25th bit conversion data d 16, d
17 ', ..., d 24' and, data input of the memory 25 terminal I
To the 17th to 26th bits.

In this linear logic circuit 29, the first row corresponds to the coefficient of the 10th-order primitive polynomial (1 + x 3 + x 10 ) (00
Will be doing the conversion of data using the square matrix Q 10 to be 10000001), by configuring to enter the converted data as the next input data, different (2 10 -1) types 10 Bit data is generated in a fixed order.

The above-described linear logic circuits 27 to 29
Uses a primitive polynomial consisting of three terms,
By using the polynomial of the minimum number of terms in this way, the actual circuit configuration can be simplified (the number of EXOR circuits is small).

The above, 2 7 -1 (= 127), 2 9 -
Since 1 (= 511) and 2 10 -1 (= 1023) are relatively prime integers, the data conversion circuit 26 calculates (2 7 -1)
・ (2 9 -1) ・ (2 10 -1) ways (66389631)
Data), which is larger than the maximum count value of 5 × 10 7 required when measuring for 1 second with a time resolution of 20 nanoseconds as described above. Note that the latch circuits 27a to 29a latch input data by a common latch signal L.

The switch 30 connected to the data input terminal I of the memory 25 in FIG. 1 is used to set the initial data (all bits 1) as a reference in the memory 25 at the start of measurement.

Reading of data from the memory 25 and writing of converted data are performed by the rewrite control circuit 31.

The rewrite control circuit 31, as shown in FIG.
Clock signal C output from clock signal generator 23
During one cycle Ts, the read signal R to the memory 25,
A latch signal L for the data conversion circuit 26 and a write signal W for the memory 25 are sequentially output.

Therefore, the data stored at the address selected by the data output from A / D converter 22 is output from memory 25 to data conversion circuit 26 by read signal R from rewrite control circuit 31. The data is converted into different data of the next stage, and the converted data is written by the write signal W instead of the previous data.

The operation of the rewrite control circuit 31 is performed by the arithmetic processing unit 40 connected via the interface circuit 32.
Is controlled by

The arithmetic processing unit 40 is constituted by, for example, a personal computer, and its functions are shown as blocks in FIG.

The arithmetic processing section 40 is provided with a measurement control section 41 for controlling the measuring operation of the measuring section 21.

That is, when receiving the measurement request, the initial data setting means 42 connects the data changeover switch 24 to the interface circuit 32, connects the switch 30 to the initial data, and writes the write signal W to the memory 25. At the same time, address data is input from 0 to 2 m -1 to set initial data in the memory 25.

When the processing of the initial data setting means 42 is completed, the measurement instructing means 43
4 is connected to the A / D converter 22, the switch 30 is connected to the data conversion circuit 26, and the rewrite control circuit 31 is operated for a predetermined measurement time T. By this processing, the memory 2
5 are stored in the A / D converter 22 from the initial data.
, The data that has transitioned by the number of times selected in the output data is stored.

When the measurement is completed, the measurement data reading means 44 switches the data changeover switch 24 to the interface circuit 32 side, stops the operation of the rewrite control circuit 31, and sends the address data together with the read signal R to the memory 25. 0 to 2 m -1 is input, and the measurement data stored in the memory 25 is read out in order of address.

The measurement data read from the memory 25 is input to the arithmetic processing unit 40 via the interface circuit 32. As described above, the arithmetic processing unit 40 is provided with the conversion tables 45, 46, 47 corresponding to the respective linear logic circuits 27 to 29 of the data conversion circuit 26.

The conversion table 45 to 47, constitutes a transition count output means of this embodiment, the conversion table 45, k a th from initial data Da 0 as a reference, based on the 7-order primitive polynomial (K a = 0 to 126), each data Da 0 , Da 1 , Da 2 ,..., Da
126 is stored are associated with each value k a, the first 26 bits of the measurement data read out from the memory 25
And it outputs the value k a corresponding to to seventh bits of data.

[0052] the conversion table 46, k b-th from the initial data Db 0 based on the 9-order primitive polynomial (k b = 0
510), the respective data Db 0 , Db 1 , Db
2, ..., Db 510 is stored are associated with each value k b, eighth measurement data read from the memory 25
And it outputs the value k b corresponding to ~ 16 bits of data.

The conversion table 47 contains k c -th (k c = k ) times from the initial data Dc 0 based on the tenth-order primitive polynomial.
0 to 1022), Dc 0 , Dc 1 ,
Dc 2 ,..., Dc 1022 are stored in association with each value k c , and output a value k c corresponding to the 17th to 26th bits of the measurement data read from the memory 25.

Here, the number of times F that the input measurement data is actually rewritten by the data conversion circuit 26 (the address of the memory 25 storing the measurement data is A / D
The number of times selected by the output data of the converter 22);
FIG. 4 shows the relationship between the output values k a , k b , and k c of the conversion tables 45 to 47.

In this figure, as described above, 127
(= 2 7 -1), 511 (= 2 9 -1), and 1023 (=
Since 2 10 -1) is relatively prime, each of the conversion tables 45 to 4
The value k a outputted from 7, k b, the k c are both equal ranges up to 0 to 126. Therefore, if k a = k b = k c is satisfied in this range, the value directly represents the actual number of rewrites F.

However, the true rewrite frequency F cannot be directly obtained from the values k a , k b , and k c output from the conversion tables 45 to 47 for measurement data whose rewrite frequency F exceeds 126.

Therefore, in this embodiment, the values k a , k b , and k c output from the conversion tables 45 to 47 are input to the frequency calculating means 48, and a method called a remainder number system or a Chinese remainder theorem is used. The actual number of rewrites F is obtained by using this.

The following is one of the operation procedures of the above method, Gar
The ner method is shown. That is, the frequency calculation means 48 determines in advance m 1
= 2 7 -1, m 2 = 2 9 -1 and m 3 = 2 10 -1 values,
m 1 · m 2 values, the values of m 1 · m 2 · m 3 , and the following congruences (3) U ij · m i ≡1 (mod m j) ...... (3) ( where, (mod y) indicates three coefficients U ij (i <j) satisfying the remainder when the operation result is divided by y.

Then, according to the following recurrence formula, k a ,
k b, k c from v a, v b, calculates the v c. v a = k a v b = (k b -v a) U 12 mod m 2 v c = [(k c -v a) U 13 -v b ] U 23 mod m
3 is then determined by calculating the following equation rewriting number F (4) F = (v a + m 1 v b + m 1 m 2 v c) mod m 1 m 2 m 3 ...... (4).

The frequency calculation means 48 performs the above calculation sequentially on the values k a , k b , and k c output from the conversion tables 45 to 47, and obtains each address value (0 to 2 m
The calculation results F (0), F (1),..., F (2
m- 1) is stored in the frequency data memory 49 as frequency data for each threshold voltage.

For each frequency data stored in the frequency data memory 49, the amplitude probability calculating means 50 calculates the following equation (5) P (zΔe) = (1 / N) ΣF (j) (5) Δe is the quantization width of the A / D converter 22, N is the number of times of sampling performed during the fixed time T, and the symbol Σ is j =
The calculation of z〜2 m −1) is performed for z = 0 to 2 m −1, and the time rate at which the signal V exceeds each threshold voltage zΔe, that is, the APD is obtained.

The amplitude probability distribution of the signal V obtained in this way is output to the display control means 51, and is graphically displayed on the screen of the display 52, for example, as shown in FIG.

As described above, in the APD measuring apparatus of this embodiment, 2 m storage circuits are constituted by the static RAM type memory 25, and the data content of each storage circuit is constituted by a plurality of linear logic circuits. Since the transition is performed by the data conversion circuit 26 and the rewrite control circuit 31, it is possible to mount the device in an extremely small scale as compared with a conventional device using a binary counter, to reduce the power consumption, to reduce the size, and to realize a high amplitude resolution. APD measuring device can be provided,
Particularly convenient for portable use. In addition, since the measurement result for each threshold voltage is read from the data output terminal of the memory 25, even if the amplitude resolution is increased, the capacitance of the reading bus does not increase, and the measurement result is stable. And can be read at high speed.

[0064]

In the first embodiment, the static RAM type memory 25 constitutes 2 m storage circuits, and the storage contents of each storage circuit are converted and rewritten by a common data conversion circuit. In the above, an example of the APD measuring apparatus which is small and capable of measuring high amplitude resolution with low power consumption has been described. At present, the above speed is the limit. Then, next, APD that can obtain higher time resolution
A measuring device will be described as a second embodiment. In the following description, the same circuits as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 6 shows the configuration of an APD measuring device 60 according to the second embodiment. The APD measuring device 60 includes a measuring unit 61 and an arithmetic processing unit 70 as in the case of the above-described APD measuring device 20. The measuring unit 61 converts a signal V input from an input terminal 61a into an A / D converter. The data is converted into m-bit (for example, 8-bit) parallel data A by 22 and output to the decoder 62.

The decoder 62 has 2 m (= M) output terminals, and outputs the value indicated by the input data A (0 to 2 m).
A selection signal is output from the output terminal corresponding to -1).

The output terminals of the decoder 62 are connected to storage conversion circuits 63 1 to 63 M in which the storage circuit of the present invention and the data transition means are integrally formed.

The storage conversion circuits 63 1 to 63 M are provided with transfer shift registers 67 1 to 67 M for serially transferring measurement data.

FIG. 7 shows a specific circuit configuration of one set of the storage conversion circuit 63 and the transfer shift register 67 in the case where n is 30 which is 4 bits larger than 26 bits in the first embodiment. I have. As shown in the figure, the storage conversion circuit 63 stores three bits of 30-bit data and rewrites the data.
It is divided into 65 and 66.

The linear logic circuit 64 has a ninth-order primitive polynomial (1
+ X 4 + x 9 ) to rewrite 9-bit data. The output of the final stage of the nine-stage shift register 64a and the output of the fifth stage counted from the final stage are input to the EXOR circuit 64b. , The output of which is input to the first stage.

The linear logic circuit 65 rewrites 10-bit data based on the 10th-order primitive polynomial (1 + x 3 + x 10 ). The output of the last stage of the ten-stage shift register 65a and the counting from the last stage are performed. EX with the output of the fourth stage
It is configured to input to the OR circuit 65b and input its output to the first stage.

The linear logic circuit 66 rewrites 11-bit data based on the 11th-order primitive polynomial (1 + x 2 + x 11 ). EX with the output of the third stage
It is configured to be input to the OR circuit 66b and to input the output to the first stage.

Each of shift registers 64a to 66a sets initial data (for example, all 1-bit data) as a reference upon receiving set signal S from arithmetic processing unit 70, and receives a selection signal from decoder 62. When the clock signal C falls, the data is shifted one stage from the first stage to the next stage, and the data is shifted to the next stage.

Therefore, the relationship of the equation (2) between the data of each stage before the transition of each of the linear logic circuits 64-66 and the data of each stage after the transition is the same as in the first embodiment. After the measurement time T has passed, the number of transitions from the initial data can be obtained from the measurement data held in each of the linear logic circuits 64-66.

The transfer shift register 67 stores the measured time T
Is used to latch and output the data held in each of the linear logic circuits 64 to 66 after the elapse of the period, and is constituted by a 30-stage shift register of a parallel input serial output type. The transfer shift register 67 receives the transfer set signal S T from the arithmetic processing unit 70, latches the output data of each stage of each shift register 64A~66a, for transferring data of 30 bits and the latch one bit for each receive the clock signal C T serially outputs.

Note that the M transfer shift registers 67 1
To 67 M are be connected in series as a whole, since the shift of data with a common transfer clock signal C T, the measurement data of the M storage converter 63 1 to 63 M is, M-th transfer shift it can be read from the register 64 M through one data line.

The measurement data is sent to the arithmetic processing unit 70 via the interface 68. The arithmetic processing unit 70 controls the operation of the measurement unit 61 by the measurement control unit 71. Upon receiving the measurement request, the initial data setting means 72 of the measurement control section 71 stops the operation of the decoder 62 and sets the initial data in each of the storage conversion circuits 63 1 to 63 M ,
When the setting of the initial data is completed, the measurement command means 73 causes the decoder 62 to be in the operation state for the measurement time T, and when the measurement time ends, the storage conversion circuits 63 1 to 63 M
During the measurement time, the A / D converter 22
, The data that has transitioned by the number of times selected in the output data is stored.

Then, the measurement data reading means 74
Immediately after the transfer is completed, each transfer shift register 671~ 67
MSet signal S for transferTIs output to each memory conversion circuit.
63 1~ 63mMeasurement data stored in the
Then, each transfer shift register 671~ 67MTurn to
Transmission clock signal CTIs output 30 × M times and the measurement data
The data is taken into the arithmetic processing unit 70.

The measurement data input from the measurement unit 61 to the arithmetic processing unit 70 is converted into parallel data by a serial / parallel conversion unit 75 in units of 30 bits, of which the first to ninth bits are input to the conversion table 76. Then, the 10th to 19th bits are input to the conversion table 77, and the 20th to 30th bits are input to the conversion table 78.

The conversion table 76 has a value k a indicating how many times the input 9-bit data has changed from the initial data.
The stores in advance in correspondence to each 9-bit data, and outputs the value k a corresponding to the input data.

The conversion table 77 has a value k indicating how many times the input 10-bit data has shifted from the initial data.
b is stored in advance corresponding to each 10-bit data, and a value k b corresponding to the input data is output.

The conversion table 78 has a value k indicating how many times the input 11-bit data has transitioned from the initial data.
c is stored in advance corresponding to each of the 11-bit data, and outputs a value k c corresponding to the input data.

The frequency calculating means 48 converts each conversion table 76
Calculations similar to those in the first embodiment are sequentially performed on k a , k b , and k c output from .about.78 to obtain frequency data F (0), F for each of the storage conversion circuits 63 1 to 63 M. (1),
.., F (2 m -1) are obtained and stored in the frequency data memory 49, and the amplitude probability calculating means 50 performs the calculation of the above equation (5) for each frequency data stored in the frequency data memory 49, and obtains the signal V Is the time rate at which each exceeds the threshold voltage zΔe,
That is, the APD is obtained.

Note that the APD measuring device 60 sets each of the storage conversion circuits 63 1 to 63 M immediately after the measurement time T ends.
Since the data transferred to the transfer shift register 67 1 to 67 M, it is possible to perform the next measurement while reading data from the transfer shift register 67 1 to 67 M.

[0085] That is, the 30-bit data M (= 2 m) pieces time required to serially output, the period of the transfer clock signal C T and 8 m on even about 8 ms as 1 microsecond Since the measurement is completed, the transfer of the data and the calculation of the APD can be performed with a sufficient margin during the measurement time of one second. Therefore, measurement can be performed continuously, measurement without dead time is possible, and it is not necessary to miss an intermittently generated interference wave.

When such continuous measurement is performed, the arithmetic processing unit 70 does not stop the operation of the decoder 62 except for the setting of the initial data, and each time the measurement time elapses, the transfer set signal S T Is output to read out the measurement data. In this case, after calculating the difference between the previous frequency data and the current frequency data, the amplitude probability may be calculated. Also,
The display control unit 79 may display the previous measurement result on the display 52 while sequentially updating the previous measurement result with the next measurement result, or may display a plurality of measurement results three-dimensionally including a time axis.

As described above, the APD measuring apparatus 60 according to the second embodiment measures the frequency for each threshold voltage by the linear feedback type linear logic circuit including the shift register. There is no limit due to the delay time of the multi-digit counter, so that measurement can be performed with extremely high time resolution, and the measured data is stored and read out to the transfer shift register when the measurement time ends. Continuous measurement can be performed with almost no dead time, and measurement data can be read at high speed.

The APD measuring device 60 of the second embodiment
Is intended for high-speed operation and enables continuous measurement. However, as in a measuring unit 81 shown in FIG. 8, RAM-type memories 82 and 92, data conversion circuits 83 and 93, and latch circuits 84 and 94 , Two rewrite control circuits 86 and 96 are provided, and a first memory for alternately supplying the output data of the A / D converter 22 to the first memory 82 and the second memory 92.
And a second data changeover switch 98 for switching between the measurement data of the first memory 82 and the measurement data of the second memory 92 and sending the data to the arithmetic processing section. 2 data changeover switches 97 and 98
Is switched every time the measurement time T elapses,
As shown in FIG. 9, while one of the memories is performing measurement, reading, calculation, and initial data setting of measurement data can be performed from the other memory, and continuous measurement can be performed with a margin.

In this embodiment, a general memory having a common data input / output terminal is used, and each of the latch circuits 84 and 9 is used when reading data from the memory.
4 is in a high impedance state. Also,
As described above, the latch circuits 84 and 94 are connected to the data conversion circuit 8.
When provided on the output side of 3, 93, the latch circuits 27a to 29a shown in FIG. 2 are unnecessary, and their inputs and outputs may be directly connected.

In each of the above embodiments, the data transition means divides n-bit data. However, when high amplitude resolution is required but time resolution is not so required, that is, n is small and m is small. If it is large, the capacity of the conversion table may be small, and the data may be transitioned using an n-th primitive polynomial. Even in this case, it is more advantageous in mounting than increasing the number of counters as in the conventional device.

In the measuring section of FIG. 8, the RAM
In the measurement unit using the shift register type storage circuit, two sets of the storage circuit, the data transition means, and the measurement data reading means are provided to alternate the data of the A / D converter. May be given.

In the case of multi-point measurement, for example, in which signals of a plurality of terminals of an IC are measured simultaneously, the interface 68 of the measuring section 61 is externally provided as in a measuring section 100 shown in FIG. Using a plurality of provided measuring units 61 ',
If the inputs and outputs of the transfer shift register are connected in series, a large amount of measurement data for the signals V 1 to V n input to the input terminals 100 a can be easily taken into the arithmetic processing unit 70.

In each of the embodiments described above, the measuring unit and the arithmetic processing unit are configured separately, but this does not limit the present invention. They may be provided in the same housing.

[0094]

As described above, according to the amplitude probability distribution measuring apparatus of the present invention, the data of the storage circuit selected by the output data of the A / D converter is converted to the next stage by the linear logic circuit corresponding to the primitive polynomial. Transition to different data of
When the measurement is completed, the number of transitions of the data of the storage circuit from the reference data is obtained, and the number of times the storage circuit is selected by the output data of the A / D converter within the measurement time is obtained. Because we calculate the probability distribution,
Compared to the counting method using a counter, it is possible to measure a high amplitude resolution with a small configuration and with low power consumption.

Further, the n-bit data stored in the storage circuit is divided into data of the number of bits in which a value obtained by subtracting 1 from a power of 2 is relatively prime and the sum thereof is n. The data is transited by primitive polynomials of the order corresponding to the number of bits, respectively, so that even if the time resolution is increased, the size of the apparatus does not need to be increased.

Further, in the amplitude probability distribution measuring device using a RAM type memory or a shift register as a storage circuit, it is not necessary to connect the read lines of each storage circuit in parallel. , And stable and high-speed reading can be performed.

Further, in the amplitude probability distribution measuring device in which the storage circuit and the data transition means are integrated by using a shift register, it is possible to measure a much higher time resolution. In the amplitude probability distribution measuring device that latches and outputs data by the transfer shift register, measurement can be performed continuously, and measurement without dead time can be performed. In addition, in the amplitude probability distribution measurement device in which the transfer shift registers are connected in series, the measurement data of each storage circuit can be read by one signal line,
High-speed reading becomes possible, and the device can be simplified.

Further, continuous measurement can be easily realized even if two sets of storage circuits, data transition means and measurement data readout units are provided to perform measurement alternately.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a main part of the first embodiment.

FIG. 3 is a time chart for explaining the operation of the main part of the first embodiment;

FIG. 4 is a diagram for explaining the operation of the main part of the first embodiment;

FIG. 5 is a diagram illustrating an example of a measurement result according to the first embodiment.

FIG. 6 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 7 is a circuit diagram of a main part of the second embodiment.

FIG. 8 is a block diagram showing a configuration of a main part of another embodiment of the present invention.

FIG. 9 is a timing chart for explaining the operation of another embodiment of the present invention.

FIG. 10 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a conventional device.

[Explanation of symbols]

 Reference Signs List 20 APD measuring device 22 A / D converter 23 Clock signal generator 24 Data changeover switch 25 Memory 26 Data conversion circuit 27-29 Linear logic circuit 31 Rewrite control circuit 40 Operation processing unit 45-47 Conversion table 48 Frequency operation means 50 Amplitude Probability calculation means 51 Display control means 52 Display

Continuation of the front page (56) References JP-A-1-297564 (JP, A) JP-A-62-88969 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) G01R 29 / 08 H04L 13/00 H04B 1/60-17/02

Claims (10)

(57) [Claims]
1. A storage circuit comprising: 2 m storage circuits capable of storing and changing n-bit data; and sampling an input signal, converting the converted data into m-bit parallel data, and converting the converted data into the 2 m storage circuits. An A / D converter that sequentially outputs as data for selecting any one of the following; and a storage circuit selected from output data of the A / D converter among the 2 m storage circuits. Data transition means for transitioning data to the next stage data by a linear logic circuit corresponding to an n-th primitive polynomial; and the 2 m storage circuits after the A / D converter performs sampling for a predetermined measurement time. Measurement data reading means for sequentially reading the data stored in the memory as measurement data; and data obtained when predetermined reference data is changed in advance according to a transition process of the n-th primitive polynomial. A transition count output unit that stores a transition count value corresponding to the measurement data read by the measurement data reading unit, wherein the transition count value is stored in association with the transition count value from the reference data, An amplitude probability distribution measuring device, wherein an amplitude probability distribution of the input signal with respect to a threshold voltage of the A / D converter is obtained based on a transition count value of each storage circuit output from an output unit.
Each of said storage circuits is constituted by an n-stage shift register; said data transition means, each time said storage circuit is selected by output data of said A / D converter, 2. The amplitude probability distribution measurement according to claim 1, wherein, among the outputs of the stages, the exclusive OR output of the stage corresponding to the n-th primitive polynomial is fed back to the first stage to transition the data to the next stage. apparatus.
3. The 2 m storage circuits are constituted by a RAM-type memory having an address of m bits, and the data transition means is configured to execute the A / D conversion among data stored in the memory. Means for reading data at the address selected by the output data of the device, means for converting the read data into data of the next stage by a linear logic circuit corresponding to the n-th primitive polynomial, and means for converting the converted data before conversion. And means for writing the same data to the same address.
An amplitude probability distribution measuring device as described in the above.
4. A 2 m storage circuit capable of storing and changing n-bit data, an input signal being sampled and converted into m-bit parallel data, and the converted data is stored in the 2 m storage circuits. An A / D converter that sequentially outputs as data for selecting any one of the following; and a storage circuit selected from output data of the A / D converter among the 2 m storage circuits. the data, minus one from the power of 2 (2 ni -1) is split becomes and the sum (n 1 + n 2 + ... + n r) to the equal number of bits of data to the number n relatively prime, Data transition means for causing each of the divided data to transition to data at the next stage by a plurality of linear logic circuits corresponding to a primitive polynomial having the number of bits as an order, and wherein the sampling by the A / D converter is performed for a predetermined measurement time period. Measurement data reading means for sequentially reading data stored in the 2 m storage circuits as measurement data after the data is read, and data obtained when predetermined reference data is changed in advance in accordance with the transition process of each primitive polynomial. And a transition count value from the reference data are stored in association with each other,
A transition count output unit that outputs a plurality of transition count values respectively corresponding to the divided data of the measurement data read by the measurement data read unit; and a plurality of transition count values output from the transition count output unit. The storage circuit, which stores the measurement data on which the number of transitions is based, is stored in the memory during the predetermined measurement time.
Frequency calculating means for calculating the number of times selected by the output data of the / D converter as frequency data corresponding to the storage circuit, and the A / D conversion is performed based on the frequency data calculated by the frequency calculating means. An amplitude probability distribution measuring device for determining an amplitude probability distribution of the input signal with respect to a threshold voltage of the detector.
5. The storage circuit comprises a plurality of shift registers each having a number of stages corresponding to the number of bits of each of the divided data, and the data transition means includes a memory for storing the output data of the A / D converter. Every time the shift register is selected, the exclusive OR output of the stage corresponding to each primitive polynomial among the outputs of each stage of each shift register is fed back to the first stage, and the data of each shift register is transferred to the next stage. The apparatus for measuring an amplitude probability distribution according to claim 4, wherein a transition is made.
6. The two- m storage circuit, two sets of said data transition means and two sets of said measurement data reading means are provided. Data switching means for alternately providing output data of the A / D converter at the predetermined measurement time intervals, while the output data of the A / D converter is input to one storage circuit side, Is read out, and while the output data of the A / D converter is input to the other storage circuit, the measurement data stored in one storage circuit is read out. The amplitude probability distribution measuring device according to claim 4 or 5, wherein:
7. The measurement data reading means includes an n-stage transfer shift register of a parallel input serial output type, and sets a parallel output of each stage of each shift register of the storage circuit in the transfer shift register. 6. An apparatus according to claim 5, wherein said set data is read out in series.
8. The transfer shift register for each of the storage circuits is connected in series as a whole so that measurement data stored in 2 m storage circuits can be read from the output of one transfer shift register. The amplitude probability distribution measuring device according to claim 7, characterized in that:
9. The 2 m storage circuits are constituted by a RAM-type memory having an address of m bits, and the data transition means is configured to execute the A / D conversion among the data stored in the memory. Means for reading data at an address selected by the output data of the device, and reading the read data by a value obtained by subtracting 1 from a power of 2 (2 ni
1) are disjoint and their sum (n 1 + n 2 +... +
means for dividing the divided data into data of a number of bits where nr ) is equal to the number n, and converting the divided data into data of the next stage by a plurality of linear logic circuits corresponding to a primitive polynomial having the degree of the bits. 5. The amplitude probability distribution measuring apparatus according to claim 4, further comprising: means for writing the converted data to the same address as the data before the conversion.
10. The apparatus according to claim 1, wherein two sets of said memory, said data transition means, and said data measurement means are provided.
Data switching means for alternately providing output data of the D converter to one memory and the other memory at predetermined time intervals is provided, while the output data of the A / D converter is input to one memory. Reading the measurement data stored in the other memory and reading the measurement data stored in the one memory while the output data of the A / D converter is input to the other memory. The amplitude probability distribution measuring apparatus according to claim 9, wherein:
JP34064396A 1996-12-05 1996-12-05 Amplitude probability distribution measurement device Expired - Lifetime JP3156152B2 (en)

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US6509728B1 (en) 1998-05-28 2003-01-21 Anritsu Corporation Spectrum analyzer having function of displaying amplitude probability distribution effectively
JP2002350498A (en) * 2001-05-29 2002-12-04 Advantest Corp Parallel processing method for semiconductor testing device and semiconductor testing device
WO2005076035A1 (en) 2004-02-09 2005-08-18 Anritsu Corporation Radar apparatus
CN101019033A (en) * 2005-01-11 2007-08-15 太阳诱电株式会社 Electromagnetic field distribution measuring method and apparatus thereof, computer program and information recording medium
JP4205070B2 (en) 2005-03-09 2009-01-07 アンリツ株式会社 Signal measuring apparatus and signal analyzing apparatus
JP2008039762A (en) * 2006-07-13 2008-02-21 National Institute Of Information & Communication Technology Electromagnetic disturbance wave measuring system, and selecting system using it
JP4812685B2 (en) * 2007-04-27 2011-11-09 アンリツ株式会社 APD measuring device and signal measuring device
JP5395685B2 (en) * 2010-01-19 2014-01-22 アンリツ株式会社 APD measuring device
JP5115938B2 (en) * 2010-02-25 2013-01-09 アンリツ株式会社 Interference determination circuit and interference determination method

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