JPH06230084A - Serial pattern generator - Google Patents

Abstract

PURPOSE:To cope even with different bit lenghts by reading bit lenght data from the second storage part by an address indicating part, dividing parallel data from the corresponding first storage part into bit lengths, and giving an address of the next data outputted by a parallel-serial converting part to the first and the second storage part. CONSTITUTION:The first storage part 1 stores parallel data having different bit lenghts, and the second storage part 2 stores bit length data corresponding to it. A parallel-serial converting part 3 converts the parallel data from the storage part 1 into serial data. An address indicating part 4 receives the bit length data from the storage part 2, and divides the parallel data of the corresponding storage part 1 into bit lenghts, and gives an address of the next data outputted by the converting part 3 to the storage parts 1 and 2. In this way, since the storage part 2 is arranged to store the bit length data corresponding to the parallel data having different bit lenghts, the serial data can be sent out in response to the parallel data having different bit lenghts.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial pattern generator of a test apparatus for testing a test object such as an LSI having a D / A (digital / analog) conversion function, and more specifically, a test. The present invention relates to a serial pattern generator capable of generating data to be given to an object with good operability.

[0002]

2. Description of the Related Art Conventionally, a memory of an LSI tester for testing an LSI including a D / A conversion function has been arithmetically processed by a DSP (digital signal processor) which is data given to the LSI as shown in FIG. Stores data. In the figure, the memory is 8 for one address.
Bits can be stored. The memory continuously stores one-code data of 5 bits. This 1-code data is used as digital data for testing the D / A converter. When D / A conversion is performed using these data groups, for example, a waveform as shown in FIG. 4 is formed. Here, x indicates which part of the waveform the digital data forms.

When data as a signal under test is applied to an LSI having a D / A conversion function from a memory for storing the above data, it is necessary to convert the data from parallel data to serial data. In such cases,
Conventionally, parallel / serial conversion was performed by a selector. For this reason, the DSP needs to take a long time to consider how to arrange the output data in the memory. As a countermeasure against the above, a configuration in which a storage unit having the same bit length as one code of data to be sent to the LSI is provided can be considered. However, when the control data and the digital data for forming the waveform are sent to the LSI, the bit lengths of the control data and the digital data may be different from each other, and the above countermeasure cannot be taken.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to easily write serial data as parallel data in a storage unit and to send serial data corresponding to parallel data having different bit lengths. It is to realize the generator.

[0005]

According to the present invention, a first storage unit for storing parallel data having different bit lengths and a bit length data corresponding to the parallel data stored in the first storage unit are stored. A second storage unit, a parallel / serial conversion unit that converts parallel data read from the first storage unit into serial data and outputs the serial data, and bit length data from the second storage unit The parallel data stored in the first storage unit corresponding to the long data is divided into bit lengths, and the address of the next data output from the parallel / serial conversion unit is stored in the first storage unit and the second storage unit. And an address designating section to be given to the section.

[0006]

According to the present invention, the address designating section reads the bit length data from the second storage section which stores the bit length data corresponding to the parallel data stored in the first storage section. Then, addresses are given to the first storage unit and the second storage unit in order to give the parallel / serial conversion unit parallel data of the first storage unit that is converted and transmitted as serial data.

[0007]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure,
A first storage unit 1 stores parallel data (or pattern data) having different bit lengths. The second storage unit 2 stores bit length data corresponding to the parallel data stored in the first storage unit 1. For example, the contents of address 0 in the first storage unit 1 and the second storage unit 2 are 16-bit parallel data and "1", respectively.
5 ". The contents with an address of 1 are 4-bit parallel data and" 3 ". That is, the first
The number of bits of valid data stored in one address in the storage unit 1 is the number stored in the same address as in the first storage unit 1 in the second storage unit 2. In the above example, "15" means a bit length "16" and "3" means a bit length "4". A parallel / serial conversion unit 3 converts the parallel data read from the first storage unit 1 into serial data and outputs the serial data. An address designating unit 4 receives bit length data from the second storage unit 2,
The parallel data stored in the first storage unit 1 corresponding to the bit length data is divided into bit lengths. Then, the address of the next data output from the parallel / serial conversion unit 3 is given to the first storage unit 1 and the second storage unit 2. In the address designating unit 4, reference numeral 41 denotes a counter, which receives the bit length data from the second storage unit 2, down-counts the bit length data and outputs the count value to the parallel / serial conversion unit 3. When the count value is "0", the count clock is output. An address generator 42 receives the count clock from the counter 41 and gives the address of the next data output from the parallel / serial conversion unit 3 to the first storage unit 1 and the second storage unit 2.

The operation of such a device will be described below.
FIG. 2 is a time chart showing the operation of the apparatus of FIG. In the figure, (a) is a clock, (b) is a count value of the counter 41, (c) is a count clock output by the counter 41, and (d) is the first storage unit 1 and the second storage unit 2. Address data to be given, (e) is pattern data which is parallel data read from the first storage unit 1, and (f) is serial data output from the generator.
The clock is input to the counter 41 and the count value is "
When it becomes "0", the count clock rises.
2 advances the address by one and sends it to the first storage unit 1 and the second storage unit 2. At this time, the address data
(N: integer). The first storage unit 1 sends pattern data whose effective data is 4 bits. Second storage unit 2
Sends out bit length data "3". The counter 41 starts counting from the count value “3” at the next clock and sends the count value “3” to the parallel / serial conversion unit 3. The parallel / serial converter 3 has a count value "
3 "is received and the third data bit" D3 "of the pattern data is sent out. Then, at the next clock, the counter 41 counts down and the count value is set to" 2 ". Receives the count value "2" and the second data "D" of the pattern data
2 "is sent out. These operations are counted value" 1,0 "
When the count value is "0", the count clock rises. Then, according to the count clock, the address generator 42 advances the address by one and sends it to the first storage unit 1 and the second storage unit 2. The above operation is repeated. Since the storage unit for storing the bit length data corresponding to the parallel data having different bit lengths is provided as described above, the serial data can be transmitted corresponding to the parallel data having different bit lengths.

Note that the present invention is not limited to this, and the parallel / serial conversion section may be configured to send parallel data in sequence as serial data at a clock. In that case, the address indication part
Instead of giving the count value to the serial conversion section, a configuration may be adopted in which the parallel / serial conversion section gives a load signal which is a signal for reading parallel data to be sent next.

[0010]

The present invention has the following effects. Since the storage unit for storing the bit length data corresponding to the parallel data of different bit lengths is provided, the serial data can be transmitted corresponding to the parallel data of different bit lengths. Further, since serial data can be sent in correspondence with parallel data having different bit lengths, one data can be stored at one address in the storage section. That is, since one data is stored in the storage unit for one address, data can be easily written in the storage unit.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the apparatus of FIG.

FIG. 3 is a configuration diagram of a memory of a conventional device.

FIG. 4 is a waveform diagram of a D / A converter.

[Explanation of symbols]

 1 1st memory | storage part 2 2nd memory | storage part 3 Parallel / serial conversion part 4 Address instruction part

Claims (1)

[Claims] 1. A first storage unit for storing parallel data having different bit lengths, and a second storage unit for storing bit length data corresponding to the parallel data stored in the first storage unit. A parallel / serial conversion unit that converts parallel data read from the first storage unit into serial data and outputs the serial data; and a first parallel-serial conversion unit that receives bit length data from the second storage unit and corresponds to the bit length data. An address designating section for dividing the parallel data stored in the storage section into a bit length and giving an address of the next data output from the parallel / serial conversion section to the first storage section and the second storage section. A serial pattern generator having: