JPH0879012A - Digital filter - Google Patents

Abstract

PURPOSE: To provide a digital filter by which an output waveform closer to an object value (design value) than that of a conventional filter is obtained. CONSTITUTION: The filter is provided with a correction data memory 14 arranged in parallel with a memory 10 in addresses of which corresponding to addresses d0 -dn of the memory 10 correction data corresponding to data stored in the memory 10 are respectively stored and an adder 18 adding data and correction data respectively outputted from the memory 10 and the correction data memory 14 which receive same address signals in response to a same output command signal Sout .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter.

[0002]

2. Description of the Related Art An example of a digital filter is disclosed in, for example, Japanese Patent Laid-Open No. 3-159413. This digital filter includes a shift register and a memory (RO
M) and a counter. The shift register used here shifts the input digital signal bit by bit by the first clock signal, holds n bits, and outputs it.

A ROM is used as the memory and stores data used as a filter output. Further, the ROM is configured such that the n-bit data held by the shift register is input as an address signal and the stored data corresponding to the address signal is output in response to the output instruction signal from the counter. .

The counter outputs a signal (output instruction signal) for instructing the memory to output data. Specifically, a signal generated by counting a second clock signal having a frequency n times (n is an integer of 2 or more) the first clock signal is output as an output instruction signal corresponding to this memory. Met.

[0005]

However, when waveform processing is performed using the above-mentioned digital filter, the waveform of the output data of the digital filter is attempted to be taken out as a continuous waveform close to the target analog output waveform. At that time, it was difficult to approach the target output waveform. The reason for this will be described below with reference to FIG.
This will be described with reference to (B) and (D).

FIG. 5A shows the first clock signal (CL
5B is a diagram in which the output waveform (digital amplitude waveform) of the target digital filter is plotted and drawn, while FIG. 5D shows the conventional digital filter. It is an output waveform diagram obtained by.
The plotted values of these waveforms correspond to the clock. As can be understood from FIGS. 5B and 5D, in the conventional output waveform, a difference occurs between the respective output waveforms as compared with the target output waveform diagram. For example, at clock times t ₃ and t ₉ , the target values are −
Although it is 1.5, the actual output value is -2.0. This is because the conventional memory outputs data as a positive integer value, so if you want to output the number of digits below the target decimal point, the number below the decimal point is carried up or down. Due to that. For this reason, in order to obtain a target output waveform with the circuit configuration of the conventional digital filter, it is necessary to store the digits below the decimal point as data in the memory in advance. As described above, in order to store the data having a decimal point or less in the memory, a memory having a large number of bits is required. However, a memory (ROM) having a large number of bits is expensive, and a method of processing output data becomes complicated, which is not a good idea.

Therefore, there has been a demand for a digital filter which can obtain an output waveform close to a target value (design value) without using a memory having a large number of bits.

[0008]

Therefore, the digital filter of the present invention is used as a filter output and an n-bit scale shift register controlled by the first clock signal when an input digital signal is input. A digital memory comprising a memory for storing data, wherein n-bit data from a shift register is input as an address signal and the data designated by the address signal is output in response to an output instruction signal. In the filter, the correction data, which is provided in parallel with the memory and for each data stored in this memory, is the same as the correction data memory stored at the address corresponding to the address of the memory. The address signal is input to the main memory and the correction data memory, and the same output instruction signal (here, the first Data (data stored in the memory) in response to a second clock signal having a frequency n times as high as the frequency signal (n is an integer of 1 or more). ) And correction data (data stored in the correction memory) are added and output.

[0009]

According to the digital filter of the present invention, first, the respective input digital signals stored in the sequential digits of the shift register are simultaneously generated by the first clock signal.
It is output from the shift register as n-bit data,
This n-bit data becomes an address signal. This address signal is simultaneously input to the memory and the correction data memory provided in parallel with the memory.

Further, the memory stores data used as a filter output, while the correction data memory stores correction data for each data stored in the memory. Then, by inputting the same output instruction signal, that is, the read timing signal, in synchronization with the memory and the correction data memory, the data and the correction data are output in response to the output instruction signal. The output data from the memory and the correction data from the correction data memory are added by an adder and output. Therefore, as in the conventional method, the stored data is written as a positive integer value in the memory as before, while the correction data memory stores the address for each data stored at the specified address in the memory. The difference value with respect to the target value or its approximate value is stored in the corresponding address as correction data. By doing so, the data output from the memory and the correction data output from the correction data memory are added by the adder by the same address signal, so that they are the same for the target output waveform. Alternatively, approximate output data can be obtained.
Therefore, a highly accurate output waveform of the digital filter can be obtained by using a commercially available inexpensive memory without increasing the number of bits in one memory as in the conventional case.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first and second embodiments of the present invention will be described below with reference to the drawings. In FIGS. 1 and 2 used for the explanation, constituent components similar to the conventional constituent components are indicated by a dashed line.

1. First Embodiment FIG. 1 is a diagram showing the configuration of a digital filter according to the first embodiment. The digital filter of the first embodiment is n
It comprises a bit shift register 10, a memory 12 for storing data, a correction data memory 14 for storing correction data, and an output instruction signal generator 16.

The shift register 10 is an n-bit shift register 10 controlled by the first clock signal (CLK1). The shift register 10 stores the first bit of the input digital signal in the first stage and then stores the first bit. The input digital signal is shifted bit by bit by the clock signal, and subsequent input digital signals are sequentially stored.
The number of digits of the shift register 10, that is, the number of stages n is
It can be any number depending on the design of the digital filter.

A ROM is used as the memory 12, and the memory 12 is a ROM that stores a large number of data used as a filter output. Below, memory 1
2 is also called a ROM. From the shift register 10, n
The bit data d _{0 to} d _{n form} one set and are output as one address signal (d _{0 to} d _n ) and input to the ROM 12. From the ROM 12, the address signal (d ₀
To d _n) data specified by the output instruction signal generating part 16
_Is output in response to the output instruction signal (output timing signal) S _out from. The output instruction signal generator 16 is composed of a counter. In this embodiment, the first
The second frequency n times the frequency of the clock signal (CLK1)
A counter for counting the clock signal (CLK2) is prepared, and the output signal from the counter at that time is used as the output instruction signal S _out .

The above shift resist 10 and ROM 1
2, and the structure of the output instruction signal generator 16 is a part 24 of the conventional structure. It should be noted that in FIG.
4 is surrounded by a dashed line.

In the present invention, a correction data memory 14 and an adder 18 are provided in addition to the conventional component portion 24.

In the first embodiment of the present invention, the correction data memory 14 is provided in parallel with the ROM 12, and the correction data memory 14 stores the correction data for each data stored in the ROM 12. It is stored. Then, the same address signals d _{0 to} d _n are input to the ROM 12 and the correction data memory 14, and the same output instruction signal S
An adder 18 for adding and outputting the data and the correction data respectively output in response to _out is provided.

The correction data memory 14 is the memory 1
It has the same number of storage locations as 2, and each storage location has an address corresponding to each other. Then, the data stored at an address position in the correction data memory 14 is the difference between the value of the stored data at the corresponding address position in the memory 12 and the target value desired to be output from that address position as the output of the digital filter. Is given as data. This difference value data may be data that gives an accurate difference value, or may be data that gives a difference value within an error range that is allowed to some extent.

FIG. 3 is a diagram for explaining an example of data stored in the ROM 12 and the correction data memory 14 when the waveform shown in FIG. 5B is targeted.

Target values corresponding to the first six clock times t ₀ , t ₁ , t ₂ , t ₃ , t ₄ , t ₅ in FIG. 5B are (0.0), (1.0). , (0.0), (-1.
5), (0.0), and (4.0).

On the other hand, the values of the data corresponding to these times in the memory 12 are (0.0), (1.0), (0.0),
This is shown in the left column as (-2.0), (0.0), (4.0). In such a case, the difference value between the target value and the value of the stored data in the memory 12 is (0.
0), (0.0), (0.0), (+0.5), (0.
0) and (0.0), the data giving this difference value is stored in the corresponding address position of the correction data memory 14, respectively. The contents of the data stored in the correction data memory 14 are shown in the right column of FIG.

The operation of the digital filter of the present invention in such a stored state will be described as an example.

For example, assume that a 4-bit address signal is stored in the 4-digit shift register 10. R from the shift register 10 according to the first clock signal (CLK1)
An address signal (d ₀ d ₁ d ₂ d ₃ ) is output to the OM 12. Data (0.0) is stored in the address position designated by the address signal of the ROM 12, while data (0.0) is stored in the same address position in the correction data memory 14. . Therefore, both of the output data from both memories 12 and 14 are added to the adder 18
Is added and output as (0.0) data.

At the same time, at the clock time t ₄ , the address signal (d ₃ d ₄ d ₅ d ₆ ) stores the data (-2.0) at the address of the ROM 12, which corresponds to the correction data memory 14. (+0.5) for the address
The correction data of is stored. Therefore, the memory 1
The outputs from 2 and 14 are added by the adder 18 (-
It is output as data of 1.5). Thus, each address (d ₀ d ₁ d ₂ d ₃ ), ... (d ₅ d ₆ d ₇ d
₈ ), the output signal corresponding to each address (that is, the output signal from the adder) is (0.
0), (1.0), (0.0), (-1.5), (0.
0) and (4.0), and the output signal gives the output waveform shown in FIG. With the configuration of FIG. 1, the output waveform of the adder 18 is a digital output, and this output waveform may be converted into an analog signal by a D / A converter (not shown).

FIG. 4 shows the relationship between data (values obtained by converting ROM data and correction data in the correction data memory) corresponding to the first clock signal (CLK1) and the second clock signal (CLK2). It is a figure for explaining.

The clock time of the first clock signal CLK1 is t ₀ , t ₂ ... t _n (state of the first clock signal of (a)), and the clock time of the second clock signal (CLK2) is also the first clock. Assume the same case as the signal. That is, the second clock signal may be generated at a frequency n times (n is an integer) the frequency of the first clock signal, but in this case, n = 1 (state of the second clock signal in (b)). ).

When the second clock signal (CLK2) is input to the count 16, the counter 16 is m times the second clock signal (CLK2) (m is an integer, but here m =
The counter output signal is output at the speed of 3). This counter output is a timing signal for reading out both memories 12 and 14, that is, an output instruction signal, and is simultaneously supplied to both memories. Therefore, the output instruction signal S _out is output at each timing time s ₀ , s ₁ ... s _{n of the} counter output.
Generate

FIG. 4 (d) is a diagram showing a target value, that is, a target value desired to be output from the digital filter in response to the output instruction signal S _out of the counter 16 and taken out. For example, when the target output data is the time t ₀ of the first clock signal CLK1, the data of (0.0) stored in the ROM is output, and the first clock signals t ₂ and t ₃ are output in the same manner. (1.0), (0.0),
The data of (-1.5), (0.0) and (4.0) are R
It is assumed that the outputs are sequentially output from the OM.

FIG. 4E shows a conventional value counter 16
6 is a diagram when the data stored in the memory is taken _out in accordance with the output instruction signal S _out of FIG.

Conventionally, the counter output times s ₀ , s ₁ ,
Three pieces of data are sequentially output from the ROM 12 by s ₂ . The value at this time is stored in the ROM (0.
It becomes the value of the data of 0). In addition, the first clock (CLK
When the time t _{2 of} 1) is reached, the counter 16 displays the time s ₃ , s
_The output instruction signal S _out is sequentially generated at ₄ and s ₅ , so that the ROM 12 outputs the stored data corresponding to the address signal (d ₁ d ₂ d ₃ d ₄ ) stored therein. That is, the data is (1.0). However, FIG.
As can be understood from (e) of (1), (−2.0) is output at the time t _{4 of} the first clock signal (CLK1), and only the value of (−0.5) is output as compared with the target value. The output is small (the target value is -1.5). This is because the values below the decimal point are processed for carry or carry, which causes a difference from the target value.

FIG. 4 (f) is a diagram showing the value of the first embodiment of the present invention when the data stored in the memory is taken _out in accordance with the output instruction signal S _out of the counter 16.

In the first embodiment, the first clock signal (CL
At time t ₄ of K1), (- it indicates a 1.5),
It will be the same value as the target value. The reason will be described below. As described with reference to FIG. 3, the address signal (d ₃ d ₄ d ₅ d
₆ ) is input to the ROM 12 and the correction data memory 14, the (-2.0) data is output from the ROM 12 while the correction data memory 14 outputs (+0.
The correction data of 5) is output. Then, the respective values are added by the adder 18, and (-1.5) is output.

In the above-mentioned example, the second clock signal (CLK2) of FIG. 4B is replaced with the first clock signal (CLK).
Although the description has been made assuming that the frequency of 1) is n = 1 times, for example, n =
When it is set to 2, the count value of the count output signal is further increased by 3 counts to generate 6 output instruction signals.
Therefore, six pieces of data stored in each memory are also taken out.

FIGS. 5B to 5D show the output waveforms of the digital filter using FIGS. 4A to 4F described above.

In the figure, (A) is the first clock signal (CLK
1), and the time to generate the clock is represented by t ₀ to t ₁₂ . It should be noted that although the display is made only until time t ₁₂ here, a continuous output waveform is obtained after time t ₁₂ . In (B), a target output waveform is represented by a digital waveform, and an analog waveform is represented by a broken line.
(C) is a digital output waveform obtained in the first embodiment. In addition to digital waveforms, solid lines also represent analog waveforms (described later). (D) represents a conventional digital output waveform. In the output waveforms of (B) to (D), the horizontal axis represents time T and the vertical axis represents amplitude (arbitrary).

As can be understood from FIGS. 5C and 5D, in the conventional example, both the times t ₂ and t _{9 of} the first clock signal (CLK1) are smaller than the target value. On the other hand, in the first embodiment, the waveform matches the target value ((B) in FIG. 5).

2. Second Embodiment FIG. 2 is a block diagram for explaining the configuration of the second embodiment.

In the second embodiment, the correction data (digital value) output from the correction data memory 14 and the first D / A converter 20 for converting the data (digital value) output from the ROM 12 into an analog signal. 2) is converted into an analog signal by adding a second D / A converter 22. The first and second D / A converters 20 and 22 are not particularly limited and may be conventionally known ones. Further, the adder 18 may be configured by a conventionally known one. Since the other components are the same as those in the first embodiment, detailed description will be omitted here. The output waveform of the filter configured in the second embodiment is the analog output waveform of FIG. 5 (C).

As can be understood from the above, the first
Also, in the second embodiment, by providing the correction data memory 14 and the adder 18, a digital signal having an output waveform which is the same as or close to the output waveform of the target value can be obtained without increasing the number of bits of the conventional ROM. You can get a filter. Therefore, the price of the ROM can be reduced as compared with the conventional one, and a digital filter can be provided without requiring complicated processing.

[0040]

As is apparent from the above description, the digital filter of the present invention includes the correction data memory and the adder. Therefore, the correction data for each data stored in the memory is stored in the correction data memory at an address corresponding to the address of the memory. Therefore, since the data output from the memory and the correction data output from the correction data memory are added, it is possible to obtain an output waveform that is equal to or approximate to the target output waveform. For this reason, it is possible to obtain a digital filter having an output waveform that is the same as or close to the target value using an inexpensive memory. Further, the data from the memory is converted into an analog signal by the first D / A converter, the correction data from the correction data memory is converted into an analog signal by the second D / A converter, and the respective analog signals are added. By doing so, it is possible to output as an analog output waveform.

[Brief description of drawings]

FIG. 1 is an explanatory diagram provided for explaining a configuration of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram provided for explaining a configuration of a second embodiment of the present invention.

FIG. 3 is a diagram provided for explaining the contents of address signals, memory storage data, and correction data storage correction data in the first and second embodiments.

4 (a) to (f) are explanatory diagrams provided for explaining output data according to each clock signal of the present invention and a conventional example.

5A to 5D are explanatory diagrams provided for explaining an output waveform corresponding to a first clock signal of the present invention and a conventional example.

[Explanation of symbols]

 10: shift register 12: memory 14: correction data memory 16: output instruction signal generator (counter) 18: adder 20: first D / A converter 22: second D / A converter 24: conventional component

Claims (2)

[Claims] 1. An input digital signal is input, and a first digital signal is input.
A memory which stores an n-bit shift register controlled by a clock signal and data used as a filter output, wherein n-bit data from the shift register is input as an address signal, In a digital filter comprising a memory that outputs designated data in response to an output instruction signal, correction data for each data stored in the memory that is provided in parallel with the memory is A correction data memory stored at an address corresponding to the address of the memory, and the same address signal is input to the memory and the correction data memory and output in response to the same output instruction signal. And an adder for adding and outputting the data and the correction data. I digital filter. 2. The digital filter according to claim 1, further comprising a first D / A converter for converting the data output from the memory into an analog signal, and the correction data output from the correction data memory. A digital filter comprising a second D / A converter for converting into an analog signal.