JP2000078030A - Interleaving address generator and interleaving address generation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a read/write address to a memory so that a continuous interleaving processing on data of a plurality of blocks is realized with one memory. SOLUTION: An address generator 1 generating a read/write address to a memory for executing an interleaving on N rows × M columns where N×M data are made into one block is provided with an address counter 3 executing count-up from zero at step width which is synchronized with a clock and is inputted, outputting the count value as the address, setting a value obtained by modulo-operating the value by (N×M-1) to be the next count value when the count value at the next clock becomes not less than (N×M), and returning the next count value to '0' when the count value becomes (N×M-1) and a step width computing element 5 changing step width to the counter 3 to a value obtained by (NμM-1) modulo-operating a value obtained by multiplying step width till then by M whenever the count value returns to '0'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital communication technology, and more particularly, to an interleaving process for reducing the influence of a burst error in a digital communication system.

[0002]

2. Description of the Related Art In general, a burst error occurring on a radio transmission path of a digital communication system is such that error data is intensively generated. Even if the correction processing is directly applied, a great effect cannot be obtained.

[0003] Therefore, conventionally, by using an interleaving process together with an error correction process on data transmitted through a wireless transmission path, concentrated error data due to a burst error is dispersed and converted into a random error. The error correction effect is improved.

[0004] In this interleaving process, the transmitting side changes the order of data and transmits the data. Then, the data is returned to the original order by performing the reverse operation of the transmitting side on the receiving side. By doing so, the burst errors in the transmission path are dispersed and converted into random errors, so that the error correction effect can be enhanced.

Here, in such an interleaving process, in order to change the order of N × M data (where N and M are integers of 2 or more) as one block, a RAM is used.
(Random access memory). In this method, assuming that the RAM has N row addresses and M column addresses, the input data is written to the RAM in the order of the row addresses, and after the writing is completed, the input data is written in the order of the column addresses. By reading data from the RAM, XY conversion between a virtual row address and a column address is performed, and input data is output in a different order from the input order.

For example, as shown in FIG. 7, a conventional interleave circuit 101 for performing such interleave processing is used.
Stores the input data from the data input terminal DIN, and transfers the stored data to the data output terminal DOUT.
And a clock input terminal CLK
N + 1-bit address counter 1 that counts up from the initial value 0 by 1 in synchronization with the clock from
05 and n output from the address counter 105
Of the + 1-bit data Q0 to Qn, n-bit data Q0 to Qn-1 other than the most significant bit Qn are input to the n-bit first input terminals a0 to an-1 and from the address counter 105. N-bit data Q0 to Q
The lower m bits Q0 to Qm-1 and the upper (n-
m) Address selector 107 in which n-bit data Qm to Qn-1 and Q0 to Qm-1 in which bits Qm to Qn-1 are exchanged are input to n-bit second input terminals b0 to bn-1.
And an interleaved address generator.

In the address selector 107, the most significant bit Qn of the address counter 105 is, for example, "0".
In this case, the data Q0 to Qn-1 from the address counter 105 input to the first input terminals a0 to an-1 are transferred from the own output terminals Y0 to Yn-1 to the address input terminals A0 to An- of the RAM 103. 1 as a write address, and conversely, the most significant bit Qn of the address counter 105.
Is "1", the data Qm to Qn-1 from the address counter 105 input to the second input terminals b0 to bn-1.
, Q0 to Qm-1 are output as read addresses from their own output terminals Y0 to Yn-1 to address input terminals A0 to An-1 of the RAM 103.

Further, when the most significant bit Qn of the address counter 105 is "0", the RAM 103
Data sequentially input from the data input terminal DIN in synchronization with the clock is stored at an address indicated by the data input to the address input terminals A0 to An-1.
When the most significant bit Qn of the address counter 105 is "1", the data of the address indicated by the data input to the address input terminals A0 to An-1 is sequentially output from the data output terminal DOUT in synchronization with the clock. I do.

In such an interleave circuit 101, when input data is written to the RAM 103, the address counter 107 is used by the address selector 107.
The n-bit data Q0 to Qn-1 from 5 are stored in the RA
Since the data is output as a write address to the address input terminals A0 to An-1 of M103, data is written in order from address 0 of the RAM 103.

When reading data from the RAM 103, the address selector 107 causes the lower m bits Q0 to Qm-1 and the upper (nm) bits Qm of the n-bit data Q0 to Qn-1 from the address counter 105 to be read. To Qn-1 and n-bit data Qm to Qn-
1, Q0 to Qm-1 are output to the address input terminals A0 to An-1 of the RAM 103 as read addresses, so that data is read in the order in which the row address and the column address of the RAM 103 are exchanged with respect to the time of data writing. It will be.

For example, when interleaving processing is performed in 4 rows × 4 columns (ie, when interleaving processing is performed with 4 × 4 data as one block), the input data from the data input terminal DIN is as shown in FIG. The data is written to the RAM 103 in the order of the address shown in FIG.
When all 16 (= 4 × 4) data for one block have been written, data is read from the RAM 103 in the order of addresses shown in FIG. 8B, and the read data is read out. Are sequentially output from the data output terminal DOUT. Note that the numbers in the circles in FIG. 8A indicate the order of addresses to write data.
The numbers in parentheses in FIG. 8B indicate the order of addresses from which data is read.

Thus, for one block of input data, D1, D2, D3,..., D14,.
Assuming that indexes D15 and D16 are provided, input data is input from the data output terminal DOUT to D1 and D5.
, D9, D13, D2, D6, D10, D14, D3, D7
, D11, D15, D4, D8, D12, D16 in that order.

[0013]

By the way, in the above-mentioned conventional interleave circuit 101, it is necessary to hold one block of data until the data reading from the RAM 103 is completed. Therefore, in order to continuously interleave data of a plurality of blocks that are sequentially input, as shown in FIG. 9, the interleave circuit 1 shown in FIG.
01, two circuit blocks 101A,
101B, a delay circuit 109 for delaying the start of the clock supply to one circuit block 101B by one block, and a circuit when the most significant bit Qn of the address counter 105 in the other circuit block 101A is "1". Data output from the data output terminal DOUT of the block 101A is output as output data, and conversely,
When the most significant bit Qn is "0", an interleave circuit is constituted by the selector 111 that outputs data output from the data output terminal DOUT of the circuit block 101B as output data.
A and 101B each have a phase of writing data to the RAM 103 at the timing shown in FIG.
It is necessary to alternately handle the phase of reading data from M103.

FIG. 10 shows a case where an interleave process is performed with 4 × 4 data as one block, as in FIG. In FIG. 10, the output data of numbers 1 to 16 and the output data of number 33 or more output when Qn is “1” are interleaved by the circuit block 101A, The number output when Qn is "0" is 17
Output data up to 32 are data subjected to interleave processing by the circuit block 101B.

As described above, in the prior art, in order to continuously perform interleaving processing on a plurality of blocks of data that are sequentially input, an interleaved address generator including the address counter 105 and the address selector 107 includes: It is necessary to provide two RAMs 103 each, and it is difficult to reduce the size of the circuit for performing the interleave processing. And especially, since this kind of interleaving processing is performed in a mobile communication device or the like,
The circuit that performs the interleaving process is required to be small.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an interleave address generator and an interleave address generation method capable of performing a continuous interleave process on a plurality of blocks of data with one memory.

[0017]

The interleave address generating method according to the present invention, which has been made to achieve the above object, has N × M addresses (where, N and M). (M is an integer of 2 or more) as one block, and sequentially writes the data into a memory, and reads out the data written in the memory in an address order different from that at the time of writing, so that the input data is It is used to perform an interleaving process of outputting in an order different from the order, and generates addresses for reading and writing to the memory.

The interleave address generating method of the present invention counts up from an initial value of 0 at a set step width, and sequentially outputs the count value as an address for reading and writing to the memory. If the next count value is equal to or more than the above (N × M), the value obtained by taking the modulo of (N × M−1) for that value is set as the next count value, and the current count value is (N × M−1). N × M−1), an address counting process for returning the next count value to the initial value 0,
A step width setting process for setting the step width used in the address counting process. In the step width setting process, a value obtained by multiplying the currently set step width by the M is (N × M−1) modulo. Is obtained as a new step width at the time of the interleave processing for the next block, and the step width used in the address count processing is synchronized with the timing when the count value by the address count processing returns to the initial value 0. It is characterized in that it is updated to the obtained new step width.

Further, such an interleave address generating method of the present invention can be implemented by the interleave address generator according to the first aspect. That is,
The interleave address generation circuit according to claim 1,
N × M data (where N and M are integers of 2 or more) are sequentially input as data and written into a memory,
By reading data written in the memory in an address order different from that at the time of writing, it is used for performing interleave processing of outputting input data in an order different from the order at the time of input, and reading out the memory. And an address for writing, and includes an address counting means and a step width calculating means.

The address counting means performs a count-up operation from an initial value of 0 with a step width input from the outside in synchronization with a clock, and outputs the count value as an address for reading and writing to the memory. In addition, when the count value at the next clock timing is equal to or more than the above (N × M), the value obtained by taking the modulo (N × M−1) for the value is used as the count value at the next clock timing. Further, when the current count value becomes (N × M−1), the count value at the next clock timing is returned to the initial value 0.

Further, the step width calculating means calculates the step width used for the count-up operation by the address counting means and outputs the calculated step width to the address counting means.
Is set as a new step width at the time of interleaving processing for the next block, and the count value of the address counting means returns to the initial value 0. In synchronization with the timing, the step width output to the address counting means is changed to the set new step width.

Incidentally, the step width means an increment value for each time when a count value serving as an address to the memory is counted up. The value obtained by taking the modulo of (N × M−1) for a certain value Z means the remainder value when the certain value Z is divided by (N × M−1).

In the interleave address generation method and the interleave address generator according to the present invention, the step width of the address output by the address count processing or the address count means is such that the output address is (N × M-1). , And is changed every time one block of input data is returned.

Therefore, according to the interleave address generation method and the interleave address generator of the present invention,
During the period of inputting the data of the first (ie, first) block, the input data is sequentially written to each address of the memory output by the address counting process or the address counting means, and the data of each of the second and subsequent blocks is written. During the input period, data is read from each address of the memory output by the address counting process or the address counting means, and the read address is overwritten with the current input data, so that the data reading from the memory is performed. Addressing is performed with a step width different from that when the data is written. Therefore, continuous interleave processing on data of a plurality of blocks can be performed only by providing one set of a memory and an interleave address generator.

For example, the initial value of the step width is set to 1, the number of rows (the number of rows) N = 4 and the number of columns (the number of columns) M =
When the interleave processing is performed with a block size of 3 (ie, 4 rows × 3 where 4 × 3 data is one block)
The case of performing interleave processing in columns) will be specifically described.

In this case, as shown in the fifth and bottom rows from the top in FIG. 4, the data of the first block (D1-1
To D1-12), 0, 1, 2, 2 from the address counting process or the address counting means.
The addresses are output in the order of 3, 4, 5, 6, 7, 8, 9, 10, and 11.

Then, the data (D2-
1 to D2-12), the step width set or output by the step width setting process or the step width calculating means is set to M (= 1) in the step width (= 1) in the input period of the first block. 3) (=
3) is a value (= 3) obtained by taking a modulo of 11 (= N × M−1). Therefore, from the address count processing or the address count means, 0, 3, 6, 9, 1, 1,
The addresses are output in the order of 4, 7, 10, 2, 5, 8, and 11. Note that the output address changes to 1 after 9 because the value obtained by adding 3 which is the current step width to 9 (= 12) is 12 (= the number of data in one block). N × M) or more, so in this case,
This is because 1 which is a value obtained by taking a modulo of 11 (= N × M−1) for 12 becomes the next count value. Similarly, the output address changes to 2 after 10 because the value obtained by adding 3 which is the current step width to 10 (= 13) is 12 (= N × M) or more. Therefore, in this case, the value 2 obtained by taking the modulo of 11 (= N × M−1) for 13 becomes the next count value.

Further, during the period of inputting the data (D3-1 to D3-12) of the third block, the step width set or output by the step width setting processing or step width calculating means is equal to the second step width. The value (= 9) obtained by taking the modulo of 11 (= N × M−1) for the value (= 9) obtained by multiplying the step width (= 3) by M (= 3) in the input period of the block. Therefore, from the address counting process or the address counting means, 0, 9, 7,.
The addresses are output in the order of 5, 3, 1, 10, 8, 6, 4, 2, and 11. Note that the output address changes from 9 to 7 because the value obtained by adding 9 which is the current step width to 9 (= 18) is 12 (= the number of data in one block). This is because, in this case, 7 which is a value obtained by taking the modulo of 11 (= N × M−1) for 18 becomes the next count value. The same applies to the case where the output address changes from 7 to 5 or from 5 to 3 or the like.

Although not shown in FIG. 4, during the period of inputting the data of the fourth block, the step width set or output by the step width setting processing or the step width calculating means is equal to the third step width. A value (= 5) obtained by taking a modulo of 11 (= N × M−1) for a value (= 27) obtained by multiplying the step width (= 9) by M (= 3) in the input period of the block. Therefore, from the address count processing or the address count means, 0, 5, 1
Addresses are output in the order of 0, 4, 9, 3, 8, 2, 7, 1, 6, and 11. Note that the output address is changed to 4 after 10 because the value obtained by adding 5 which is the current step width to 10 (= 15) is 12 (= the number of data in one block). N × M) or more,
In this case, the value 4 obtained by taking the modulo of 11 (= N × M−1) for 15 becomes the next count value. The same applies to a case where the output address changes to 3 after 9 or a case where the output address changes to 2 after 8.

Therefore, if the data of the first block is sequentially written into each address of the memory output by the address counting process or the address counting means, the data of the first block will be 0 to 11 in the memory.
Addresses are written in the order of the numbers shown in the circles in FIG.

During the period of inputting the data of the second block, data is read from each address of the memory output by the address counting process or the address counting means, and the read address is overwritten with the current input data. For example, each data of the first block already written in the memory is 0 to 1
1 (B), the data of the second block are read from the addresses 0 to 11 of the memory to the addresses 0 to 11 in FIG. 1 (C).
Are written in the order of the numbers shown in the circles (ie, the same order as the numbers shown in the circles in FIG. 1B).

Further, during the period of inputting the data of the third block, data is read from each address of the memory output by the address counting process or the address counting means, and the read address is overwritten with the current input data. Then, each data of the second block already written in the memory is read from the addresses from 0 to 11 in the order of the numbers shown in {} in FIG. Each data of the block is written to addresses 0 to 11 of the memory in the order of the numbers shown in {} in FIG. 1 (D), similarly to the relationship between FIG. 1 (B) and FIG. 1 (C). Become.

For this reason, D1, D2, D3,.
D4, D5, D6, D7, D8, D9, D10, D11, D
Assuming that an index of 12 is added, as can be seen from the relationship between FIG. 1A and FIG. 1B and the relationship between FIG. 1C and FIG. Are read from the memory, so that
1, D4, D7, D10, D2, D5, D8, D11, D3
, D6, D9, D12.

That is, by changing the step width of the address to the memory for each block of data by the step width setting processing or the step width calculating means, continuous interleave processing can be performed with only one memory. It becomes. Note that the initial value of the step width is not limited to 1, but may be any integer greater than or equal to 1. Also,
The start address of the memory used for the interleave processing is 0
If the address is not an address, the head address value is added to the address output by the address counting process or the address counting means, and the address after the addition may be supplied to an address input terminal of the memory.

In the interleaved address generator according to the first aspect, the step width calculating means may be arranged so that the count value of the address counting means is from the initial value 0 to (N × M-1). During the period of one block up to, the currently output step width is cumulatively added M times, and the value obtained by taking the modulo of (N × M−1) for the cumulative added value is given by Step width setting means for setting as a new step width at the time of interleave processing for the block of No., detecting means for detecting that the count value of the address counting means has become (N × M-1), and When it is detected that the count value of the counting means has reached (N × M−1), the new step width set by the step width setting means is replaced with the next step width. Stores the lock timing may be composed of a step width output means for outputting a step width that the storage to the address counting means.

In other words, in the interleave address generator according to the present invention, a value obtained by multiplying the currently output step width by the M is obtained by cumulatively adding the current step width for the M times. . Claim 1
In the interleave address generator described in (3), the step width calculating means multiplies the currently output step width by the M and calculates the multiplied value by (N × M− Step width setting means for setting the value obtained by taking the modulo of 1) as a new step width at the time of interleave processing for the next block, and the fact that the count value of the address counting means has become (N × M-1). Detecting means for detecting, and when the detecting means detects that the count value of the address counting means has reached (N × M−1), the new step width set by the step width setting means is And a step width output means for storing the stored step width at the next clock timing and outputting the stored step width to the address counting means.

That is, in the interleave address generator according to the third aspect, a value obtained by multiplying the currently output step width by the M is obtained by multiplying the current step width by the M. However, the configuration in which the currently output step width is cumulatively added M times as described in claim 2 is advantageous in that the circuit configuration can be simplified because there is no need to directly perform multiplication. It is.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. First, FIG. 2 is a block diagram showing a configuration of the interleave address generator 1 of the first embodiment, and FIG. 3 is a detailed circuit diagram of the interleave address generator 1.

The interleave address generator 1 according to the first embodiment performs an interleave process in N rows × M columns using N × M data (where N and M are integers of 2 or more) as one block. In order to perform the above, addresses for reading and writing to a memory (specifically, a RAM) not shown are generated. In the following description, M is referred to as “column number” meaning the number of columns, and (N × M), which is the number of data in one block, is referred to as “block size”.

As shown in FIG. 2, the interleave address generator 1 of the first embodiment has a clock input terminal T1.
An address counter 3 that performs a count-up operation from an initial value 0 at a step width input from the outside in synchronization with a clock from an external device, and outputs the count value as an address for reading and writing to a memory; , The block size input from the block size input terminal T2−1 (= N ×
M-1) and the data representing the number of columns (= M) inputted from the column number input terminal T3, the step width of the address counter 3 is synchronized with the clock from the clock input terminal T1. And a step width calculator 5 for calculating and outputting.

Incidentally, a high active reset signal is inputted to the address counter 3 and the step width calculator 5 via a reset signal input terminal T4. The address counter 3 also has a block size -1 (= N × M-1) from the block size input terminal T2.
Is input. Further, an address is output from the address counter 3 to the memory via the address output terminal T5.

Next, as shown in FIG. 3, the address counter 3 stores the count value of the address counter 3 in synchronization with the clock from the clock input terminal T1, and stores the stored count value in the address to the memory. And a flip-flop group 11 (hereinafter, referred to as F / F group 11) including a number of flip-flops with a clock synchronous reset function corresponding to the input bus width and output to the address output terminal T5, and an output value of the F / F group 11 (Ie, the current count value of the address counter 3, which is the address of the memory currently being output) and the step width input from the step width calculator 5, and the adder 13 13, the data representing the block size -1 input from the block size input terminal T2 (hereinafter simply referred to as the block size Subtractor 15 for subtracting) of 1
And the operation result of the adder 13 and the block size input terminal T
2 is compared with the block size −1, and the result of the operation of the adder 13 is the block size −1 (= N × M−1).
If it is less than or equal to the above, a high-level select signal is output. Otherwise (that is, if the operation result of the adder 13 is equal to or larger than the block size (= N × M)), a low-level select signal is output. A comparator 17 that performs
When the select signal from the comparator 17 is at a high level, the operation result of the adder 13 is input to the data terminal (D) of the F / F group 11, and when the select signal from the comparator 17 is at a low level, the subtractor 15 Calculation result of F
Selector 1 for input to data terminal (D) of / F group 11
9.

The F / F group 11 operates in synchronization with the rise of the clock, and the selector 19 operates normally when the reset signal input from the reset signal input terminal T4 to its own reset terminal (RESET) is at a low level. The data value input to the own data terminal (D) from the input terminal via the input bus is stored (latched) at the rising edge of the clock, and is output from the output terminal (Q) to the address output terminal T.
Output to 5 When the output value of the F / F group 11 becomes the block size −1 (= N × M−1), the output value of the F / F group 11 is initialized at the next rising edge of the clock regardless of the output of the selector 19. It is configured to return to the value 0.

The address counter 3 configured as described above
When a high-level reset signal is input from the reset signal input terminal T4, the F / F group 11 is reset in synchronization with the clock from the clock input terminal T1, and as a result, stored in the F / F group 11. In the count value to be output to the memory from the address output terminal T5, all bits have an initial value of 0 (see FIG. 4).

When the reset signal from the reset signal input terminal T4 goes low and the reset is released, the F / F is output from the next clock after the reset is released.
The count-up operation of the address to the memory is performed centering on the F group 11. The count-up operation of the address counter 3 is as follows.
The current output value of the F group 11 and the step width input from the step width calculator 5 are added, and the calculation result of the adder 13 and the value of the block size −1 (= N × M−1) are
The magnitude is compared by the comparator 17.

When the operation result of the adder 13 is equal to or smaller than the block size -1 (= N × M-1), the selector 19 operating according to the select signal from the comparator 17 outputs The calculation result is F /
The data is input to the data terminal (D) of the F group 11, and as a result,
The / F group 11 stores the operation result of the adder 13 as the count value of the address counter 3 at the next rising edge of the clock, and outputs the stored count value from its own output terminal (Q) to address output. Terminal T5
To be output as an address to the memory.

On the contrary, when the operation result of the adder 13 is equal to or larger than the block size (= N × M), the selector 19 calculates the operation result of the subtractor 15 and the operation result of the adder 13. From the block size -1 (= N × M-
The value obtained by subtracting 1) is input to the data terminal (D) of the F / F group 11, and as a result, the F / F group 11 outputs the operation result of the subtractor 15 at the next rising edge of the clock. In addition to storing the count value of the address counter 3, the stored count value is output from its own output terminal (Q) to the address output terminal T5 as an address to the memory.

Therefore, in the address counter 3, the F / F
By the operation of the group 11 and the adder 13, a count-up operation is performed from the initial value 0 with the step width input from the step width calculator 5 in synchronization with the clock, and the count value is output as an address to the memory. In particular, when the count value at the next clock timing is equal to or greater than the block size (= N × M), the operation of the subtractor 15, the comparator 17, and the selector 19 causes the block size to exceed the block size. Is a value obtained by taking the modulo of the block size -1 (= N × M-1) as the count value at the next clock timing. Further, when the count value at the current clock timing becomes the block size -1 (= N × M-1), the above-described F /
By the operation of the F group 11, the count value at the next clock timing returns to the initial value 0.

On the other hand, as shown in FIG. 3, the step width calculator 5 stores the step width used by the address counter 3 in the above-described count-up operation in synchronization with the clock from the clock input terminal T1, and stores the stored step width. A step width is output to the address counter 3 (specifically, an adder 13 of the address counter 3). The first bit is a flip-flop with a clock synchronous reset function, and the other bit is a flip-flop with a clock synchronous reset function. Group 21 (hereinafter referred to as F / F group 21)
And the number of clocks corresponding to the input bus width, in which the operation value generated in the process of calculating the step width to be output from the F / F group 21 to the address counter 3 is stored in synchronization with the clock from the clock input terminal T1. And a flip-flop group 23 including a flip-flop with a synchronous reset function (hereinafter, referred to as F / F group 23).

The F / F groups 21 and 23 operate in synchronization with the rise of the clock, and have their own reset terminals (RE
Normally, when the signal input to the terminal (SET) or the preset terminal (SET) is at the low level, the data value input to the own data terminal (D) via the input bus is stored (latched) at the rising edge of the clock. Output from the output terminal (Q). Also, the step width calculator 5
Is the output value of the F / F group 21 (that is, the step width currently output from the F / F group 21 to the address counter 3) and F
/ F group 23 and an output value of the block size input terminal T2 based on the operation result of the adder 25.
The subtracter 27 for subtracting the input block size -1 (= N × M-1) and the arithmetic result of the adder 25 and the block size -1 from the block size input terminal T2 are compared in size and added. The operation result of the unit 25 is a block size−
1 (= N × M−1) or less, outputs a high-level select signal; otherwise (ie, if the operation result of the adder 25 is equal to or greater than the block size (= N × M)) ), A comparator 29 for outputting a low-level select signal, and selecting and outputting the operation result of the adder 25 when the select signal from the comparator 29 is at a high level, and when the select signal from the comparator 29 is at a low level A selector 31 for selecting and outputting the operation result of the subtracter 27; a count value of the address counter 3 (that is, an address output from the F / F group 11 of the address counter 3 to the memory); and a column number input terminal. The data representing the number of columns input from T3 (hereinafter simply referred to as the number of columns) is compared in magnitude, and the count value of the address counter 3 is compared with the number of columns. (= M), a high-level select signal is output; otherwise, the count value of the address counter 3 is equal to the number of columns (= M).
M) or more), the comparator 33 that outputs a low-level select signal, and when the select signal from the comparator 33 is at a high level, outputs the selector 31 to the data terminal (D) of the F / F group 23. And a selector 35 for inputting the output of the F / F group 23 to the data terminal (D) of the F / F group 23 when the select signal from the comparator 33 is at a low level.

Further, the step width calculator 5 compares the count value of the address counter 3 with the block size -1 from the block size input terminal T2, and determines that the count value of the address counter 3 is the block size -1 (= N ×
M-1), a high-level select signal is output; otherwise, the address counter 3
Is not equal to the block size −1 (= N × M−1), the comparator 37 that outputs a low-level select signal, and the F / F when the select signal from the comparator 37 is at a high level. The output of the group 23 is input to the data terminal (D) of the F / F group 21. When the select signal from the comparator 37 is at a low level,
The output of the / F group 21 is connected to the data terminal (D) of the F / F group 21
And a reset signal input terminal T
And a logical sum circuit 41 for inputting a logical sum signal of the reset signal from the comparator 4 and the select signal from the comparator 37 to the reset terminal (RESET) of the F / F group 23.

Next, the operation of the step width calculator 5 configured as described above will be described. First, when a high-level reset signal is input from the reset signal input terminal T4, in the F / F group 23, the signal input to the reset terminal (RESET) of each flip-flop is transmitted via the OR circuit 41. High level and F / F group 2
At 1, the signals input to the preset terminal (SET) of the flip-flop of the first bit and the reset terminal (RESET) of the flip-flops of other bits become high level.

Therefore, when a high-level reset signal is input from the reset signal input terminal T4, all bits of the output value of the F / F group 23 become 0 in synchronization with the clock from the clock input terminal T1. . The output value of the F / F group 21 is 1 only in the first bit and 0 in other bits.
As a result, the step width output to the address counter 3 becomes 1 as an initial value (see FIG. 4).

After that, when the reset signal from the reset signal input terminal T4 becomes low level and the reset is released, the F / F group 23 outputs the output of the selector 35 which operates according to the select signal from the comparator 33. , And latch and output in synchronization with the clock.

Here, the selector 35 is connected to the comparator 3
3 is high (that is, the count value of the address counter 3 and the address output from the address output terminal T5 is the number of columns (=
M)), the output of the selector 31 is set to F
/ F group 23 to the data terminal (D).

Then, the selector 31 sets the comparator 2
9 according to the select signal from F / 9.
If the operation result obtained by adding the output value of the F group 21 and the output value of the F / F group 23 is equal to or smaller than the block size -1 (= N × M-1) from the block size input terminal T2,
The operation result of the adder 25 is output to the selector 35 as it is, and conversely, the operation result of the adder 25 is the number of blocks (= N
× M) or more, the block size −1 (= N × M−
The calculation result obtained by subtracting 1) is output to the selector 35.

The selector 35 includes a comparator 33
Is low level (ie, the current count value of the address counter 3 and the address output from the address output terminal T5 is equal to or more than the number of columns (= M)). The output of the / F group 23 is input to the data terminal (D) of the F / F group 23.

Therefore, when the count value of the address counter 3 is smaller than the number of columns (= M), the F / F group 23 adds the current output value of itself and the output value of the F / F group 23. Block size -1 (= N × M-
The value obtained by taking the modulo of 1) is latched at the next clock timing, and when the count value of the address counter 3 is equal to or greater than the number of columns (= M), the output value of the address counter 3 is held without being updated. Will be done.

As a result, the F / F group 23 includes the adder 25,
Subtractor 27, comparators 29 and 33, and selector 3
1 and 35, the count value of the address counter 3 is changed from the initial value 0 to the block size -1.
During the period of one block until (= N × M−1), the step width output from the F / F group 21 is cumulatively added M times the number of columns, and the block size is calculated for the cumulative added value. The value obtained by taking the modulo of -1 (= N × M-1) is stored as a new step width at the time of the interleave processing for the next block. By this operation, the value obtained by multiplying the value obtained by multiplying the step width currently output to the address counter 3 by the number of columns (= M) and taking the modulo of the block size -1 (= N × M-1) becomes Is set as a new step width at the time of the interleave processing for the block of.

When the count value of the address counter 3 reaches the block size -1 (= N.times.M-1), the comparator 37 determines that it is the input timing of the last data of the block and outputs a high-level select signal. Output. The high-level select signal from the comparator 37 is sent to the F / F group 23 via the OR circuit 41.
Is input to the reset terminal (RESET). Therefore,
The F / F group 23 is reset at the next clock timing (that is, the timing at which the count value of the address counter 3 returns to the initial value 0 and the timing at which the first data of the next block is input), and the output value of the F / F group 23 is reset. Will return to 0. That is, the high-level select signal output from the comparator 37 is a block end signal indicating the end of one block.

On the other hand, in the step width calculator 5,
When the reset signal from the reset signal input terminal T4 changes from high level to low level and the reset is released,
The F / F group 21 latches the output of the selector 39 that operates according to the select signal from the comparator 37 in synchronization with the clock, and outputs it as a step width.

Here, the selector 39 selects the comparator 3
7 is low (that is, the count value of the address counter 3 is equal to the block size -1 (=
If not (N × M−1)), the output of the F / F group 21 is input to the data terminal (D) of the F / F group 21, and if the select signal from the comparator 37 is at a high level (ie, , When the count value of the address counter 3 is the block size −1 (= N × M−1)), the F / F group 2
3 is input to the data terminal (D) of the F / F group 21.

Therefore, in the F / F group 21, the count value of the address counter 3 is equal to the block size −1 (= N × M−
At 1), at the next clock timing (ie, when the count value of the address counter 3 returns to the initial value of 0), a new step width for the next block stored in the F / F group 23 immediately before is set. The latched step width is transferred to the address counter 3 during the period of one block from when the count value of the address counter 3 returns to the initial value 0 from the next block size -1 (= N × M-1). Will be output.

That is, the F / F group 21 operates in cooperation with the selector 39, and the count value of the address counter 3 is reduced by the comparator 37 to the block size.
1 (= N × M-1), F /
The new step width latched in the F group 23 is stored at the next clock timing, and the stored new step width is output to the address counter 3. By this operation, the step width output to the address counter 3 is changed to a new step width in synchronization with the timing at which the count value of the address counter 3 returns to the initial value 0.

Next, FIG. 4 shows a case where the operation of the above-mentioned interleave address generator 1 is performed by performing an interleave process with a block size of the number of rows (number of rows) N = 4 and the number of columns (number of columns) M = 3. It is a time chart represented by giving an example. Note that the interleave address generator 1 of the present embodiment
Is used, data is sequentially input to the memory in synchronization with the clock to the clock input terminal T1.

As shown in FIG. 4, in this example, 1
A period during which the data (D1-1 to D1-12) of the second block is input (that is, a period corresponding to 12 cycles of a clock corresponding to one block of data from immediately before the reset signal changes from the high level to the low level). , From the address counter 3, 0, 1, 2, 3, 4, 5, 6, 7, 8,
Addresses are output in the order of 9, 10, and 11. This is because the initial value of the step width output from the F / F group 21 of the step width calculator 5 is 1.

In this period, the address counter is operated by the operation of the F / F group 23 of the step width calculator 5, the adder 25, the subtractor 27, the comparators 29 and 33, and the selectors 31 and 35. When the address from 3 is 0, 1, or 2 smaller than the number of columns M (= 3), the step width (= 1) currently output from the F / F group 21 is cumulatively added. The value (= 3) obtained by taking the modulo of the block size -1 (= 11) for the cumulative addition value is stored in the F / F group 23 as a new step width for the next block. In this case, the value stored in the F / F group 23 changes from 0 to 1 to 2 to 3 because the block size (= 12) does not exceed the block size even if the step width is cumulatively added three times. .

When the address output from the address counter 3 returns from 11 to 0, at that timing,
The new step width stored in the F / F group 23 (=
3) is latched by the F / F group 21 and the F / F group 2
3 returns to 0, and the new step width (= 3) latched in the F / F group 21 is the step width during the period of inputting the data (D2-1 to D2-12) of the second block. Is output to the address counter 3.

Therefore, the data of the second block (D
2-1 to D2-12), the address counter 3 outputs 0, 3, 6, 9, 1, 4, 7, 10,.
Addresses are output in the order of 2, 5, 8, and 11. During this period, the output address changes to 1 after 9 because the value obtained by adding 3 which is the current step width to 9 (= 12) is the block size (= 12).
12) or more, in this case, the result of the operation of the subtractor 15 and the block size of -12 (=
This is because the value 1 obtained by taking the modulo of 11) is latched by the F / F group 11 as the next count value. This also applies to a case where the output address changes to 2 after 10.

In this period, the address counter is operated by the operation of the circuit portion including the F / F group 23 of the step width calculator 5, the adder 25, the subtractor 27, the comparators 29 and 33, and the selectors 31 and 35. When the address from 3 is 0, 1, or 2 smaller than the column number M (= 3), the step width (= 3) currently output from the F / F group 21 is cumulatively added, and A value (= 9) obtained by taking the modulo of the block size -1 (= 11) for the cumulative addition value is stored in the F / F group 23 as a new step width for the next block. In this case, the value stored in the F / F group 23 changes from 0 to 3 to 6 to 9 because the block size (= 12) does not exceed the block size even if the step width is accumulated three times. .

When the address output from the address counter 3 returns from 11 to 0, at that timing,
The new step width stored in the F / F group 23 (=
9) is latched by the F / F group 21 and the F / F group 2
3 returns to 0, and the new step width (= 9) latched in the F / F group 21 is the step width during the period of inputting the data (D3-1 to D3-12) of the third block. Is output to the address counter 3.

Therefore, the data of the third block (D
3-1 to D3-12), from the address counter 3, 0, 9, 7, 5, 3, 1, 10, 8,
The addresses are output in the order of 6, 4, 2, and 11. In this period, the output address changes to 9 after 9 because the value (= 18) obtained by adding 9 which is the current step width to 9 is the block size (= 18).
12) or more, in this case, the result of the operation of the subtractor 15 and the block size −1 (=
This is because the value 7 obtained by taking the modulo of 11) is latched in the F / F group 11 as the next count value. The same applies to the case where the output address changes from 7 to 5 or from 5 to 3 or the like.

During this period, the address counter is operated by the circuit portion including the F / F group 23, the adder 25, the subtractor 27, the comparators 29 and 33, and the selectors 31 and 35 of the step width calculator 5. When the address from 3 is 0, 1, or 2 smaller than the number of columns M (= 3), the step width (= 9) currently output from the F / F group 21 is cumulatively added. A value (= 5) obtained by taking the modulo of the block size -1 (= 11) for the cumulative addition value is stored in the F / F group 23 as a new step width for the next block. In this case, F
The value stored in the / F group 23 changes from 0 → 9 → 7 → 5.

Then, although not shown in FIG. 4, the address output from the address counter 3 becomes 11
Returns to 0 at that time, the new step width (= 5) stored in the F / F group 23 is
And the output value of the F / F group 23 returns to 0, and the new step width (=
5) is output to the address counter 3 as the step width in the period of inputting the data of the fourth block. Therefore, during the period of inputting the data of the fourth block, the address counter 3 outputs
0, 5, 10, 4, 9, 3, 8, 2, 7, 1, 6, 11
In this order.

As described above, in the interleaved address generator 1 according to the first embodiment, the step width of the address output from the address counter 3 in synchronization with the clock is the block size minus 1 (block size). =
(N × M−1), and is returned to the initial value 0, and is changed by the step width calculator 5 for each block of the input data.

Therefore, according to the interleave address generator 1, during the period of inputting the data of the first block, the input data is sequentially written to each address of the memory output from the address counter 3, and the second and subsequent data are written. During the period of inputting data of each block, data is read from each address of the memory output from the address counter 3 and the read address is overwritten with the current input data, as described with reference to FIG. As described above, the reading of data from the memory is addressed with a step width different from that when the data is written. For example, in the case of the example shown in FIG. 4, D1, D2, D3, D4, D5, D6,.
Assuming that D7, D8, D9, D10, D11 and D12 are indexed, the input data of each block which is sequentially input is read out from the memory, so that
D1, D4, D7, D10, D2, D5, D8, D11, D
3, D6, D9, and D12.

Therefore, according to the interleave address generator 1 of the first embodiment, continuous interleave processing for data of a plurality of blocks can be performed only by providing one set of the interleave address generator 1 and a memory. In addition, a circuit for performing the interleave processing (interleave circuit) can be downsized.

In the first embodiment, the address counter 3 corresponds to an address counting means, and the operation of the address counter 3 corresponds to an address counting process. The step width calculator 5 corresponds to a step width calculator, and the operation of the step width calculator 5 corresponds to a step width setting process. Then, among the units constituting the step width calculator 5, the F / F group 2
3, adder 25, subtractor 27, comparator 29,3
3, the selectors 31, 35 and the OR circuit 41 correspond to the step width setting means according to claim 2, and the comparator 37 corresponds to the detection means according to claim 2, and the F / F
The group 21 and the selector 39 correspond to the step width output means.

In the interleave address generator 1 of the first embodiment, a value obtained by multiplying the step width currently output to the address counter 3 by the number of columns M is accumulated by the current step width for the number of columns M. Although obtained by adding, the current step width and the number of columns M may be directly multiplied.

Then, a value obtained by multiplying the current step width and the number of columns M by a multiplier is used to obtain a value obtained by multiplying the current step width by the number of columns M in the second embodiment. The generator will be specifically described. First, FIG. 5 is a circuit diagram illustrating the interleaved address generator 43 according to the second embodiment. Note that, in FIG. 5, the same components as those of the interleave address generator 1 of the above-described first embodiment are denoted by the same reference numerals, and a detailed description thereof will be omitted.

As shown in FIG. 5, the interleave address generator 43 of the second embodiment differs from the interleave address generator 1 of the first embodiment only in the configuration of the step width calculator 45. , Address counter 3 are exactly the same. The step width calculator 45 of the second embodiment is different from the step width calculator 5 of the first embodiment.
, The adder 25, the subtractor 27, the comparator 2
9, 33, the selectors 31, 35, and the OR circuit 41, instead of the output value of the F / F group 21 (ie, the current step width) and the number of columns from the column number input terminal T3 (= M).
When the count value of the address counter 3 (ie, the address output from the F / F group 11 of the address counter 3 to the memory) is 0,
A comparator 49 that outputs a high-level select signal and outputs a low-level select signal when the count value of the address counter 3 is not 0;
9 is high, the multiplier 4
7 is selected and output, and when the select signal from the comparator 49 is at a low level, a selector 51 for selecting and outputting the output of the F / F group 23 and a block size input from the output of the selector 51 A selector 53 compares the output of the selector 51 with the block size -1 from the block size input terminal T2, and compares the output of the selector 51 with the block size -1 from the block size input terminal T2. 51 is the block size -1 (= N ×
M-1), a high-level select signal is output. Otherwise (ie, when the output of the selector 51 is equal to or larger than the block size (= N × M)),
Comparator 55 for outputting low-level select signal
When the select signal from the comparator 55 is at a high level, the output of the selector 51 is input to the data terminal (D) of the F / F group 23, and when the select signal from the comparator 55 is at a low level, And a selector 57 for inputting the calculation result of (1) to the data terminal (D) of the F / F group 23.

Then, in this step width calculator 45,
The reset signal from the reset signal input terminal T4 is directly input to the reset terminal (RESET) of the F / F group 23. In the step width calculator 45 configured as above, when a high-level reset signal is input from the reset signal input terminal T4, the F / F group 2
3, the reset terminal (RE) of each flip-flop
SET) goes high, and
In the F / F group 21, the signals input to the preset terminal (SET) of the flip-flop of the first bit and the reset terminal (RESET) of the flip-flops of other bits become high level.

Therefore, similarly to the step width calculator 5 of the first embodiment, when a high-level reset signal is input from the reset signal input terminal T4, the clock input terminal T
All bits of the output value of the F / F group 23 become 0 in synchronization with the clock from 1. The output value of the F / F group 21 is
Only the first bit is 1, the other bits are 0,
As a result, the step width output to the address counter 3 becomes 1 as an initial value (see FIG. 6).

Then, thereafter, the reset signal input terminal T
When the reset signal from 4 goes low and the reset is released, the F / F group 23 latches and outputs the output of the selector 57 in synchronization with the clock. Here, in the step width calculator 45 of the second embodiment, when the count value of the address counter 3 is 0, the output value of the F / F group 21 and the number of columns ( = M) and the result of multiplication is output.
Further, the multiplication result of the multiplier 47 is equal to the block size -1.
If (= N × M−1) or less, the result of the multiplication is directly output from the selector 57 to the data terminal (D) of the F / F group 23, and conversely, the result of the operation of the multiplier 47 is the number of blocks (= If it is equal to or more than N × M, the block size −1 (= N × M−
The calculation result obtained by subtracting 1) is supplied from the selector 57 to the F / F
The data is output to the data terminal (D) of the group 23.

When the count value of the address counter 3 is not 0, the output of the F / F group 23 is selected and output from the selector 51.
3 is equal to or smaller than the block size −1 (= N × M−1), the output of the F / F group 23 is output from the selector 57 to the data terminal (D) of the F / F group 23 as it is,
Conversely, the output value of the F / F group 23 is the number of blocks (= N × M)
If so, the operation result obtained by subtracting the block size −1 (= N × M−1) from the output value of the F / F group 23 by the subtractor 53 is output from the selector 57 to the data terminal of the F / F group 23 ( D).

Therefore, the F / F group 23 includes a multiplier 47,
Subtractor 53, comparators 49 and 55, and selector 5
1 and 57, the F / F group 21
Block size -1 (= N × M-1) for the multiplied value obtained by multiplying the step width output from the above by the number of columns M
Is stored as a new step width at the time of interleave processing for the next block. Then, by this operation, the address counter 3
Is multiplied by the number of columns (= M) to the currently output step width, the value obtained by taking the modulo of the block size −1 (= N × M−1) is a new value at the time of the interleave processing for the next block. Set as step width.

On the other hand, in the step width calculator 45, similarly to the step width calculator 5 of the first embodiment, the reset signal from the reset signal input terminal T4 changes from the high level to the low level, and the reset is released. And F /
The F group 21 latches the output of the selector 39 that operates according to the select signal from the comparator 37 in synchronization with the clock, and outputs it as a step width. Then, the selector 39 determines that the select signal from the comparator 37 is at a low level (that is, the count value of the address counter 3 is not the block size -1 (= N × M-1)).
, The output of the F / F group 21 is input to the data terminal (D) of the F / F group 21. When the select signal from the comparator 37 is at a high level (that is, the count value of the address counter 3 is Size -1 (= N × M-1)
), The output of the F / F group 23 is input to the data terminal (D) of the F / F group 21.

Therefore, also in the step width calculator 45 of the second embodiment, the count value of the address counter 3 of the F / F group 21 is equal to the block size −1 (= N × M−1).
, The next clock timing (ie, the timing at which the count value of the address counter 3 returns to the initial value 0)
Then, a new step width for the next block stored in the F / F group 23 is latched, and the latched step width is determined by the count value of the address counter 3 and the block size minus 1 (= N × M− During the period of one block from 1) until the initial value is returned to 0, the data is output to the address counter 3.

FIG. 6 shows the operation of the interleave address generator 43 of the second embodiment according to the number of rows (the number of rows).
9 is a time chart illustrating an example in which an interleave process is performed with a block size of N = 4 and the number of columns (the number of columns) M = 3. Then, as shown in FIG. 6, the interleave address generator 43 of the second embodiment
The output value of the F group 23 is the data of the first block (D1-
At the second clock timing from the start of the period for inputting 1 to D1-12), the state changes from 0 to 3 and the start of the period for inputting data (D2-1 to D2-12) of the second block From the third clock to the ninth at the second clock timing, and the data (D3-
1 to D3-12) at the second and third clock timings from the start of the input period, the only point that sequentially changes from 9 to 16 to 5 is the interleaved address generator 1 of the first embodiment. Is different.

Also, with the interleave address generator 43 of the second embodiment, the addresses are output from the address counter 3 in exactly the same order as the interleave address generator 1 of the first embodiment. By simply providing one set of the interleave address generator 43 and the memory, continuous interleave processing can be performed on data of a plurality of blocks.

In the second embodiment, the address counter 3 corresponds to the address counting means, and the operation of the address counter 3 corresponds to the address counting process. The step width calculator 45 corresponds to a step width calculator, and the step width calculator 45
Corresponds to the step width setting process. Then, among the components constituting the step width calculator 45, F
/ F group 23, multiplier 47, subtractor 53, comparator 4
9 and 55 and the selectors 51 and 57 correspond to the step width setting means according to claim 3, and the comparator 37
The F / F group 21 and the selector 39 correspond to the step width output means according to the third aspect.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and it goes without saying that various forms can be adopted.
For example, in each of the above-described embodiments, the initial value of the step width output from the step width calculators 5 and 45 to the address counter 3 is 1, but the initial value of the step width is 1
Any integer greater than or equal to the integer may be used.

If the start address of the memory used for the interleave processing is not address 0, the value of the start address of the memory is added to the address output from the address counter 3 and the address after the addition is used as the address of the memory. What is necessary is just to supply it to an input terminal.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating an operation of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an interleaved address generator according to the first embodiment.

FIG. 3 is a circuit diagram illustrating a configuration of an interleaved address generator according to the first embodiment.

FIG. 4 is a time chart illustrating an operation of the interleave address generator in FIG. 3;

FIG. 5 is a circuit diagram illustrating a configuration of an interleaved address generator according to a second embodiment.

6 is a time chart showing the operation of the interleave address generator of FIG.

FIG. 7 is a block diagram illustrating a basic configuration of an interleave circuit using a conventional interleave address generator.

FIG. 8 is an explanatory diagram illustrating an operation of the interleave circuit of FIG. 7;

FIG. 9 is a block diagram showing a configuration of a conventional interleaving circuit for continuously interleaving data of a plurality of blocks.

FIG. 10 is a time chart illustrating an operation of the interleave circuit in FIG. 9;

[Explanation of symbols]

1,43 ... interleave address generator 3 ... address counter 5,45 ... step width calculator 11,21,23 ... flip-flop group (F / F group) 13,25 ... adder 15,27,53 ... subtractor
47: Multiplier 17, 29, 33, 37, 49, 55 ... Comparator 19, 31, 35, 39, 51, 57 ... Selector 4
1: OR circuit T1: Clock input terminal T2: Block size input terminal T3: Column number input terminal T4: Reset signal input terminal T5: Address output terminal

Claims (4)

[Claims] 1. A method of sequentially inputting data of N × M (where N and M are integers of 2 or more) as one block and writing the data to a memory, and writing the data written to the memory to an address different from the address at the time of writing. The interleave address generator is used to perform interleave processing of outputting input data in an order different from the order at the time of input by reading in the order of, and generating addresses for reading and writing to the memory. In synchronization with the clock, a count-up operation is performed from the initial value 0 with a step width input from the outside, and the count value is output as an address for reading and writing to the memory, and at the next clock timing. When the count value is equal to or more than the above (N × M), the value is modulo (N × M−1). The taken value is used as the count value at the next clock timing, and when the current count value becomes (N × M−1), the count value at the next clock timing is returned to the initial value 0. And a means for calculating the step width and outputting the calculated step width to the address counting means, wherein a value obtained by multiplying the currently output step width by M is (N × M−1 ) Is set as a new step width at the time of the interleave processing for the next block, and is synchronized with the timing at which the count value of the address counting means returns to the initial value 0, and is sent to the address counting means. And a step width calculating means for changing the output step width to the set new step width. Greed. 2. The interleave address generator according to claim 1, wherein the step width calculating means includes one block from when the count value of the address counting means changes from an initial value of 0 to (N × M−1). During the period
The currently output step width is cumulatively added for the M times, and the value obtained by taking the modulo of (N × M−1) for the cumulative added value is used as a new step width at the time of the interleave processing for the next block. The step width setting means to be set, and the count value of the address counting means is (N × M−
1) detecting means for detecting that the count value of the address counting means has become (N × M-1); And a step width output means for storing the new step width obtained at the next clock timing and outputting the stored step width to the address counting means. . 3. The interleave address generator according to claim 1, wherein the step width calculating means multiplies the currently output step width by the M, and calculates (N × M− Step width setting means for setting the value obtained by taking the modulo of 1) as a new step width at the time of the interleave processing for the next block; and the count value of the address counting means being (N × M−
Detecting means for detecting that the count value has become (1), and setting the step width setting means when the count value of the address counting means has become (N × M-1). And a step width output means for storing the new step width obtained at the next clock timing and outputting the stored step width to the address counting means. . 4. A method in which N × M (where N and M are integers of 2 or more) data as one block are sequentially input and written to a memory, and the data written to the memory has an address different from the address at the time of writing. The interleave address generation method is used for performing interleave processing of outputting input data in an order different from the order at the time of input by reading out in the order of, and generating addresses for reading and writing to the memory. The count is incremented from the initial value 0 at the set step width, and the count is sequentially output as an address for reading and writing to the memory, and the next count is equal to or more than the above (N × M). In the case of, the value obtained by taking the modulo of (N × M−1) for the value is set as the next count value, and Count value is (N × M
When -1) is reached, it comprises an address counting process for returning the next count value to the initial value 0, and a step width setting process for setting the step width used in the address counting process. In the width setting process, a value obtained by taking the modulo of (N × M−1) for a value obtained by multiplying the currently set step width by the above M is obtained as a new step width in the interleaving process for the next block. A step width used in the address counting process is updated to the obtained new step width in synchronization with a timing when the count value in the address counting process returns to the initial value 0.