JPH07193463A - Variable phase shifter - Google Patents

Abstract

PURPOSE:To provide a variable phase shifter for shifting the phase of any arbitrary waveform with small waveform distortion and high accuracy. CONSTITUTION:The cycle of input waveform data is extracted by a clock extracting circuit 6, the cyclic signal of its output is multiplied by a multiplier 7, and a clock signal CK is generated. The clock signal CK is applied to an A/D converter 2, D/A converter 4 and RAM 9, applied to a binary counter 8 and counted while simultaneously synchronizing them. Phase shift data are added to a count value C as the output of the counter 8 by an adder 10 and applied to the RAM 9 as address data DA. Corresponding to a waveform read/ write switching signal Srw, a switch 3 changes over the state of writing the input waveform in the RAM 9 and the state of reading and outputting waveform data in the RAM 9. By changing the phase shift data during reading, phase shifting is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable phase shifter, and more particularly to a variable phase shifter for digitally sampling an arbitrary repetitive waveform wave.

[0002]

2. Description of the Related Art Conventionally, a delay circuit has been used to shift the phase of a periodic wave other than a sine wave. However, in order to make the amount of phase shift variable, multiple delay circuits are required and the circuit scale becomes large. Also, when the frequency of the phase-shifted signal is low, a delay circuit using an integrating circuit is used. However, since the delay time has frequency characteristics, waveform distortion occurs when an arbitrary waveform is input.

Therefore, by storing the waveform data by digital sampling, reading them in synchronism with an appropriate clock to reproduce the waveform, and shifting the read address for reading the waveform data with respect to the clock signal. A small-sized variable phase shifter with less distortion has been considered. As a conventional example of such a variable phase shifter, the one shown in Japanese Patent Laid-Open No. 63-33908 is shown in FIG. In FIG. 2, reference numerals different from the reference numerals described in the drawing of the conventional example are shown. A variable phase shifter according to a conventional example includes an initial value control circuit 110, an address counter 109, a read only memory (ROM) 10
4 and a digital / analog (D / A) converter 105. In the initial value control circuit 110, since the output of the phase control circuit 107 is 0 in the normal waveform output state,
Only the value M is input to the adder 101. Comparator 10
Reference numeral 8 compares the output of the adder 101 with the value N, and outputs 0 when the value N is large and outputs the value N to the adder 102 otherwise. This value is added to the output of the adder 101 and returned to the adder 101 via the latch 103. Therefore, the output of the address counter 109 is equivalent to the counter output which outputs the value from 0 to N-1 by skipping M. The address counter 109 operates in synchronization with a fixed clock, and accordingly, the waveform data stored in the ROM 104 is read out and converted into an analog value by the D / A converter 105.
The phase shift value is output by outputting the phase jump value from the phase control circuit 107 for one clock and adding it to M.

[0004]

In the above-mentioned conventional example,
Since the waveform is limited to the data in ROM, it cannot support arbitrary waveforms. Further, since the data in the ROM is skipped at fixed address intervals, the read frequency becomes lower than the write sampling frequency in the ROM, and the upper limit frequency for reproduction becomes lower according to Nyquist's sampling theorem.

Therefore, one technical object of the present invention is to provide a variable phase shifter capable of phase shifting an arbitrary waveform, capable of performing phase shifting with small waveform distortion and with high accuracy.

Further, another technical object of the present invention is to provide a variable phase shifter capable of equalizing the write sampling rate and the read sampling rate to the memory.

[0007]

According to the present invention, in a variable phase shifter that shifts the phase of analog waveform data by a variable amount of phase shift, a clock generator that generates a clock signal according to the cycle of the analog waveform data. Means, address data generation means for generating address data according to the phase data representing the phase shift amount and the clock signal, and A / A for converting the analog waveform data into digital waveform data in synchronization with the clock signal. A variable phase shifter characterized by comprising D conversion means, RAM for storing the digital waveform data according to the address data, and switch means for switching between reading and writing of the digital waveform data with respect to the RAM.

According to the present invention, the clock generating means includes a clock extraction circuit for detecting the period of the analog waveform data to generate a periodic signal, and a multiplier for multiplying the periodic signal to form the clock signal. A variable phase shifter characterized by including is obtained.

According to the present invention, the address data generating means counts the clock signal to generate a count value, and adds the phase data to the count value to add the resultant value as the address data. A variable phase shifter is obtained which includes a generating adder.

According to the present invention, a RAM for storing waveforms
A counter for giving address data corresponding to the phase of the waveform data to the RAM; an adder for adding phase data to the counter output; and a D / A converter for converting the waveform data read from the RAM into an analog waveform. In a variable converter including: a clock extracting means for detecting a cycle of an input waveform; a multiplying means for multiplying the periodic signal to generate a clock signal; and a digital waveform for the input waveform in synchronization with the clock signal. A variable phase shifter characterized by comprising A / D conversion means for converting into data and switch means for switching between reading and writing of data from and into the RAM is obtained.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the variable phase shifter includes a clock generating means for generating a clock signal CK, an address data generating means for generating address data DA in synchronization with the clock signal CK, and an analog in synchronization with the clock signal CK. An analog / digital (A / D) conversion means for converting the waveform data IW into digital waveform data, and a clock signal CK
Random access memory (RA that stores address data DA and analog waveform data IW in synchronization with
M) 9 and switch means, the digital waveform data ID from the switch is converted into analog waveform data by the digital-analog (D / A) converter 4 synchronized with the clock signal CK, and output from the output port 5. Is output.

The clock generation means detects a cycle of the analog waveform data IW input from the input port 1 and generates a cycle signal T, and a clock signal CK that multiplies the cycle signal T by 2 ^n. Multiplier 7 that outputs
And have.

The address data generating means counts the clock signal CK and generates a count value C. n bits 2
The advance counter 8 and the phase shift adder 10 for adding the input phase shift data and the count value C and inputting the address data DA to the RAM 9 are provided.

The switch means is composed of a parallel digital switch and receives the input waveform read / write switching signal S.
The digital waveform data I for the RAM 9
It has a switch 3 for reading and writing D.

Next, the operation of the variable phase shifter shown in FIG. 1 will be described. Analog waveform data I coming in from port 1
The W input waveform is branched into two, one of which is input to the A / D converter 2 and converted into digital waveform data ID which is a digital signal. The other IW is the clock extraction circuit 6
The period T is extracted at. The frequency (1 / T) of the signal indicating the cycle T output from the clock extraction circuit 6 is multiplied by 2 ^{n by the} multiplier 7, and a clock signal CK having a frequency 2 ⁿ times the frequency of the signal of the cycle T is generated. To be done. The switch 3 writes the output of the A / D converter 2 to the RAM 9 in accordance with the waveform read / write signal S _rW input from the outside (hereinafter referred to as WRITE state) and the data in the RAM 9 to the D / A converter. The read state to 4 (hereinafter referred to as the READ state) is switched. The clock signal CK is counted by the n-bit binary counter 8 and its count value C0
~ 2 ^n-1 is output. The overflow of counter 8 is ignored. The count value C output of the counter 8 is added by the phase shift adder 9 with desired phase shift data DT,
It is given to the RAM 9 as address data DA. This corresponds to the phase of the waveform data. Since the frequency of the analog waveform data IW input from the input port 1 is multiplied by 2 ^{n in the} multiplier 7, the counter 8
Overflows once. The capacity of RAM9 is 2
^{There are n} words, and the RAM 9 can sample data for one waveform. Here 1 word is
It is the bit rate of the A / D converter 2 and the D / A converter 4. Therefore, when the switch 3 is in the WRITE state, the data of one waveform from the input 1 is A / D converted by the A / D converter 9 and written in the RAM 9, and in the READ state, RA
The waveform data in M9 is converted into an analog value by the D / A converter 4 and output. Further, by changing the phase shift data in the READ state, the read address of the RAM 9 is shifted and the output waveform is also phase shifted.

[0016]

As described above, in the variable phase shifter according to the present invention, the input waveform is sampled and stored in the RAM which is the storage means. Therefore, it is possible to shift the phase of any waveform and the waveform distortion is small. And it can be realized with high accuracy.

Further, according to the present invention, since it has a multiplication circuit for the clock signal extracted from the input waveform data, it is possible to make the sampling rate for writing to the RAM equal to the sampling rate for reading. Have.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

[Explanation of symbols]

 1 Input Port 2 A / D Converter 3 Switch 4 D / A Converter 5 Output Port 6 Clock Extraction Circuit 7 Multiplier 8 n-bit Binary Counter 9 RAM 10 Phase Shift Adder 101, 102, 106 Adder 103 Latch Circuit 104 ROM 105 D / A converter 107 Phase control circuit 108 Comparator 109 Address counter 110 Initial value setting circuit

Claims (4)

[Claims] 1. A variable phase shifter that shifts the phase of analog waveform data by a variable amount of phase shift, and a clock generation unit that generates a clock signal according to the cycle of the analog waveform data, and a phase representing the amount of phase shift. Address data generating means for generating address data according to data and the clock signal, and A / A for converting the analog waveform data into digital waveform data in synchronization with the clock signal.
A variable phase shifter comprising: a D conversion means, a RAM for storing the digital waveform data according to the address data, and a switch means for switching between reading and writing of the digital waveform data with respect to the RAM. 2. The clock generation means includes a clock extraction circuit that detects a period of the analog waveform data and generates a periodic signal, and a multiplier that multiplies the periodic signal to form the clock signal. The variable phase shifter according to claim 1, which is characterized in that. 3. The address data generation means includes a counter that counts the clock signal to generate a count value, and an adder that adds the phase data to the count value and generates an addition result value as the address data. The variable phase shifter according to claim 1, further comprising: 4. A RAM for storing a waveform, a counter for providing the RAM with address data corresponding to the phase of the waveform data, an adder for adding phase data to the counter output, and waveform data read from the RAM. In a variable converter including a D / A converter for converting into an analog waveform, a clock extracting means for detecting a cycle of an input waveform, a multiplying means for multiplying the periodic signal to generate a clock signal, and the clock signal 2. A variable phase shifter comprising: an A / D conversion means for converting the input waveform into digital waveform data in synchronism with the above; and a switch means for switching data read / write to the RAM.