JP4575398B2 - A / D converter - Google Patents

Description

  The present invention relates to a technique for enabling data signals output from a plurality of A / D converters to be stored in a time series without error in an interleaved A / D converter.

  As a technique for sampling a high-speed analog signal and converting it into a digital value, an interleaved A / D converter is realized.

  FIG. 6 shows the configuration of the interleaved A / D converter 10. For example, a plurality (four in this case) of the analog signal x (t) shown in FIG. The signal branches to the signal path and is input to the four A / D converters 12 (1) to 12 (4).

  Each of the A / D converters 12 (1) to 12 (4) has a phase shifted by ¼ of the predetermined period Ts in the predetermined period Ts, as shown in (b) to (e) of FIG. Phase sampling clocks Cs <b> 1 to Cs <b> 4 are supplied from the clock generator 13.

  As a result, from each A / D converter 12 (1) to 12 (4), as shown in (f), (h), (j), (l) of FIG. Data Da to Dd equivalent to the case where sampling is performed at a cycle can be obtained. Therefore, a signal having a frequency higher than the operation speed of the A / D converter can be converted into a data signal.

  Such an interleaved A / D converter is disclosed in, for example, the following Patent Document 1.

Japanese Patent No. 3756237

  For example, the frequency characteristics of the A / D converters 12 (1) to 12 (4) are corrected with respect to the time-series data signal obtained by sampling in such an interleaved A / D converter. When processing is performed, the data signal to be processed is temporarily stored, but it is necessary to generate a write permission signal necessary for the storage.

  In the generation of the write permission signal, each of the A / D converters 12 (1) to 12 (4) is a data signal as shown in (g), (i), (k), and (m) of FIG. The data clocks Ca to Cd for data acquisition that are output together with this are applied to the write enable signal generation circuit 14 as shown in FIG.

  The write enable signal generation circuit 14 receives the start signal S instructing to take in the data signal, and then, based on the data clocks Ca to Cd output from each A / D converter, the write enable signal Ea to Ed. Are generated in the order of sampling and supplied to the latch circuits 18 (1) to 18 (4) of the storage unit 17.

  Here, the write permission signal generation circuit 14 receives a start signal S at a data input terminal, and a latch circuit that receives a data clock Cd output from the A / D converter 12 (4) whose sampling order is the last one at a clock terminal. 15 and a latch circuit 16 (1) receiving the output of the latch circuit 15 at the data input terminal and receiving at the clock terminal the data clock Ca output from the A / D converter 12 (1) whose sampling order is first. The latch circuit 16 (2) receives the output of the latch circuit 16 (1) at the data input terminal and receives the data clock Cb output from the A / D converter 12 (2) whose sampling order is the second highest at the clock terminal. Then, the output of the latch circuit 16 (2) is received at the data input terminal, and the data clock Cc output by the A / D converter 12 (3) whose sampling order is third is clocked. The latch circuit 16 (3) received at the terminal and the output of the latch circuit 16 (3) are received at the data input terminal, and the data clock Cd output from the A / D converter 12 (4) whose sampling order is the fourth place. Latch circuit 16 (4) received at the clock terminal, and outputs of the latch circuits 16 (1) to 16 (4) are used as write enable signals Ea to Ed, and the latch circuits 18 (1) to 18 of the storage unit 17 are used. 18 (4).

  Data signals Da to Dd output from the A / D converters 12 (1) to 12 (4) are input to the data terminals of the latch circuits 18 (1) to 18 (4) of the storage unit 17, respectively. Data clocks Ca to Cd are respectively input to the clock terminals.

  Therefore, as shown in FIG. 7 (n), when the start signal S is input at an arbitrary timing t0, the output of the latch circuit 15 (overall permission signal) at the timing t1 when the data clock Cd is first input after the input. ) E rises as shown in (o) of FIG. 7, and then the write enable signal Ea is outputted as shown in (p) of FIG. 7 at the timing t2 when the data clock Ca rises, and then the data clock Cb rises. At time t3, the write enable signal Eb is output as shown in (q) of FIG. 7, and thereafter, at the timing t4 when the data clock Cc rises, the write enable signal Ec is output as shown in (r) of FIG. At the timing t5 when the data clock Cd rises, the write enable signal Ed is output as shown in (s) of FIG.

  Therefore, the data signals Da (2), Db (2), Dc (2), and Dd (2) are temporarily stored in the latch circuits 18 (1) to 18 (4) of the storage unit 17 as the first valid data. Thereafter, subsequent data signals are stored in the order of sampling.

  However, as described above, after the start signal S is input, the data clock Cd output first by the A / D converter 12 (4) whose sampling order is final and the data output by the first A / D converter 12 (1) are output. In the method of generating the whole permission signal E with the clock Ca and sequentially transmitting it to the latch circuit having the lower sampling order to generate the write permission signal, the phase margin is only 1 / N of the data clock Ca. In some cases, the input order of the data clock to the write permission signal generation circuit 14 differs from the desired sampling order due to environmental changes or the like.

  For example, the data signal Db and the data clock Cb of the second A / D converter 12 (2) in FIGS. 8C and 8D are the first ones in FIGS. 8A and 8B. When the data signal Da of the A / D converter 12 (1) precedes the data clock Ca, a set of four data stored first is Da (2), Db (3), Dc (3), Dd ( 3) and data continuity is lost.

  An object of the present invention is to provide an A / D converter capable of solving the above-described problems, having a large phase margin, and capable of stably capturing data.

In order to achieve the above object, an A / D conversion device according to claim 1 of the present invention comprises:
A signal branching section (21) for branching an analog signal into a plurality of N signal paths;
A clock generator (23) for generating N-phase sampling clocks (Cs1 to Cs4) whose phases are shifted by 1 / N of the predetermined period in a predetermined period;
The analog signal branched by the signal branching unit and the N-phase sampling clock are received, the analog signal is sampled at the input timing of the sampling clock, converted into data signals (Da to Dd), and output. A plurality of N A / D converters (22 (1) to 22 (4)) for outputting data clocks (Ca to Cd) for taking in the data signals;
A write permission signal generation circuit (24) for generating a write permission signal for the data signal based on the data clock after receiving a start signal instructing data acquisition;
In an A / D converter having a storage unit (28) that receives the write enable signal and the data clock and performs storage processing on the data signal output from each A / D converter,
The write enable signal generating circuit is
Inversion means (25 (1), 25 (2)) for inverting the data clock output from the even-numbered A / D converters counted in the sampling order among the plurality of N A / D converters;
A plurality of N latch circuits (26 (1) to 26 (4)) provided one by one corresponding to the plurality of N A / D converters,
The plurality of N latch circuits are connected in series so that the (N-1) th latch output is input to the Nth data input terminal,
A data clock output from the odd-numbered A / D converters in the sampling order among the plurality of N A / D converters is supplied to a clock terminal of the latch circuit corresponding to the odd-numbered A / D converters, The inverted output of the data clock of the even-numbered A / D converter counted in the sampling order among the plurality of N A / D converters is given to the clock terminal of the latch circuit corresponding to the even-numbered A / D converter. It is characterized by being configured as described above.

The A / D converter according to claim 2 of the present invention is the A / D converter according to claim 1,
The write permission signal generation circuit includes:
Including N shift circuits (27 (1) to 27 (1)) for delaying the latch outputs of the respective latch circuits by a predetermined stage shift with a data clock from the corresponding A / D converter,
Among the N shift circuits, the odd-numbered and even-numbered consecutive sampling orders are set as one set, and the number of shift stages in each set is decreased by one stage in the sampling order.

  Thus, in the write enable signal generating circuit of the A / D converter according to claim 1 of the present invention, after the start signal is input, the data clock of the A / D converter whose sampling order is the first is first in a predetermined direction. The transition timing is detected by the latch circuit, and a write permission signal for the data signal of the A / D converter is output at the timing. The latch circuit detects when the inverted output of the data clock output from the second A / D converter first transitions in a predetermined direction after the data clock of the first A / D converter is latched. At that timing, a write permission signal for the data signal of the A / D converter is output.

  Here, the difference between the timing at which the first data clock in the sampling order is latched and the timing at which the inverted output of the second data clock is latched is (N / 2 + 1) / of the period of the data clock in the ideal state. N.

  Similarly, the difference between the timing at which the third data clock in the sampling order is latched and the timing at which the inverted output of the fourth data clock is latched is (N / 2 + 1) / of the period of the data clock in the ideal state. N. The timing at which the write enable signal corresponding to the A / D converter with the second highest sampling order is output and the timing at which the write enable signal corresponding to the third A / D converter is output. The difference is (N / 2 + 1) / N of the period of the data clock in the ideal state.

  Thereafter, the same processing is performed to generate a write permission signal corresponding to the data signal of each A / D converter. Therefore, the phase margin is increased as compared with the conventional case, and stable data fetch processing can be performed.

  In the write enable signal generating circuit of the A / D converter according to claim 2 of the present invention, a shift circuit for shifting the output of the latch circuit and supplying it to the storage unit is provided, so that it is stored first after the start signal is input. Can be used effectively from the data signal.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration of an A / D conversion apparatus 20 to which the present invention is applied.

  The A / D converter 20 branches an analog signal x (t) into a plurality of N signal paths (hereinafter described in an example where N = 4) by a signal branching unit 21, and each A / D converter 22 ( 1) to 22 (4).

  These A / D converters 22 (1) to 22 (4) are respectively supplied with four-phase sampling clocks Cs 1 to Cs 4 whose phases are shifted by Ts / 4 at a predetermined period Ts generated by the clock generator 23. The analog signal x (t) is equivalently sampled with the period Ts / N.

  Each A / D converter 22 (1) to 22 (4) is configured to output data signals Da to Dd obtained by sampling and to output data clocks Ca to Cd synchronized with the data signals. ing.

These data clocks Ca to Cd are input to the write enable signal generation circuit 24.
The write permission signal generation circuit 24 permits writing of data signals obtained in the order of sampling with the specific A / D converter 22 (1) as the head after receiving the start signal S instructing the start of data acquisition. In this embodiment, after the data clocks Ca to Cd respectively output from the A / D converters 22 (1) to 22 (4) are received and the start signal S is input, Then, four-phase write enable signals Ea to Ed whose levels transition in synchronization with the data clock level transition timing are generated.

  More specifically, as shown in FIG. 1, the A / D converters 22 (2) and 22 (22 (2), 22 (1) having a specific A / D converter 22 (1) at the head and the even-numbered sampling order. 4) inverters 25 (1) and 25 (2) for respectively inverting the data clocks Cb and Cd output, and four latch circuits respectively corresponding to the A / D converters 22 (1) to 22 (4). 26 (1) to 26 (4) are provided.

  The latch circuits 26 (1) to 26 (4) follow the sampling order starting from the A / D converter 22 (1), and the latch output of the upper latch circuit corresponding to the A / D converter is the lower latch. Data clocks Ca and Cc output from the odd-numbered A / D converters 22 (1) and 22 (3) are connected in cascade so as to be input to the data input terminal of the circuit, respectively. The data clocks Cb and Cd received by the clock terminals of the latch circuits 26 (1) and 26 (3) and output by the even-numbered A / D converters 22 (2) and 22 (4) are the inverter 25. Inversion results Cb ′ and Cd ′ are received at the clock terminals of the latch circuits 26 (2) and 26 (4).

  The latch outputs of the latch circuits 26 (1) to 26 (4) are input to the storage unit 28 together with the data clocks Ca to Cd and the data signals Da to Dd as four-phase write enable signals Ea to Ed.

  The storage unit 28 may have any configuration depending on the processing of the subsequent device for the acquired data. For example, there are a case where processing is performed after addressing to a memory such as a RAM and a predetermined amount of data is written, or a case where data is temporarily stored and processed immediately. The latter case will be described here.

  In this case, as shown in FIG. 1, the storage unit 28 includes a plurality of latch circuits 29 (1) to 29 (4) for temporarily storing data.

  Data signals Da to Dd are respectively input to the data terminals of the latch circuits 29 (1) to 29 (4), and data clocks Ca to Cd are respectively input to the clock terminals. Further, write enable signals Ea to Ed are input to the enable terminals, respectively.

  Therefore, after the write enable signal Ea transits from 0 to 1, the data signal Da output from the A / D converter 22 (1) is first latched at the timing when the data clock Ca rises first. The data signal Db output from the A / D converter 22 (2) at the timing when the data clock Cb rises after the write enable signal Eb transits from 0 to 1 The data is temporarily stored in the latch circuit 29 (2), and further, output from the A / D converter 22 (3) at the timing when the data clock Cc rises after the write enable signal Ec transits from 0 to 1. After the data signal Dc is temporarily stored in the latch circuit 29 (3) and the write enable signal Ed finally transits from 0 to 1, the A / D change occurs at the timing when the data clock Cd rises. Vessel 22 data signal Dd which is outputted from the (4) is temporarily stored in the latch circuit 29 (4).

  Thereafter, while the write enable signals Ea to Ed are kept at 1, the data in the latch circuits 29 (1) to 29 (4) of the storage unit 28 are respectively synchronized with the data clocks Ca to Cd. Updated. The temporarily stored data is output to a subsequent processing device (not shown) to perform desired processing.

Next, the operation of the A / D conversion device 20 of this embodiment will be described.
By sampling the analog signal x (t), for example, the data signals Da to Dd of (b), (d), (f), and (h) of FIG. 2 and (c), (e), (g), (i ) Data clocks Ca to Cd are output from the A / D converters 22 (1) to 22 (4), and the start signal S is input at time t0 as shown in FIG. Then, the output Ea of the latch circuit 26 (1) rises at the timing t1 when the data clock Ca first rises from the input timing of the start signal S, and is output as a write enable signal as shown in FIG. 2 (j).
Further, the output Eb of the latch circuit 26 (2) rises at the timing t2 when the data clock Cb first falls after the output Ea of the latch circuit 26 (1) rises, and writing is permitted as shown in FIG. 2 (k). Output as a signal.

  Similarly, the output Ec of the latch circuit 26 (3) rises at the timing t3 when the data clock Cc first rises after the output Eb of the latch circuit 26 (2) rises, and writing is permitted as shown in (l) of FIG. The output Ed of the latch circuit 26 (4) rises at the timing t4 when the data clock Cd first falls after the output Ec of the latch circuit 26 (3) rises, as shown in FIG. It is output as a write permission signal.

Note that each interval between the signals Ea to Ed in the ideal state of FIG. 2 is 3Ts / 4.
These write permission signals Ea to Ed are input to the latch circuits 29 (1) to 29 (4) of the storage unit 28.

  Therefore, the latch circuit 29 (1) temporarily stores the data signal Da (2) at the timing t1 ″ at which the data clock Ca first rises after the timing t1 at which the write enable signal Ea transitions to 1.

  Similarly, the data signal Db (2) at the timing t2 ″ at which the data clock Cb rises first after the timing t2 when the write enable signal Eb transits to 1 is temporarily stored, and the write enable signal Ec transits to 1. The data signal Dc (3) at the timing t3 ″ when the data clock Cc first rises after the timing t3 is temporarily stored as valid data, and after the timing t4 when the write permission signal Ed changes to 1, the data clock Cb is first generated. The data signal Dd (3) at the rising timing t4 ″ is temporarily stored as valid data.

  Thereafter, the data in the storage unit 28 is updated at the rising timing of each of the data clocks Ca to Cd.

  Of the data signals Da and Db, the data signals Da (2) and Db (2) that are first stored in the storage unit 28 after the output of the start signal S are data signals corresponding to the data signals Da (2) and Db (2). Since Dc (2) and Dd (2) are not stored, they are discarded and used as valid data from subsequent Da (3) and Db (3). The determination of the discard data is determined in advance by the number N of stages.

  The operation example of FIG. 2 is a case where the data signals and data clocks output from the A / D converters 22 (1) to 22 (4) are output in the sampling order at the ideal timing. In the A / D conversion device 20 of this embodiment, as described above, the write enable signal is output at the rising timing for the odd-numbered data clock, and the write is enabled at the falling timing for the even-numbered data clock. As a result, the phase margin is expanded to (1 / N + 1/2) π of the data clock as compared with the conventional example having only 1 / N of the data clock, and each A / D converter 22 ( Even if the relative phase between the outputs 1) to 22 (4) slightly varies, the continuity of the data set stored in the storage unit 28 can be maintained.

  Thus, in the A / D conversion device 20 of the present embodiment, the sampling order is set for the data clocks Ca to Cd output from the A / D converters 22 (1) to 22 (4) together with the data signals, respectively. The write enable signals Ea to Ed are generated by latching the odd-numbered data clocks as they are, and by latching the inverted outputs of the even-numbered data clocks, and performing the storage process for the respective data. Yes.

  For this reason, even when high-speed sampling is performed, data acquisition processing can be performed stably with a sufficient phase margin.

(Second Embodiment)
In the first embodiment described above, the latch output of each of the latch circuits 26 (1) to 26 (4) is used as a write permission signal. However, like the A / D converter 20 'of the second embodiment shown in FIG. In addition, the latch outputs of the latch circuits 26 (1) to 26 (4) are delayed by the shift circuits 27 (1) to 27 (4), and this is given to the storage unit 28 as a write permission signal. Good. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

  Each of the shifts 27 (1) to 27 (4) receives the latch outputs of the latch circuits 26 (1) to 26 (4), shifts by a predetermined stage with the corresponding data clock, and shifts by four stages. Ea ′ to Ed ′ are generated.

  Here, the number of shift stages of the shift circuits 27 (1) to 27 (4) is a set of two odd and even numbers that are consecutive in the sampling order, and M stages and M−1 stages from the group that precedes the sampling order. , M-2 stages,...

  M is an arbitrary value equal to or greater than N / 2. As described above, when N = 4, the minimum configuration is M = 2, and the shift circuits 27 (1) and 27 (2) of the set preceded by sampling are 2 In the stage shift configuration, the remaining sets of shift circuits 27 (3) and 27 (4) have a one-stage shift configuration.

  Four-phase write enable signals Ea ′ to Ed ′ output from the shift circuits 27 (1) to 27 (4) are input to the storage unit 28 together with the data clocks Ca to Cd and the data signals Da to Dd.

  In the storage unit 28, the data signal Da output from the A / D converter 22 (1) is latched at the timing when the data clock Ca first rises after the write enable signal Ea ′ transitions from 0 to 1. The data is temporarily stored in the circuit 29 (1), and then output from the A / D converter 22 (2) at the timing when the data clock Cb rises after the write enable signal Eb 'transits from 0 to 1. The data signal Db is temporarily stored in the latch circuit 29 (2), and after the write enable signal Ec ′ transitions from 0 to 1, the A / D converter 22 (3 ) Is temporarily stored in the latch circuit 29 (3), and finally the timing at which the data clock Cd rises after the write enable signal Ed ′ transitions from 0 to 1 Data signal Dd which is output from the A / D converter 22 (4) is temporarily stored in the latch circuit 29 (4).

  Thereafter, while the write permission signals Ea ′ to Ed ′ are kept at 1, the data in the latch circuits 29 (1) to 29 (4) of the storage unit 28 are synchronized with the data clocks Ca to Cd. Updated respectively. The temporarily stored data is output to a subsequent processing device (not shown) to perform desired processing.

Next, the operation of the A / D conversion device 20 ′ of the second embodiment will be described.
By sampling the analog signal x (t), for example, the data signals Da to Dd of (b), (d), (f), and (h) of FIG. 4 and (c), (e), (g), (i ) Data clocks Ca to Cd are output from the A / D converters 22 (1) to 22 (4), and the start signal S is input at time t0 as shown in FIG. The output Ea of the latch circuit 26 (1) rises at the timing t1 when the data clock Ca first rises from the input timing of the start signal S, and at the timing t1 'when the data clock Ca rises for the second time from this time t1. The write enable signal Ea ′ that rises as shown in (j) of FIG.

  The output Eb of the latch circuit 26 (2) rises at a timing t2 when the data clock Cb first falls after the output Ea of the latch circuit 26 (1) rises, and the data clock Cb rises the second time from this time t2. At the timing t2 ', the write enable signal Eb' that rises as shown in (k) of FIG. 4 is output.

  Similarly, the output Ec of the latch circuit 26 (3) rises at the timing t3 when the data clock Cc first rises after the output Eb of the latch circuit 26 (2) rises, and the data clock Cc rises for the first time from this time t3. The write enable signal Ec 'rising at the timing t3' as shown in (l) of FIG. 4 is output, and the latch circuit 26d at the timing t4 when the data clock Cd first falls after the output Ec of the latch circuit 26 (3) rises. The output Ed at 26 (4) rises, and the write enable signal Ed 'rises as shown in FIG. 4 (m) at the timing t4' when the data clock Cd rises for the first time from time t4.

  Note that each interval between the signals Ea to Ed in the ideal state of FIG. 4 is 3Ts / 4, and each interval between the write enable signals Ea ′ to Ed ′ obtained by shifting them by two stages or one stage is Ts / 4. It has become.

  These write permission signals Ea ′ to Ed ′ are input to the latch circuits 29 (1) to 29 (4) of the storage unit 28.

  Therefore, the latch circuit 29 (1) temporarily stores the data signal Da (4) at the timing t1 ″ at which the data clock Ca first rises after the timing t1 ′ at which the write enable signal Ea ′ transitions to 1 as valid data. Remembered.

  Similarly, the data signal Db (4) at the timing t2 ″ at which the data clock Cb first rises after the timing t2 ′ at which the write permission signal Eb ′ transitions to 1 is temporarily stored as valid data, and the write permission signal The timing at which the data signal Dc (4) at the timing t3 ″ at which the data clock Cc first rises after the timing t3 ′ at which Ec ′ transitions to 1 is temporarily stored as valid data, and the timing at which the write enable signal Ed ′ transitions to 1. The data signal Dd (4) at the timing t4 ″ when the data clock Cb first rises after t4 ′ is temporarily stored as valid data.

  In the first embodiment, the data signal stored first after the output of the start signal S is discarded depending on the number of stages N and may not be used effectively. However, in the second embodiment, it is not necessary to determine whether or not to discard. All data can be used effectively.

  Thereafter, the data in the storage unit 28 is updated at the rising timing of each of the data clocks Ca to Cd.

  The operation example of FIG. 4 is a case where the data signals and data clocks output from the A / D converters 22 (1) to 22 (4) are output in the sampling order at the ideal timing. In the A / D conversion device 20 'of this embodiment, as described above, the odd-numbered data clock is shifted by a predetermined number of stages from the rising timing, and the even-numbered data clock is shifted by the predetermined number of stages from the falling timing. Since the shift is performed, even if the relative phase between the outputs of the A / D converters 22 (1) to 22 (4) slightly varies, the continuity of the data set stored in the storage unit 28 is increased. Can be held.

  For example, as shown in FIG. 5, the data signal Db and the data clock Cb of the A / D converter 22 (2) precede the ideal timing, and the first data clock Cb after the start signal is input has the falling timing t2. When it comes immediately after the rising timing t1 of the data clock Ca, the timing t2 'at which the write enable signal Eb' rises precedes the time t1 'as shown in FIG. 3 (j), and the next rising edge of the data clock Cb. The data signal Db (4) input at the timing t2 ″ can be stored together with the other data signals Da (4), Dc (4), Dd (4) in the fourth set, and the continuity of data is Although not shown, even when the data signal Db and the data clock Cb of the A / D converter 22 (2) are delayed from the ideal timing, It can store the data signals Db (4) time.

  This phase margin is caused by shifting the inverted output of the even-numbered data clock with respect to the odd-numbered data clock, and when N = 4 as described above, 3π / of the data clock period. 4 and can be represented by N, which is (1 + N / 2) / N.

  As described above, in the A / D conversion device 20 ′ of the second embodiment, sampling is performed on the data clocks Ca to Cd output from the A / D converters 22 (1) to 22 (4) together with the data signals, respectively. Latch the odd-numbered data clock as it is, latch the inverted output of the even-numbered data clock, and write permission by shifting the latch output by a predetermined number of stages with each data clock Signals Ea ′ to Ed ′ are generated, and storage processing for each data is performed.

  For this reason, even when high-speed sampling is performed, data acquisition processing can be performed stably with a sufficient phase margin, and all acquired data can be used effectively.

Configuration diagram of the first embodiment of the present invention Operation explanatory diagram in the ideal state of the first embodiment Configuration diagram of second embodiment of the present invention Operation explanatory diagram in the ideal state of the second embodiment Operation explanatory diagram at the time of phase fluctuation of the second embodiment Configuration diagram of conventional equipment Operation explanatory diagram in the ideal state of the conventional device Operation explanatory diagram at the time of phase fluctuation of the conventional device

Explanation of symbols

  20, 20 '... A / D converter, 21 ... signal branching unit, 22 ... A / D converter, 23 ... clock generator, 24 ... write permission signal generation circuit, 25 ... inverter , 26 ... latch circuit, 27 ... shift circuit, 28 ... storage unit, 29 ... latch circuit

Claims (2)

A signal branching section (21) for branching an analog signal into a plurality of N signal paths;
A clock generator (23) for generating N-phase sampling clocks (Cs1 to Cs4) whose phases are shifted by 1 / N of the predetermined period in a predetermined period;
The analog signal branched by the signal branching unit and the N-phase sampling clock are received, the analog signal is sampled at the input timing of the sampling clock, converted into data signals (Da to Dd), and output. A plurality of N A / D converters (22 (1) to 22 (4)) for outputting data clocks (Ca to Cd) for taking in the data signals;
A write permission signal generation circuit (24) for generating a write permission signal for the data signal based on the data clock after receiving a start signal instructing data acquisition;
In an A / D converter having a storage unit (28) that receives the write enable signal and the data clock and performs storage processing on the data signal output from each A / D converter,
The write enable signal generating circuit is
Inversion means (25 (1), 25 (2)) for inverting the data clock output from the even-numbered A / D converters counted in the sampling order among the plurality of N A / D converters;
A plurality of N latch circuits (26 (1) to 26 (4)) provided one by one corresponding to the plurality of N A / D converters,
The plurality of N latch circuits are connected in a column so that the (N-1) th latch output is input to the Nth data input terminal,
A data clock output from the odd-numbered A / D converters in the sampling order among the plurality of N A / D converters is supplied to a clock terminal of the latch circuit corresponding to the odd-numbered A / D converters, The inverted output of the data clock of the even-numbered A / D converter counted in the sampling order among the plurality of N A / D converters is given to the clock terminal of the latch circuit corresponding to the even-numbered A / D converter. An A / D converter characterized by being configured as described above. The write permission signal generation circuit includes:
Including N shift circuits (27 (1) to 27 (1)) for delaying the latch outputs of the respective latch circuits by a predetermined stage shift with a data clock from the corresponding A / D converter,
2. The N shift circuits are configured such that the odd-numbered and even-numbered consecutive sampling orders are one set, and the number of shift stages of each set is decreased by one stage in the sampling order. The A / D conversion device described.

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