KR100882725B1 - Apparatus for converting synchronous data - Google Patents

Abstract

In the process of exchanging predetermined data or processing predetermined data among various systems, data that is not synchronized with the reference clock signal is accurately synchronized with the reference clock signal due to different time delays of various components.

The first synchronous converter synchronizes and stores the asynchronous data with the reference clock signal to generate a first comparison signal, and the second synchronous converter synchronizes and stores the asynchronous data with the reference clock signal after inverting and delaying the set time, thereby comparing the second. The first synchronous conversion unit and the second synchronous conversion unit to generate a signal, and the first synchronous conversion unit compares the polarity of the first comparison signal and the second comparison signal respectively generated by the synchronous data generation unit when the polarities are different. The data synchronized with the signal is generated as the synchronization data according to the reference clock signal. When the polarities are the same, the polarity of the generated synchronization data is inverted to generate the synchronization data according to the reference clock signal.

Sync, data, conversion, reference clock signal

Description

Apparatus for converting synchronous data}

1 is a circuit diagram showing a configuration of a conventional converter,

2 is an operation waveform diagram of each part of FIG.

3 is a circuit diagram showing the configuration of the converter of the present invention,

4 is an operation waveform diagram of each part of FIG. 3 in the normal operation;

FIG. 5 is a view illustrating operation waveforms of each part of FIG. 3 when data loss occurs.

* Description of the symbols for the main parts of the drawings *

200: first synchronous conversion unit 201, 213: first and second multiplexers

203, 207, and 215: first to third latches 205 and end gates

210: second synchronous conversion unit 211: inverter

220: synchronous data generator 221: comparison / multiplexer

223: D flip-flop BCLK: reference clock signal

RST1, RST2: first and second reset signals

COMP1, COMP2: first and second comparison signals

The present invention relates to a synchronous data converter for synchronizing asynchronous data with a reference clock signal accurately.

In general, when various systems using the same reference clock signal exchange data with each other or process predetermined data, data may not be synchronized exactly with the reference clock signal due to different time delays of various components. There are many cases.

If the data is not correctly synchronized with the reference clock signal, an error occurs in the detection of the data and is lost. Therefore, when data is not synchronized with the reference clock signal, the data must be converted to be correctly synchronized with the reference clock signal.

1 is a circuit diagram showing the configuration of a conventional synchronous data converter. As shown in FIG. 1, the latch is reset according to the first reset signal RST1 and enabled according to the second reset signal RST2 to output a signal of the input terminal IN to the output terminal Q. 100 and a multiplexer 110 for selectively outputting the output data or the asynchronous data of the latch 100 according to the reference clock signal BCLK and feedbacking the input data to the input terminal IN of the latch 100. The AND gate 120 logically multiplies the output data of the multiplexer 110 and the second reset signal RST2, and is reset according to the second reset signal RST2, and reset according to the reference clock signal BCLK. The D-type flip-flop 130 stores output data of the AND gate 120 and outputs the synchronous data.

In the conventional converter configured as described above, the reset terminal RST of the latch 100 and the D-type flip-flop 130 have the first reset signal RST1 and the second reset signal RST2 at low potential. Reset of the latch 100 and the D-type flip-flop 130 when the first reset signal RST1 and the second reset signal RST2 become high potential after being applied and reset to the terminal RST, respectively. Is released, and the latch 100 is enabled by applying the high potential second reset signal RST2 to the enable terminal EN.

In this state, the asynchronous data input as shown by the waveform (a) of FIG. 2 is applied to the input terminal IN2 of the multiplexer 110, and the reference clock signal as shown by the waveform (b) of FIG. BCLK is applied to the selection terminal SEL of the multiplexer 110.

Then, the multiplexer 110 selects and outputs asynchronous data of the input terminal IN2 during the low potential period of the reference clock signal BCLK, and the output data is inputted to the input terminal IN of the latch 100, so the latch is latched. 100 stores the output data of the multiplexer 110, outputs the output data to the output terminal Q as shown by the waveform (c) of FIG. 2, and is input to the input terminal IN1 of the multiplexer 110.

The multiplexer 110 selects and outputs data output from the latch 100 and input to the input terminal IN1 during the high potential period of the reference clock signal BCLK. BCLK), predetermined data is output as shown by waveform (d) of FIG. 2. That is, the multiplexer 110 selects the signal of the input terminal IN1 when the reference clock signal BCLK is in the high potential period and the asynchronous operation of the input terminal IN2 when the reference clock signal BCLK is in the low potential period. The data is selected and asynchronous data is output in synchronization with the reference clock signal BCLK, as shown by the waveform (d) of FIG. 2.

The output data of the multiplexer 110 is logically multiplied by the second reset signal RST2 at the AND gate 120, and the output signal of the AND gate 120 is input to the D-type flip-flop 130. It is inputted to D) and again synchronized to the reference clock signal BCLK, and then output as shown by the waveform (e) of FIG.

The conventional technology is that the multiplexer 110 selects asynchronous data and converts it into synchronous data while storing it in the latch 100 during the low potential period of the reference clock signal BCLK. Although accurate synchronization can be outputted, data continuously changing for each reference clock signal at the same frequency cannot be converted to synchronization data correctly and an error occurs.

For example, when the asynchronous data cannot be stored in the latch 100 at time t1 due to the operation time delay of the latch 100 or the delay of the asynchronous data, the latch 100 continues to store the previously asynchronous data. The data is retained, and the asynchronous data thus retained affects the synchronous data output from the D-type flip-flop 130, thereby losing data of one section. That is, if the current change in the asynchronous data is maintained until the next reference clock signal BCLK is input, the next reference clock signal BCLK is outputted as synchronous data, but the asynchronous data is the same as the reference clock signal BCLK. There is a problem in that current data is lost when it is changed or input in the form of a signal of data.

 Accordingly, an object of the present invention is to provide a synchronous data converting apparatus that converts asynchronous data into synchronous data accurately without losing time even if a time delay or the like occurs.

In the synchronous data conversion device of the present invention having the above object, the first synchronous conversion unit synchronizes the asynchronous data to the reference clock signal, stores the data synchronized therein, and generates the first comparison signal, and the second synchronous conversion unit generates the asynchronous data. After delaying the inversion and setting time, it synchronizes with the reference clock signal, stores the synchronized data, generates the second comparison signal, and compares the polarity of the first comparison signal and the second comparison signal with the synchronization data generator. The first synchronization converter generates data synchronized with the reference clock signal as the synchronization data, and when the polarity is the same, the data inverting the polarity of the synchronization data is generated as the synchronization data.

The first synchronous converter is configured to select a feedback input signal or asynchronous data according to a reference clock signal by a first multiplexer, and a first latch is reset according to a first reset signal and is enabled according to a second reset signal. The select data of the first multiplexer is stored and output as a first comparison signal, and AND gates logically multiply output data of the first multiplexer and the first latch, and a second latch is reset according to the first reset signal. It is set and enabled according to the second reset signal, and stores the output data of the AND gate to be input to the first multiplexer as a feedback input signal.

The second synchronous conversion unit, the inverter inverts and delays the asynchronous data, the second multiplexer selects the output data or the second comparison signal of the inverter according to the reference clock signal, the third latch is the first reset The output data of the second multiplexer may be stored and reset as a second comparison signal while being reset according to the signal and enabled according to the second reset signal.

The synchronization data generation unit selects data synchronized with the reference clock signal by the first synchronization converter when the comparison / multiplexer compares the first comparison signal and the second comparison signal with different polarities, and has the same polarity. Selects inverted synchronous data, and the D-type flip-flop outputs the output data of the comparison / multiplexer as the synchronous data according to a reference clock signal, and generates inverted synchronous data inverted the synchronous data and inputs the inverted synchronous data to the comparison / multiplexer. It is characterized by.

Hereinafter, the synchronous data converter of the present invention will be described in detail with reference to the accompanying drawings of FIGS. 3 to 5.

3 is a circuit diagram showing the configuration of the synchronous data converter of the present invention. As shown in FIG. 1, the first synchronous conversion unit 200 which synchronizes asynchronous data with the reference clock signal BCLK, stores the synchronized data, and generates the first comparison signal COMP1, and inverts and sets the asynchronous data. The first comparison between the second synchronous conversion unit 210 and the first synchronous conversion unit 200 generated after the time delay is synchronized with the reference clock signal and stores the synchronized data generated as the second comparison signal COMP2. When the polarities are different by comparing the polarities of the signal COMP1 and the second comparison signal COMP2 of the second synchronous conversion unit 210, the first synchronous conversion unit 200 is applied to the reference clock signal BCLK. The synchronization data generator 220 generates synchronization data as synchronization data and generates data in which the polarity of the synchronization data is inverted as synchronization data when the synchronization data is generated as synchronization data.

The first synchronous conversion unit 200 includes a first multiplexer 201 for selecting data of the input terminal IN11 or asynchronous data of the input terminal IN12 according to the reference clock signal BCLK, and a first reset. A first latch 203 that is reset according to the signal RST1 and enabled according to the second reset signal RST2, and stores the data selected by the first multiplexer 201 and outputs the selected data as the first comparison signal COMP1. ), An AND gate 205 for logically multiplying the output data of the first multiplexer 201 and the first latch 203, and a second reset signal according to the first reset signal RST1. The second latch 207 is enabled according to RST2 and stores the output data of the AND gate 205 and inputs the input data to the input terminal IN11 of the first multiplexer 201.

The second synchronous conversion unit 210 includes an inverter 211 for inverting and delaying the asynchronous data, and a second comparison signal COMP2 of the input terminal IN22 or the inverter according to a reference clock signal BCLK. A second multiplexer 113 for selecting the output data of 211 and a second multiplexer 213 that is reset according to the first reset signal RST1 and enabled according to the second reset signal RST2. The third latch 215 stores the output data and outputs the second data as the second comparison signal COMP2.

The synchronous data generator 220 compares the polarities of the first comparison signal COMP1 of the first synchronous conversion unit 200 and the second comparison signal COMP2 of the second synchronous converter 210. In this case, the first synchronization converter 200 selects output data of the first multiplexer 201 synchronized with the reference clock signal BCLK, and selects inverted synchronization data when the polarities are the same. The output data of the comparison / multiplexer 221 is reset as the synchronous data and reset according to the multiplexer 221 and the second reset signal RST2 and is reset according to the reference clock signal BCLK. The D-type flip-flop 223 is generated and input to the comparison / multiplexer 221.

The converter according to the present invention configured as described above has the reset terminal RST of the first to third latches 203, 207, and 215 with the first reset signal RST1 and the second reset signal RST2 at low potential and First to third when the first reset signal RST1 and the second reset signal RST2 become high potential after they are respectively applied to the reset terminals RST of the D-type flip-flop 223 and reset. The latches 203, 207, and 215 and the D-type flip-flop 223 are both reset, and a second of high potential is applied to the enable terminals EN of the first to third latches 203, 207, and 215. The reset signal RST2 is applied and all are enabled.

In this state, when the reference clock signal BCLK shown by the waveform (a) of FIG. 4 and the asynchronous data shown by the waveform (b) of FIG. 4 are input, the first multiplexer of the first synchronous conversion unit 200 ( 201 selects and outputs asynchronous data of the input terminal IN12 during the high potential period of the reference clock signal BCLK.

The data selected and output by the first multiplexer 201 is input to the input terminal D of the first latch 203 and stored therein, and is output to the output terminal Q as shown by the waveform of FIG. 4C. The output data of the first latch 203 is logically multiplied by the output data of the first multiplexer 201 at the AND gate 205. The output data of the AND gate 205 is input to the input terminal D of the second latch 207 and stored and output to the output terminal Q. The output data of the second latch 207 is the first multiplexer. Input terminal IN11 of 201 is input.

The first multiplexer 201 selects and outputs the output data of the second latch 207 during the low potential period of the reference clock signal BCLK, and the output data of the first multiplexer 201 receives the first latch ( The first multiplexer 201 of the first synchronous conversion unit 200 receives the asynchronous data as a reference clock, which is stored in the second latch 207 and the second latch 207, respectively, and is input to the input terminal IN11 of the first multiplexer 201. The data is output in synchronization with the signal BCLK, and the output data of the first latch 203 is output as the first comparison signal COMP1.

That is, the first synchronous conversion unit 200 selects asynchronous data and stores the asynchronous data in the second latch 207 during the high potential period of the reference clock signal BCLK. During the low potential period of BCLK, the first multiplexer 201 selects data stored in the second latch 207 so that asynchronous data is synchronized with the reference clock signal BCLK, and the synchronized data is stored in the first latch ( 203 stores and outputs the first comparison signal COMP1 as shown in the waveform of FIG.

The second synchronous conversion unit 210 is input to the input terminal IN22 of the second multiplexer 213 after the asynchronous data input is inverted and delayed through the inverter 211, so that the second multiplexer 213 is shown in FIG. As shown by the waveform of (d), the output data of the inverter 211 is selected and output to the output terminal Q during the high potential period of the reference clock signal BCLK. The output data of the second multiplexer 213 is input to the input terminal D of the third latch 215 and stored, and is output to the output terminal Q to the input terminal IN22 of the second multiplexer 213. Is entered.

During the low potential period of the reference clock signal BCLK, the second multiplexer 213 selects and outputs the output data of the third latch 215, as shown by the waveform (d) of FIG. 4, and the second multiplexer. The output data of 213 is stored and output in the third latch 215.

That is, the second synchronous conversion unit 210 inverts and delays the asynchronous data with the inverter 211 for a predetermined time, and then inverts and delays the asynchronous data during the high potential period of the reference clock signal BCLK. The inverter 213 selects and stores the data stored in the third latch 215 while the first multiplexer 213 selects data stored in the third latch 215 during the low potential period of the reference clock signal BCLK. The asynchronous data inverted and delayed at 211 is synchronized with the reference clock signal BCLK, and the synchronized data is stored in the third latch 215 to be compared with the second as shown by the waveform of FIG. Output the signal COMP2.

In this state, the comparison / multiplexer 221 of the synchronization data generator 220 generates the first comparison signal COMP1 and the second synchronization converter 210 generated by the first synchronization converter 200. When the polarity of the second comparison signal COMPP2 is received and the polarities of the first comparison signal COMPP1 and the second comparison signal COMP2 are different from each other, the comparison / multiplexer 221 is configured to perform the first comparison. The output data of the multiplexer 201 is selectively outputted, and the output data of the comparison / multiplexer 221 is synchronized with the flip-flop 223 through the flip-flop 223 according to the reference clock signal BCLK, as shown by the waveform of FIG. It is output as data.

The comparison / multiplexer 221 is output to the output terminal (/ Q) of the D-type flip-flop 223 when the polarity of the first comparison signal COMP1 and the second comparison signal COMP2 is the same. The inverted synchronization data is selected and outputted, and the outputted inverted synchronization data is output as the synchronization data through the flip-flop 223 according to the reference clock signal BCLK.

That is, when a time delay or processing time delay of asynchronous data occurs, the first synchronous conversion unit 200 according to the input reference clock signal BCLK as shown by the waveform of FIG. As shown by the waveform (c) of FIG. 5, the first comparison signal COMP1 is continuously output at high potential as shown by the waveform (c) of FIG. 5.

At this time, since the second synchronous conversion unit 210 inverts the asynchronous data and detects it after a predetermined time delay, the second synchronous conversion unit 210 accurately detects the change of the asynchronous data and thus, the second comparison signal COMP2 as shown by the waveform of FIG. ) Will be printed.

As described above, when the first comparison signal COMP1 is continuously output at high potential and the second comparison signal COMP2 is inverted in polarity according to the change of the asynchronous data, the comparison / multiplexer 221 is connected to the first comparison signal COMP1 and the first comparison signal COMP1. If the polarity of the second comparison signal COMP2 is different from each other, the data output from the first synchronous conversion unit 200 is selected and output as synchronous data through the flip-flop 223. Asynchronous data is lost because the inverted synchronous data output from the output terminal (/ Q) of the flip-flop 223 is selected and output as the synchronous data through the flip-flop 223 as shown by the waveform (e) of FIG. 5. Without this, it is converted into synchronous data and outputted.

That is, in the present invention, the first synchronous conversion unit 200 generates the first comparison signal COMP1 in synchronization with the reference clock signal BCLK without delaying the asynchronous data, and the second synchronous conversion unit 210 generates the first synchronous conversion unit 210. Since the second comparison signal COMPP2 is generated in synchronization with the reference clock signal BCLK after the inverting and delaying of the asynchronous data, the first comparison compensates the failure of detecting the asynchronous data in the high potential period of the reference clock signal BCLK. At least one of the synchronous conversion unit 200 and the second synchronous conversion unit 210 always detects asynchronous data accurately in the high potential period of the reference clock signal BCLK. By using this, the synchronous data output unit 220 compares the first comparison signal COMP1 and the second comparison signal COMP2 and when the polarities are different, the first synchronization converter 200 and the second synchronization converter. When the 210 detects asynchronous data correctly, the first synchronous conversion unit 200 selects and outputs the data synchronized with the reference clock signal BCLK as synchronous data, and when the polarity is the same, the first synchronous conversion unit Any one of the 200 and the second synchronous conversion unit 210 does not correctly detect the asynchronous data, and selects and outputs the inverted synchronous data to prevent loss of the asynchronous data, and outputs it in synchronization with the clock signal.

As described in detail above, the present invention allows the first synchronous conversion unit and the second synchronous conversion unit to generate asynchronous data in synchronization with the reference clock signal, and synchronizes the asynchronous data with the reference clock signal according to the generated data. By converting into the synchronous data, the asynchronous data can be output in synchronization with the reference clock signal without loss.

Claims (4)

A first synchronous converter for synchronizing asynchronous data with a reference clock signal, storing the synchronized data and generating the first comparison signal; A second synchronous converter for synchronizing the asynchronous data with the reference clock signal after inverting and delaying a set time, storing the synchronized data, and generating the second comparison signal; And When the polarities of the first comparison signal and the second comparison signal are compared and different from each other, the first synchronization converter generates data synchronized with the reference clock signal as synchronization data, and when the polarities are the same, the polarity of the synchronization data is changed. And a synchronization data generator for generating inverted data as synchronization data. The apparatus of claim 1, wherein the first synchronous conversion unit; A first multiplexer for selecting a feedback input signal or asynchronous data according to a reference clock signal; A first latch that is reset according to a first reset signal and is enabled according to a second reset signal, and stores selection data of the first multiplexer and outputs the selected data as a first comparison signal; An AND gate that logically multiplies the output data of the first multiplexer and the first latch; And And a second latch that is reset according to a first reset signal and is enabled according to a second reset signal, and stores output data of the AND gate and inputs it as a feedback input signal to the first multiplexer. Synchronous Data Inverter. The method of claim 1, wherein the second synchronous conversion unit; An inverter for inverting and delaying the asynchronous data and a second multiplexer for selecting a second comparison signal or output data of the inverter according to a reference clock signal; And And a third latch configured to be reset according to the first reset signal and enabled according to the second reset signal, and to store the output data of the second multiplexer and output the second data as a second comparison signal. . The apparatus of claim 1, wherein the synchronization data generator comprises: a synchronization data generator; A comparison / multiplexer for comparing the first comparison signal and the second comparison signal to select data synchronized with the reference clock signal when the polarity is different and selecting inverted synchronization data when the polarity is the same; ; And D, which is reset according to the second reset signal and outputs the output data of the comparison / multiplexer as synchronous data according to the reference clock signal, and generates inverted synchronous data inverting the synchronous data and inputs the same to the comparison / multiplexer. A synchronous data converter comprising a flip flip flop.

Images