JPH11312953A - Data delay device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data delay device which can provide data delay by a simple structure. SOLUTION: This device is equipped with a memory 21 for storing input data Di, an address counter 22 for generating a bit signal S0 (the first bit) of a T cycle, a most significant bit signal S1 (the second bit) of a 2T cycle and a most significant bit signal S3 (the third bit) of a 4T cycle by frequency dividing a clock signal Ck, and an exclusive OR circuit 26 which takes the exclusive OR of the most significant bit signal S2 inputted to one input terminal and the clock signal Ck inputted to another input terminal and outputs to the memory 21 as a bit signal S2 ' (the third bit). The memory 21 takes a leading address as a reference address in writing the input data Di, while it is write and read controlled in reading the input data Di with an intermediate address as the reference address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data delay device used for delaying data.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration of a conventional data delay device. The data delay device shown in this figure is, for example, a device for implementing a voice delay loopback function in a line connection tester of a mobile phone. Reference numeral 1 shown in FIG. 4 is a signal input terminal to which a voice input signal Si is input. Reference numeral 2 denotes an LPF (low-pass filter) that passes a low-frequency component of the audio input signal Si input via the signal input terminal 1. Reference numeral 3 denotes an S / H (sample and hold) circuit, which samples the audio input signal Si filtered by the LPF 2 at predetermined time intervals, and holds it. A / D (analog / digital) 4 converts an output signal (audio input signal Si) of the S / H circuit 3 into input data Di which is digital data.
It is a converter.

[0003] Reference numeral 6 denotes a delay unit for delaying input data Di input through the data input terminal 5 by a predetermined time, and includes shift registers 71 to 73. That is, in the delay section 6, the input data Di is shifted in the order of the shift register 71 → the shift register 72 → the shift register 73, so that the input data Di is delayed for a certain time. A data output terminal 8 outputs the input data Di delayed by the delay unit 6 as output data Do. Reference numeral 9 denotes a D / A (digital / analog) for converting output data Do input via the data output terminal 8 into an analog signal.
It is a converter. Reference numeral 10 denotes an LPF that passes a low-frequency component of the output signal of the D / A converter 9 and outputs the low-frequency component to the signal output terminal 11 as an audio output signal So.

In the above configuration, when the audio input signal Si is input to the signal input terminal 1, the audio input signal Si becomes L
After the high frequency component is cut by the PF2, the S / H circuit 3
And the A / D converter 4 converts the data into input data Di. Then, the input data Di is input to the shift register 71 via the data input terminal 5, and the shift register 71
After shifting in the order of shift register 72 → shift register 73, the output data D is output via the data output terminal 8.
It is input to the D / A converter 9 as o. As a result, the output data Do is delayed by a certain time with respect to the input data Di.

After the output data Do is converted into an analog signal by the D / A converter 9, the high-frequency component is cut off by the LPF 10 and is input to the signal output terminal 11 as an audio output signal So.

[0006]

By the way, in the conventional data delay device, the input data Di (the audio input signal Si) is delayed by forming the shift registers 71 to 73 in a multi-stage configuration. However, there has been a problem that the circuit configuration is complicated and large. The present invention has been made under such a background, and an object of the present invention is to provide a data delay device that can realize a data delay with a simple configuration.

[0007]

According to a first aspect of the present invention, a storage means for storing data in a storage area specified by an address, and writing and reading of the data in the storage means are alternately permitted. Permission means, when writing is permitted by the permission means, write control means for sequentially writing the data in a storage area designated by a head address of the storage means, and when reading is permitted by the permission means, A read control unit for sequentially reading the data from a storage area specified by an intermediate address between the start address and the end address in the storage unit; a write address in the write control unit; and a read address in the read control unit. Address control means for incrementing And wherein the door. Claim 2
According to the invention described in the above, storage means for storing data in a predetermined storage area, based on a clock signal, the writing of the data in the storage means, permission means for alternately permitting reading, and the clock signal An exclusive OR of the clock signal and the signal of the most significant bit in the address counter is calculated based on the address counter that sets the n-bit address in the storage unit, and the output signal is stored in the storage unit. An exclusive-OR circuit for outputting to the storage means as the most significant bit in the address of the means, wherein the storage means, when the writing is permitted by the permission means, stores the data in a storage area designated by a head address. While data is sequentially written, when reading is permitted by the permission means, the start address and the last address are read. Wherein the sequentially reading the data from the storage area designated by the intermediate address between addresses.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a data delay device according to an embodiment of the present invention. In this figure, parts corresponding to the respective parts in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 1, a delay unit 20 is provided instead of the delay unit 6 shown in FIG. The delay unit 20 shown in FIG. 1 delays the input data Di by a fixed time, and
It comprises an address counter 22 and an address dividing circuit 24.

In the delay unit 20, a memory 21 stores input data Di in a storage area specified by an address represented by n bits. Reference numeral 22 denotes an n-bit address counter, which counts up the address by using a rising (or falling) edge of a clock signal Ck (see FIG. 3A) input via a clock input terminal 23 as a trigger. The address counter 22 and the memory 21 are connected via an address bus (not shown) composed of n address lines, and a signal of the count value of the address counter 22 is sent to the memory 21 via the address bus. Is entered.

Reference numeral 24 denotes an address 2 for obtaining an intermediate address between the start address and the end address of the memory 21 based on the count value of the address counter 22.
It is a division circuit. In the memory 21, writing and reading of the input data Di are performed alternately in synchronization with the clock signal Ck. In the memory 21, the input data Di is sequentially written from the top address in synchronization with the count-up of the address counter 22, while
The reading of the input data Di is performed sequentially from the intermediate address.

Here, the writing of the input data Di is performed sequentially from the head address, and when the writing to the last address is performed, the writing is performed again from the head address. On the other hand, the reading of the input data Di is performed in order from the intermediate address. When the reading is performed up to the address before the intermediate address via the last address and the head address, the reading is performed again from the intermediate address. That is, in writing the input data Di,
The head address is used as the reference address, while the intermediate address is used as the reference address in reading the input data Di. That is, the input data Di written to the head address of the memory 21 is delayed by a time (hereinafter, referred to as a delay time) from when the input data Di is written to the head address to when the input data Di is written to the intermediate address. Is read.

FIG. 2 shows a specific configuration of the data delay device shown in FIG. FIG. 2 shows a configuration example of the data delay device when the address of the memory 21 is represented by 3 bits. Address counter 2 shown in FIG.
2 and the memory 21 are connected via an address bus consisting of address lines A0 to A2.
Corresponds to the first bit (least significant bit), the address line A2 corresponds to the second bit, and the address line A2 corresponds to the third bit (most significant bit). An exclusive OR circuit (EX OR circuit) is connected to the address line A2.
26 is inserted.

The address counter 22 divides the frequency of the clock signal Ck (see FIG. 3 (a)) having a period of T to thereby generate a bit signal S0 (first bit) having a period of T shown in FIG. 3 (b). At the same time, a bit signal S1 (second bit) having a period of 2T shown in FIG. 3C is generated. In addition, the address counter 22 similarly operates as shown in FIG.
Generates the most significant bit signal S2 (third bit) whose period is 4T. Further, the address counter 22 converts the above-mentioned bit signal S0 and bit signal S1 into an address line A.
0 to the memory 21 via the address line A1, and outputs the most significant bit signal S2 to the exclusive OR circuit 26.
Output to one of the input terminals.

The exclusive OR circuit 26 has a most significant bit signal S2 (see FIG. 3D) input to one input terminal and a clock signal Ck input to the other input terminal.
An exclusive OR is calculated with this (see FIG. 3A), and this is output to the memory 21 via the address line A2 as a bit signal S2 '(third bit) shown in FIG. 3E. That is, the memory 21 receives an address signal Sa (see FIG. 3 (h)) represented by three bits, for example, a bit signal S0, a bit signal S1, and a bit signal S2 '. Note that “0” to “7” shown in FIG.
It is represented by a decimal number.

The memory 21 has a read signal input terminal 21R and a write signal input terminal 21W. The write signal input terminal 21W receives the clock signal Ck via the clock input terminal 23 for the write signal SW.
(See FIG. 3F). The memory 21
When the write signal SW is "low", the input data Di
Writing is allowed.

Reference numeral 25 denotes an inverter interposed between the clock input terminal 23 and the read signal input terminal 21R, which inverts the clock signal Ck and uses it as a read signal SR (see FIG. 3 (g)). It outputs to the read signal input terminal 21R. The memory 21 stores the read signal SR
Is low, reading of the input data Di is permitted.

In the above configuration, when the clock signal Ck falls at the time t1 shown in FIG. 3A, as shown in FIGS. 3B, 3C and 3E, the bit signal S
0, the bit signal S1 and the bit signal S2 ′ are “0”,
"0" and "0". That is, in this case, FIG.
An address signal Sa shown in (h) represents an address 0 (decimal number). On the other hand, at time t1, the write signal SW shown in FIG. 3 (f) is set to "low", so that the address 0 (000: binary number) in the memory 21 shown in FIG.
Is allowed to be written. As a result, as shown in FIG. 3 (i), the input data Di (A) is written to the storage area specified by the address 0 in the memory 21 between the time t1 and the time t2.

Then, when the clock signal Ck rises at time t2 shown in FIG. 3A, FIGS. 3B and 3C
As shown in FIG. 3E, the bit signal S0, the bit signal S1, and the bit signal S2 ′ are “0”, “0”, and “1”. That is, in this case, the address signal Sa shown in FIG. 3H represents the address 4 (decimal number). On the other hand, at time t2, since the read signal SR shown in FIG. 3F is set to "low", reading of the input data Di of the address 4 (100: binary number) in the memory 21 shown in FIG. 2 is permitted. In this case, assuming that no input data Di is stored in the storage area at the address 4, no data is read from the storage area (see FIG. 3 (j)).

Then, when the clock signal Ck falls at the time t3 shown in FIG. 3A, FIG. 3B and FIG.
As shown in FIG. 3E, the bit signal S0, the bit signal S1, and the bit signal S2 'are "1", "0", and "0". That is, in this case, the address signal Sa shown in FIG. 3H represents the address 1 (decimal number). On the other hand, at time t3, the write signal SW shown in FIG. 3 (f) is set to "low", so that the writing of the input data Di of the address 1 (001: binary) in the memory 21 shown in FIG. 2 is permitted. . As a result, FIG.
As shown in (i), between time t3 and time t4, the input data Di (a) is written to the storage area of the memory 21 specified by address 1.

Thereafter, the above-described read operation and write operation are repeated every half cycle of the clock signal Ck.
Thus, between time t5 and time t10, the input data Di is stored in the addresses 2, 3, and 4 in the memory 21.
(C), input data Di (d) and input data Di
(E) are sequentially written at half cycle intervals. Since the input data Di has not been written to the addresses 5, 6 and 7 in the memory 21 between the time t4 and the R time t10, the read operation is not performed.

Then, when the clock signal Ck rises at time t10 shown in FIG. 3A, FIG. 3B and FIG.
As shown in FIG. 3E, the bit signal S0, the bit signal S1, and the bit signal S2 'are "0", "0", and "0". That is, in this case, the address signal Sa shown in FIG. 3H represents the address 0 (decimal number). On the other hand, at time t10, since the read signal SR shown in FIG. 3 (f) is set to "low", the read permission of the input data Di (a) of the address 0 (000: binary number) in the memory 21 shown in FIG. Is done.

Thus, from the address 0 of the memory 21, the input data Di is output from the output data Do shown in FIG.
(A) and read out from the data output terminal 8 shown in FIG.
Is input to the D / A converter 9 shown in FIG. As a result, the output data Do (A) is output to the D / A converter 9
After that, the high-frequency component is cut by the LPF 10 and output from the signal output terminal 11 as the audio output signal So.

That is, the input data D shown in FIG.
A delay corresponding to the delay time Td shown in FIG. 3 (j) occurs between i (a) and the output data Do (a) shown in FIG. 3 (j). That is, the audio input signal Si shown in FIG. 1 is delayed by the delay time Td by the delay unit 20 (see FIG. 2). Here, the delay time Td is expressed by the formula (2 ⁿ × 1 / clock frequency) / 2 according to the number of bits n of the address and the frequency (clock frequency) of the clock signal Ck.

As described above, according to the data delay device of the above-described embodiment, the input data Di (voice input) is controlled by the address control of the memory 21 instead of the conventional shift registers 71 to 73 (see FIG. 4). Since the configuration is such that the signal Si) is delayed, a data delay can be realized with a simple configuration as compared with a conventional data delay device.

[0025]

As described above, according to the present invention,
The data is sequentially written to a storage area specified by a head address of the storage means by the write control means,
On the other hand, the data is sequentially read from the storage area specified by the intermediate address between the start address and the end address in the storage means by the read control means, so that the data is delayed for a predetermined time. Therefore, according to the present invention, the conventional shift register 7
Instead of 1 to 73 (see FIG. 4), the data is delayed by the address control of the storage means, so that the data delay can be realized with a simpler configuration than the conventional data delay device. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a data delay device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a data delay device according to the same embodiment.

FIG. 3 is a diagram showing signal and data waveforms of each unit in the data delay device shown in FIG. 2;

FIG. 4 is a diagram showing a configuration of a conventional data delay device.

[Explanation of symbols]

 Reference Signs List 20 delay unit 21 memory 22 address counter 24 address division circuit 25 inverter 26 exclusive OR circuit

Claims (2)

[Claims] 1. A storage unit for storing data in a storage area specified by an address, a permission unit for alternately permitting the writing and reading of the data in the storage unit, and a write operation permitted by the permission unit. Writing control means for sequentially writing the data in a storage area specified by a start address of the storage means; and when reading is permitted by the permission means, a time interval between the start address and the end address in the storage means. Read control means for sequentially reading the data from the storage area specified by the intermediate address; write address in the write control means and read address in the read control means being 1
A data delay device comprising: an address control means for incrementing the data. 2. A storage means for storing data in a storage area specified by an address; a permission means for alternately permitting writing and reading of the data in the storage means based on a clock signal; Based on the storage means
An address counter for setting the address consisting of bits; an exclusive OR of the clock signal and a signal of the most significant bit in the address counter; and storing the output signal as the most significant bit in the address of the storage means. An exclusive-OR circuit that outputs the data to a storage area specified by a start address when writing is permitted by the permission means. A data delay device, wherein when reading is permitted, the data is sequentially read from a storage area specified by an intermediate address between the start address and the end address.