JPH05120219A - Data transmitting circuit - Google Patents

Abstract

PURPOSE:To shorten the time required to transmit sent data, constituted in byte units, with frame constitution in bit units by the transmitting circuit for serial data of frame constitution. CONSTITUTION:This data transmitting circuit consists of a memory 1 where data in byte units are stored and read out in byte units with a readout signal, holding circuits 2 and 3 which holds the data of the memory 1, a selecting circuit 4 which selects the data of the holding circuit 2 in bit units with a select signal, a counter 5 which inputs frame pulses and a clock and counts the number of bits of frames, and a ROM 6 which outputs the readout signal, holding signals 1 and 2, and select signal as data. Consequently, the frame constitution which is free from a waste of data is provided and a conventional editing process is not required, so the processing time of transmission can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission circuit, and more particularly to a transmission circuit for framed serial data.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 3, this type of data transmission circuit stores data edited in bit units according to a frame type, and stores the stored transmission data in bytes. A memory 31 that is read in units, a holding circuit 32 that holds the data from the memory 31 with a holding signal that is generated at a fixed timing, a selection circuit 33 that selects the held data in bit units, and a frame pulse. It is composed of a counter 34 which counts the number of bits of a frame from a clock, and a decoder 35 which inputs the output of the counter 34 and outputs the read signal, the hold signal and the selection signal.

[0003]

The above-described conventional data transmission circuit requires an editing process for changing transmission data in byte units into bit units, as shown in FIG. There is a problem that it takes time to repeat the unit shift and perform a logical operation.

Further, as shown in FIG. 5, if the frame structure is considered so that the knitting process is not necessary, a wasteful area is formed in the data, and the frame type must be increased or the frame length must be increased. Therefore, there is a problem that it takes time to transmit data.

It is an object of the present invention to provide a data transmission circuit for transmitting serial data having a frame structure, which shortens a time for transmitting byte-unit transmission data in a bit-unit frame structure.

[0006]

A data transmission circuit according to the present invention receives a frame pulse and a clock indicating the beginning of a frame, and is configured into a frame having an arbitrary number of bits. In a circuit for transmitting serial data whose delimiter changes, a memory that stores data to be transmitted and can read data in byte units by a read signal, and a holding circuit that holds the data read from the memory by a holding signal 1 Two
A holding circuit 3 for holding the data read from the memory with a holding signal 2; a selection circuit for selecting the output of the holding circuit 2 in bit units by a selection signal; A counter that counts the number of bits and a read-only memory (ROM) that inputs the output of the holding circuit 3 and the output of the counter as addresses and outputs the read signals, the hold signals 1 and 2, and the selection signal as data. The data transmission circuit is configured.

[0007]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 shows a format example of transmission data.

In FIG. 1, a memory 1 stores transmission data in byte units. FIG. 2 shows an example of the format of transmission data stored in the memory 1. Byte-unit data is read from the memory 1 by a read signal. The holding circuit 3 holds the frame type information by the holding signal 2 among the data read from the memory 1. The holding circuit 2 holds the data read from the memory 1 with a holding signal 1.
The selection circuit 4 selects the output of the holding circuit 2 in bit units by the selection signal and outputs a frame signal of serial data. FIG. 2 shows a format example of a serial frame signal.

The counter 5 counts the number of bits of the frame signal with the frame signal (FP) and the clock signal (CLK).

A read-only memory (ROM) 6 inputs the number of bits of the frame output from the counter 5 and the frame type output from the holding circuit 3 as an address, and depending on the address, a read signal and a hold signal 1 2 and the selection signal are output as data.

[0012]

As described above, according to the present invention, when the transmission data is read from the memory and assembled into a serial transmission frame, the data is connected bit by bit according to the frame type. Therefore, with the minimum frame transmission / reception time based on a frame configuration with no waste of data, it is not necessary to edit the transmission data for each frame type before storing it in the memory as in the conventional case, and the effect of shortening the transmission processing time can be obtained. is there.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Fig. 2] Example of format of transmission data

FIG. 3 is a block diagram of a conventional example.

FIG. 4 is a format example of transmission data of a conventional example.

FIG. 5 is a format example of transmission data of a conventional example.

[Explanation of symbols]

1 memory 2, 3 holding circuit 4 selection circuit 5 counter 6 read only memory (ROM) DATA transmission serial data CLK clock FP frame pulse 21 format example of data to be transmitted 22 data stored in transmission memory (memory 1 in FIG. 1) 23 Format example of transmission frame 31 Memory 32 Holding circuit 33 Selection circuit 34 Counter 35 Decoder 41 Format example of data to be transmitted 42 Format example of data stored in transmission memory (memory 31 in FIG. 3) 43 Transmission frame Format example

Claims (1)

[Claims] 1. A circuit for transmitting serial data, which receives a frame pulse and a clock indicating the beginning of a frame, is configured into a frame having an arbitrary number of bits, and has a data delimiter that changes bit by bit depending on the frame type of the frame beginning. , A memory that stores data to be transmitted and can read the data in byte units by a read signal, a holding circuit 2 that holds the data read from the memory with a holding signal 1, and a holding signal that holds the data read from the memory A holding circuit 3 which holds the holding circuit 2; a selection circuit which selects the output of the holding circuit 2 in bit units by a selection signal; a counter which inputs the frame pulse and clock and counts the number of bits of the frame; 3 and the output of the counter are input as addresses, and the read signal and the hold signals 1 and 2 are input. And a read-only memory (RO that outputs the selection signal as data
M) and a data transmission circuit.