JPH0646023A - Frame phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To shorten the delay time of a frame phase synchronizing circuit in the condition that bits are synchronized between input and output with respect to the transmission frame having the numerical value (pointer), which indicates the head position of a payload, in the overhead part. CONSTITUTION:A reception pointer value 12 is obtained by a pointer interpreting part 4, and the phase difference (offset pointer value 14) in the payload head position between input and output frames is obtained by an offset detecting part 6, and a substitution pointer value 15 is obtained from the sum of the reception pointer value 12 and the offset pointer value 14 by an addition processing part 7, and thereby, only the phase difference of overhead between the input and the output is absorbed through a variable shift register 8 to deliver data with a minimum delay.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The frame phase synchronizing circuit of the present invention is a frame phase synchronizing circuit for performing processing such as multiple conversion and line setting in a digital synchronizing terminal device, etc., by matching the phase of each input transmission circuit with the phase in the device. It relates to a synchronous circuit.

[0002]

2. Description of the Related Art Conventionally, as a frame phase synchronizing circuit used in a network synchronizing system, an elastic store (hereinafter referred to as E
The frame memory system by S) can be mentioned.

FIG. 3 shows an example of this conventional circuit. This circuit uses the input data 1 that has been input from the pointer interpretation unit 23.
Immediately before the head position of the payload read in step 3, a head flag 11 is inserted on the writing side of ES20 as information indicating that the payload is the head, and is used as a calculation standard for the pointer value added by the frame generation unit 9. Further, a write address counter (WAC) 21 that receives an input frame synchronization pulse 2 that outputs a write address and a read address to the ES 20, and a read address counter (RAC) 2 that receives an in-device frame synchronization pulse 10 as an input.
EC20 by controlling the frame phase of 2 independently
In (1), the phase of the input side frame data 1 on the receiving side is adjusted to the phase of the inner frame of the office, and then a new pointer is added in the frame generation section 9 to perform phase synchronization and output as output data 17. At this time, the delay amount of the frame memory changes according to the phase variation amount of the input data.

[0004]

Since the above-mentioned conventional frame synchronization circuit takes into account the delay variation of the transmission path, the pointer of the input signal and the pointer of the output signal do not change at the same time. Therefore, for example, a buffer memory of about 10 bytes is required. However, when the input signal pointer and the output signal pointer change at the same time, such as when the clocks of the input signal and the output signal are the same, the buffer memory is not always necessary, and the delay caused by the memory becomes a problem. In addition, there is a problem that it is disadvantageous to downsize the device and reduce power consumption.

[0005]

The frame synchronization circuit of the present invention inputs input frame data and writes a signal of a portion which becomes a payload of the input frame data by an input frame synchronization pulse corresponding to the input frame data and outputs the frame. A variable length shift register for reading the same in synchronization and outputting payload data, a pointer interpreting unit for inputting the input frame data and reading a pointer value indicating a head position of a signal which is a payload of the input frame data, and the input frame A zero pointer detector that inputs data and outputs a zero pointer pulse when the pointer value becomes zero and the zero pointer pulse is input, and this zero pointer pulse is zero on the output side frame due to the output frame synchronization pulse. The offset pointer value indicating the position An offset detection unit for inputting, the addition value processing unit for inputting the pointer value and the offset pointer value and adding both to output a replacement point value, and inputting the payload data and the replacement point value. And a frame generation unit for outputting output frame data to which an overhead including both of them is added.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention.

The input frame data 1 includes a pointer interpreter 4, a zero pointer detector 5, and a variable length soft register 8.
Is distributed to. The writing of the input frame data 1 to the variable length shift register 8 is performed by the write clock generator (WCG).
Only the payload is done by 18. The data read from the variable length shift register 8 is performed by the read clock generator (RC
G) 19 is performed only on the payload portion of the in-apparatus frame and is output as payload data 16. The zero pointer detector 5 outputs a zero pointer pulse 13 when the pointer becomes zero in the received frame. This pulse is input to the offset detection unit 6, and the offset pointer value 14 indicating the position of the pulse based on the output frame phase is calculated. Offset pointer value 14 and reception pointer value 1 read by the pointer interpreter 4.
Reference numeral 2 is connected to two input terminals of the addition processing unit 7, and after taking the sum of the two, an operation modulo the number of bits of the payload in one frame is performed to obtain a replacement pointer value 15.

The frame generator 9 adds an overhead including a reassignment pointer value 15 to the payload data to generate output frame data 17. There are as many pointer processing modules as these circuits corresponding to the number of received signals.

As for the clock and the frame synchronization pulse for controlling these pointer processing modules, the internal clock is used for the clock, and the pointer interpretation unit 4, the zero pointer detection unit 5 and the writing are used for the frame synchronization pulse. In the clock generator 18, the input frame synchronization pulse 2 corresponding to each input signal is used,
The offset detection unit 6, the addition processing unit 7, the read clock generation unit 19, and the frame generation unit 9 use the in-device frame synchronization pulse 10 generated from the in-device clock.

The operation of pointer replacement according to the embodiment described above is shown in FIG. Here, the number of payloads in one frame is 16 bytes, overhead (the part shown by H in the figure)
Is represented as 2 bytes. The payload signal of the reception frame 1 constitutes an output frame with zero delay time. However,
In the area from the point where the overhead is inserted on the output frame side to the overhead section on the next reception frame side, a delay of the length of the overhead (here, 1 byte) is given through the variable length shift register.

The zero pointer position a of the received frame is represented by a pointer offset value b based on the output frame phase. The value of b is in the case of received frame 1: b = 3, in the case of received frame 2: b = 8 (In this case, since the position of a is an overhead part, give the pointer value of the payload signal located next to the overhead signal. It will be). The following calculation is performed by using the pointer offset value b and the reception pointer value p read from the overhead of the reception frame to obtain the replacement pointer value P.

P = [b + p] _N (where [] _N represents an operation modulo N) In FIG. 2, the following values are obtained. Reassignment pointer value of received frame 1: P = [b + p] _N =
[6 + 3] ₁₆ = 9 Replacement pointer value of received frame 2: P = [b + b] _N =
[8 + 8] ₁₆ = 0 The replacement pointer value P thus obtained is added to the overhead of the next output frame. As can be seen from the figure, the amount of delay of the payload due to the frame phase synchronization is one worst byte (corresponding to the overhead width) in any received frame phase.

[0013]

As described above, the present invention obtains the offset value of the received frame with respect to the in-apparatus frame from the zero pointer position of the received frame and adds this offset value to the received pointer value to determine the phase of the received frame. Since the ES for matching the phase of the frame in the device is replaced with the variable length shift register to reduce the memory capacity, there are effects of reduction of transmission delay, downsizing of the device, and low power consumption. Further, by using the value indicating the pointer zero position of the received frame as seen on the in-apparatus frame as the offset value, the offset value can be obtained without depending on the format of the transmission path frame (especially the number and length of overhead). There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a frame configuration diagram in FIG.

FIG. 3 is a block diagram of a conventional example.

[Explanation of symbols]

 1 Input Frame Data 2 Input Frame Synchronization Pulse 4 Pointer Interpretation Section 5 Zero Pointer Detection Section 6 Offset Detection Section 7 Addition Processing Section 8 Variable Length Shift Register 9 Frame Generation Section 10 Device Frame Synchronization Pulse 12 Receive Pointer Value 13 Zero Pointer Pulse 14 Offset pointer 15 Replacement pointer 16 Payload data 17 Output frame data 18 Write clock generation unit (WCG) 19 Read clock generation unit (RCG) a Zero pointer position of received frame b Pointer offset value p Reception pointer value P Replacement pointer value

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hiromi Ueda 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Inside Nippon Telegraph and Telephone Corporation

Claims (2)

[Claims] 1. A variable length for inputting input frame data, writing a signal of a portion which becomes a payload of the input frame data by an input frame synchronization pulse corresponding to the input frame data, and reading the signal by output frame synchronization and outputting payload data. A shift register, a pointer interpreting unit for inputting the input frame data and reading a pointer value indicating a head position of a signal which is a payload of the input frame data, and inputting the input frame data, the pointer value becomes zero. Offset detection that outputs the zero pointer pulse that outputs a zero pointer pulse indicating the position where the zero pointer pulse is zero on the output side frame by the input zero frame pulse and the output frame synchronization pulse. Part and the pointer value An addition processing unit that inputs the offset pointer value and performs addition processing on both of them and outputs a replacement point value, and output frame data to which the payload data and the replacement point value are input and an overhead including the both is added And a frame generator for outputting the frame phase synchronizing circuit. 2. The offset detection unit, instead of indicating the position where the offset pointer value becomes zero on the output side frame, is N on the output side frame (N is an integer of 1 or more and less than the number of bits of the payload). 2. The frame synchronization circuit according to claim 1, wherein the addition processing unit subtracts the N by setting a value indicating a position where