JP3213389B2 - Time division multiplex communication equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital communication and, more particularly, to a time division multiplex communication apparatus for multiplexing signals by time division for communication.

[0002]

2. Description of the Related Art In recent years, with the development of communication technology, for example,
In fields such as cordless telephones, so-called time division multiplexing (TDMA) is about to be performed. In this TDMA, a time axis is divided into a plurality of time slots, and a user is assigned to each time slot to multiplex communication. FIG. 9 shows an example of a cordless telephone to which such a TDMA system is applied. As shown in this figure, an audio signal 10 from a receiver (not shown)
8 is input to the encoding / decoding unit 101, where the A / D
The audio is sampled at a predetermined frequency after being converted,
It is converted to a digital signal sequence. As this sampling frequency, 8 kHz is generally used. Therefore,
The sampling period is 1 as shown in FIG.
25 μs. For example, as the number of sampling bits,
Assuming that 4 bits are used, the encoding / decoding unit 101
As shown in FIG. 10B, 4-bit audio data D1 to D4 are serially output every 125 μs.

The TDMA control unit 102 receives one audio sample data every 125 μs, that is, the above 4-bit audio data, and stores it in a buffer memory (not shown). When such audio samples are received for 40 samples, predetermined control data (header signal) is added to the audio data of 40 samples to form audio data for one slot under the control of the CPU 104.
This is sent to the modem 103.

[0004] The modulation and demodulation section 103 performs a predetermined modulation and sends it to the high frequency processing section 105. The high-frequency processing unit performs high-frequency processing based on the transmission frequency from a PLL circuit (not shown), and performs transmission from the antenna 106.

[0005]

As described above, in the conventional time-division multiplex communication apparatus described above, the TDMA control unit collectively sends out audio data for 40 samples per slot. Since the multiplexing unit 101 outputs audio data once every 125 μs, the TDMA control unit
In order to compose audio data for a slot, data must be received 40 times and arranged in a buffer memory. Since the cycle of 125 μs is an operation that is asynchronous with the operation of the TDMA control unit, the reception of 40 times is processed by an interrupt. Due to this interrupt, the TDMA control unit must interrupt the operation of generating a time slot each time, and it is necessary to perform the process of specifying the address of the buffer memory each time reception is performed. It takes time and the processing becomes complicated. For this reason, the TDMA control unit, which inherently performs a considerably complicated process only by the control for configuring the time slot, adds the above-described process of receiving and arranging the received data in the memory. It becomes more complicated and large-scale. For example, if the circuit is P
Even in the case of the configuration using the LA, there is a problem that this must be complicated and large-scale.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and a time division multiplex communication apparatus capable of simplifying the operation by greatly reducing the circuit configuration or program processing of a TDMA control unit. The purpose is to obtain.

[0007]

According to a first aspect of the present invention, there is provided a time division multiplex communication apparatus for encoding a voice signal digitally and a predetermined time width based on output data of the encoding section. A time-division multiplexing unit that generates transmission audio data for the time slots of (i), wherein the encoding unit (i) samples the analog audio signal at a fixed period and outputs a digital audio signal having a predetermined bit width. An encoding circuit that outputs data, (ii) a buffer memory that has a transmission audio data storage capacity corresponding to at least one time slot, and sequentially stores digital audio data that is output from the encoding circuit at a fixed cycle, (iii) a write address counter that counts a write clock indicating a write address of digital audio data from the encoding circuit to the buffer memory;
(iv) a read address counter that counts a read clock indicating a read address of digital audio data from the buffer memory to the time division multiplexing unit; and (v) a difference between the count value of the write address counter and the count value of the read address counter. A difference detection circuit to be detected, and (vi) when the difference detected by the difference detection circuit is equal to or larger than the data amount corresponding to one time slot,
Data read request means for requesting reading of digital audio data, wherein the time division multiplexing unit continuously reads digital audio data for one time slot from a buffer memory in response to the read request. Is what you do.

According to a second aspect of the present invention, there is provided a time division multiplex communication apparatus according to the first aspect.
The reading rate of digital audio data from the buffer memory by the time division multiplexing unit is made equal to the transmission rate.

According to a third aspect of the present invention, there is provided a time division multiplex communication apparatus, comprising: a time division multiplexing unit for receiving digital audio data for a time slot of a predetermined time width; and a decoding unit for decoding digital audio data. An apparatus having
The decoding unit comprises: (i) a buffer memory for storing the digital audio data received by the time division multiplexing unit for at least one time slot; and (ii) a predetermined bit period of the digital audio data written in the buffer memory. (Iii) a read address counter that counts a read clock indicating a read address of digital audio data from the buffer memory to the decoding circuit, and (iv) A write address counter that counts a write clock indicating a write address of digital audio data from the division multiplexing unit to the buffer memory; and (v) a memory that calculates a difference between the count value of the read address counter and the count value of the write address counter. (Vi) a difference detection circuit for detecting the empty region of Data write request means for requesting the time division multiplexing unit to write digital audio data when the empty area of the memory becomes equal to or more than the data amount corresponding to one time slot, The multiplexing unit is characterized in that the received digital audio data for one time slot is continuously written into the buffer memory in response to the write request.

According to a fourth aspect of the present invention, there is provided a time division multiplex communication apparatus according to the third aspect.
The writing rate of the digital audio data to the buffer memory by the time division multiplexing unit is made equal to the receiving rate.

[0011]

In the time division multiplex communication apparatus according to the first aspect of the present invention, sampled audio data of a predetermined number of bits is sequentially written into a buffer memory in an encoding unit, and a difference between a write address and a read address is one time. When the number of slots exceeds the number of slots, audio data for one time slot is continuously read and sent to the time division multiplexing unit.

In the time division multiplex communication apparatus according to the second aspect of the present invention, the continuous reading of the audio data for one time slot according to the first aspect is performed at the same rate as the transmission rate.

[0013] In the time division multiplex communication apparatus according to the third aspect of the present invention, the audio data is sequentially read out from the buffer memory in the decoding unit by predetermined bits and decoded,
When the empty area of the memory detected from the difference between the read address and the write address is equal to or more than one time slot, the received audio data for one time slot is continuously written from the time division multiplexing unit to the buffer memory.

In the time-division multiplex communication apparatus according to the present invention, the continuous writing of the audio data for one time slot is performed at the same rate as the reception rate.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a time division multiplex communication apparatus according to an embodiment of the present invention. In this device,
The encoding / decoding unit 12 is provided with a serial interface unit 14 in addition to the encoder / decoder 13. The encoder / decoder 13 includes an encoder 13-1 and a decoder 13-2, and the serial interface unit 14 includes a serial interface 14-1 and a serial interface 14-2. The TDMA control unit 16 is connected to the high-frequency processing unit 21 via the modulator 17 and the demodulator 18, and is also connected to the CPU 24. The high-frequency processing unit 21 transmits a signal from the antenna 22 based on the transmission frequency from the PLL 23. The CPU 24 is connected to an operation unit 25 having keys necessary for dialing and predetermined control keys, and a display unit 26 having a liquid crystal display and the like. Note that a receiver 27 is connected to the encoder / decoder 13.

A characteristic feature of the time division multiplex communication apparatus having the above configuration is that a serial interface section 14 is provided in the encoding / decoding section 12. The serial interface 14 has a function of adjusting a difference in data transfer speed between the encoder / decoder 13 and the TDMA controller 16.

FIG. 2 shows the encoding / decoding section 12 in FIG.
3 shows a main part of the encoding unit 12-1 related to the transmission processing in detail. This circuit includes an encoder 13-
1 and a serial interface 14-1. The encoder 13-1 is provided with an encoding circuit 32, which A / D converts the audio signal 41 input from the transmitter 11 (FIG. 1) to encode it into 4-bit digital data, and performs parallel / serial conversion. Input to the device 33. The encoding at this time is performed based on a sampling timing signal 42 of 8 kHz as shown in FIG. The sampling timing signal 42 is also input to the write clock generator 34 and the parallel / serial converter 33. The write clock generator 34 converts the sampling timing signal 42 into the write clock 4 as shown in FIG. 5C based on the basic clock 43 as shown in FIG.
4 is input to the parallel / serial converter 33 and the write address generation circuit 37 in the serial interface 14-1. The parallel / serial converter 33 converts the 4-bit parallel signal from the encoding circuit 32 to serial based on the write clock 44, and outputs it as serial data 48 as shown in FIG. The data transfer speed at this time is 32 kbps (= 4 bits x 8 kHz)
It has become. That is, the audio data 48 input from the encoder 13-1 to the serial interface 14-1.
Is a 4-bit serial signal every 125 μs as shown in FIG.

In the write address generation circuit 37 of the serial interface 14-1, as shown in FIG.
The write clock 44 is counted by the address counter 61, and is input to the address decoder 62 as an 8-bit write address count signal 46, and is also input to the address difference detection circuit 38 in FIG. The address decoder 62 carries out decoding in which one of the 256 signals is set to a high level based on the input 8-bit write address count signal 46. The decoded signal 52 is input to the buffer memory 35 in FIG.

On the other hand, a clock output section (not shown) of the TDMA control section 16 (FIG. 1)
A read clock signal 54 as shown in FIG. 4B is output in synchronization with a slot, that is, a synchronization signal every 5 ms. This read clock signal 54 is input to the read address generation circuit 36 of the serial interface 14-1. The read address generation circuit 36 has the same configuration as the above-described write address generation circuit 37 (FIG. 3), counts the input read clock signal 54 and outputs a read address count signal 45, This is decoded and an address decode signal 51 is output. The address decode signal 51 is input to the buffer memory 35. On the other hand, the read address count signal 45 is input to the address difference detection circuit 38.

The address difference detection circuit 38 detects the difference between the input write address count signal 46 and read address count signal 45, and outputs 8-bit difference data. The difference determination circuit 39 compares the difference data with the read start condition data 47 prepared in a register (not shown).
(8 bits), and when the former exceeds the latter,
A read enable signal 56 is output. That is, the read enable signal 56 is output when the difference between the write start address for the buffer memory 35 and the read start address when reading from the memory is 160 addresses or more.

For example, as shown in FIG. 7, when the distance between the write address Y and the read address X out of the 256 addresses of the buffer memory 35 exceeds 160, reading from the buffer memory 35 is performed. Becomes Here, the numeral 160 indicates an address at which data corresponding to 40 samples of audio data transmitted from the encoder 13-1 in 4 bits at a time is stored, and that writing of the 40 samples is completed. As a condition, data for 160 addresses is read at a stretch. In addition,
In FIG. 7, the reading is started when the write address becomes Y and the read address becomes X. However, it is only necessary that the relative address distance between the two is kept over 160. Are sequentially shifted.

In the buffer memory 35, as shown in FIG. 4, 256 write address signals 52 are input to 256 memory cells 64-1 to 64-256, respectively. Is written to the cell corresponding to the memory cell of which write address signal 52 is at the high level. Similarly, in the case of reading, the read data 55 is read from the cell corresponding to the signal line of the 256 read address signals 51 which has become the high level. Read data 5 in this case
5 is read out in synchronization with the above read clock 54 as shown in FIG. 6 (c). As a result, 160 bits are continuously read out every 5 ms in synchronization with the slot synchronization signal (FIG. 6 (a)). Is done. At this time, the clock rate of the read clock 54 is 384 kbps, which corresponds to the TDMA control unit 1.
6 to the modulator 17. Therefore, the data read from the buffer memory 35 is TDM
The signal passes through the A control unit 16 and is transmitted to the modulator 17. However, at this time, in the TDMA control unit 16, C
Under the control of the PU 24, a necessary control header is added, and a slot of a predetermined format is formed.

As described above, the serial interface unit 14 buffers 40 samples of the encoded 4-bit audio data, and when these 40 samples are stored, these 160-bit audio data are stored. Audio data is continuously read at the transmission rate and input to the TDMA control unit 16. Therefore, the TDMA control unit 16 does not need to perform any buffering process corresponding to the interrupt process from the encoding / decoding unit 12 as in the related art, and can concentrate on only adding the header control unit. it can. Therefore, a complicated circuit for interrupt processing is not required, and the circuit configuration can be extremely simplified.

Although the above-described embodiment has been described for the case of transmission, it can be similarly applied to the case of reception. That is, in the case of reception, a decoding unit 12-2 is provided as shown in FIG. The decoder 12-2 is provided with a decoder 13-2 and a serial interface 14-2. The operation in this case is a process completely opposite to that of the above-described transmission. In this figure, the reference numerals of the respective parts in FIG. 2 are increased by 100, and the words "read" are used in place of "write" and the word "write" is used in place of "read". ing. In this case, since the read rate is slower than the write rate, when the empty area of the memory detected from the difference between the read address and the write address exceeds 160,
A write enable signal 156 is output,
At a speed of 4 kbps, the audio data 155 is continuously written into the buffer memory 135 for 160 bits. Reading from the buffer memory 135 is performed at a rate of 32 kbps with 4 bits every 125 μs. The read data 148 is converted into a 4-bit parallel signal by the serial / parallel converter 133 of the decoder 13-2, decoded by the decoding circuit 132, further A / D converted, and converted into an analog audio signal 141. Is output from the receiver 27 (FIG. 1). The operations of the read clock generation unit 134, the write address generation circuit 136, the read generation circuit 137, and the like are the same as those in the case of the above-described transmission, and a description thereof will be omitted.

In this embodiment, the width of the time slot generated by the TDMA control unit 16 is 5 ms. However, the present invention is not limited to this, and it is needless to say that the present invention can be applied to a time slot having another length. . Further, in the present embodiment, the description has been made assuming that the audio signal is sampled with 4 bits. However, the present invention can be similarly applied to the case where the audio signal is sampled with 16 bits or more. In this embodiment, as described with reference to FIG. 4, since the read data line and the write data line are separately provided as the buffer memory, control is performed so that the read address does not collide with the write address. Thus, reading and writing can be performed simultaneously. Therefore, as shown in FIG.
The above-described processing can be cyclically performed using a buffer memory having very few memory cells, and the capacity of the buffer memory can be extremely reduced.

[0027]

As described above, according to the first aspect of the present invention, the sampled audio data is sequentially written into the buffer memory in the encoding unit, while the time division multiplexing unit writes the sampled audio data into the write address and the read address. When the difference becomes equal to or greater than one time slot, the audio data for one time slot is continuously read, so that the time division multiplexing unit frequently receives an interrupt request from the encoding unit (for each audio sampling). Nothing. Therefore, the time division multiplexing unit
It is only necessary to perform the original time slot generation processing exclusively, and it is not necessary to perform the processing in response to the interrupt request. Therefore, the circuit configuration and the program configuration of the time division multiplexing unit can be simplified. On the other hand, providing the encoder with a buffering function can be easily realized with a very simple circuit configuration. Therefore, there is an effect that the configuration of the entire apparatus is simplified.

Similarly, in the third aspect of the present invention,
The time division multiplexing unit writes the received audio data for one time slot continuously when the difference between the read address and the write address of the buffer memory in the decoding unit becomes one time slot or more. The division multiplexing unit does not frequently receive an interrupt request from the decoding unit. Therefore, the configuration can be simplified, and the same effect as that of the first aspect can be obtained.

According to the second and fourth aspects of the present invention, the data read / write rate from the time division multiplexing unit to the buffer memory in the encoding unit or the decoding unit is the same as the data transmission / reception rate. Has the effect of passing through the time-division multiplexing unit in a through manner, and has the effect of further simplifying the processing.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a time division multiplex communication device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a portion related to transmission of the time division multiplex communication device.

FIG. 3 is a block diagram illustrating a read (write) address generation unit.

FIG. 4 is a block diagram showing a configuration of a buffer memory.

FIG. 5 is a timing chart showing writing of audio data to a buffer memory.

FIG. 6 is a timing chart showing reading of audio data from a buffer memory.

FIG. 7 is an explanatory diagram showing the principle of addressing of a buffer memory.

FIG. 8 is a block diagram showing a portion related to reception of the time division multiplex communication device.

FIG. 9 is a block diagram showing a conventional time division multiplex communication device.

FIG. 10 is a timing chart showing the output timing of audio data from the encoding / decoding unit to the TDMA control unit of the conventional time division multiplex communication device of FIG.

[Explanation of symbols]

 Reference Signs List 12 encoding / decoding unit 13 encoder / decoder 13-1 encoder 13-2 decoder 14 serial interface unit 14-1 serial interface (transmission side) 14-2 serial interface (reception side) 16 TDMA control unit 35, 135 Buffer memory 36, 137 Read address generator 37, 136 Write address generator 38, 138 Address difference detection circuit 39, 139 Difference determination circuit

Continuation of front page (56) References JP-A-58-92155 (JP, A) JP-A-62-2747 (JP, A) JP-A-3-24845 (JP, A) JP-A-1-146443 (JP) JP-A-62-11328 (JP, A) JP-A-3-505960 (JP, A) JP-T-63-502867 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H04J 3/22-3/26 H04B 7/24-7/26 H04L 29/00-29/14

Claims (4)

(57) [Claims] 1. An apparatus comprising: an encoding unit for performing digital encoding of an audio signal; and a time division multiplexing unit for generating transmission audio data for a time slot having a predetermined time width based on output data of the encoding unit. An encoding circuit that samples an analog audio signal at a constant period and outputs digital audio data having a predetermined bit width; and a transmission audio data storage capacity corresponding to at least one time slot. A buffer memory for sequentially storing digital audio data output from the encoding circuit at a constant cycle; and counting a write clock indicating a write address of the digital audio data from the encoding circuit to the buffer memory. And a read address of digital audio data from the buffer memory to the time division multiplexing unit. A read address counter that counts the read clocks indicated by the read address counter; a difference detection circuit that detects a difference between the count value of the write address counter and the count value of the read address counter; and a difference detected by the difference detection circuit is one time slot. A data read request unit for requesting the time division multiplexing unit to read out digital audio data when the data amount becomes equal to or more than the data amount corresponding to the minute, the time division multiplexing unit responds to the read request, A time-division multiplex communication device, wherein digital audio data for one time slot is continuously read from the buffer memory. 2. The time division multiplex communication apparatus according to claim 1, wherein a read rate of the digital audio data from the buffer memory by the time division multiplex unit is equal to a transmission rate. 3. An apparatus comprising: a time division multiplexing unit for receiving digital audio data for a time slot of a predetermined time width; and a decoding unit for decoding the digital audio data, wherein the decoding unit A buffer memory for storing the digital audio data received by the time division multiplexing unit for at least one time slot; and reading and decoding the digital audio data written in the buffer memory at a predetermined cycle for each predetermined bit, and converting the analog audio signal. A decoding circuit for outputting; a read address counter for counting a read clock indicating a read address of digital audio data from the buffer memory to the decoding circuit; and a digital audio data from the time division multiplexing unit to the buffer memory. Write address for counting the write clock indicating the write address Counter and a difference detection circuit for detecting the air region of the memory from the difference of the count value of the count value of the read address counter and said write address counter, empty areas of the memory detected by the difference detection circuit 1
A data write requesting unit for requesting the time division multiplexing unit to write digital audio data when the data amount becomes equal to or more than the data amount corresponding to the time slot, wherein the time division multiplexing unit 1 received according to the
A time-division multiplex communication device, wherein digital audio data for a time slot is continuously written in the buffer memory. 4. The time division multiplex communication device according to claim 3, wherein a writing rate of the digital audio data to the buffer memory by the time division multiplexing unit is the same as a reception rate.