JPS63234454A - Reproducing system of sampling clock for decoding - Google Patents

Abstract

PURPOSE:To simply and easily attain coincidence between the transmission clock frequency on the transmission side and the frequency of a sampling clock on the reception side by controlling the frequency of the sampling clock for decoding on the reception side in accordance with the difference between phase difference information between the frequency of the sampling clock for decoding a reception signal and the transmission clock frequency and phase difference information from the transmission side. CONSTITUTION:Phase difference information between the sampling clock frequency and the transmission clock frequency in a multiplexer 3 is transmitted to the reception side from a transmission equipment 5. On the reception side, transmission information from the transmission side is received by a reception equipment 7 and is separated into code words and phase difference information by a separating device 9. Code words and phase difference information are sent to a decoder 10 and a reception controller 11 respectively, and the reception controller 11 detects the difference between phase difference information between the transmission clock frequency, which is extracted from transmission information from the transmission side by the reception equipment 7, and the sampling clock frequency for decoding and phase difference information from the transmission side and controls the frequency of the sampling clock for decoding so that this difference is a certain value.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to decoding in a digital transmission system in which the sampling frequency used for encoding an input signal and the transmission frequency for transmitting code words are asynchronous. The present invention relates to a sampling clock recovery method, and particularly to a decoding sampling clock recovery method suitable for matching the sampling clock frequency on the receiving side to that on the transmitting side.

(Prior Art) In a digital transmission system in which a sampling clock and a transmission clock are asynchronous, on the receiving side, a sampling clock can be created from the transmission clock. The speed of each clock is converted between the sampling clock and the sampling clock on the receiving side via a buffer memory.In this case, the amount of information written to the buffer memory on the sending side and the amount of information read from the buffer memory on the receiving side are must match.This can be compared to the frequency of each clock.

The frequency of the sampling clock on the receiving side must be controlled so that the phase difference between the sampling clock and the transmission clock on the transmitting side matches the phase difference between those clocks on the receiving side.

Here, the transmission and reception operations in this type of digital transmission system will be briefly explained as follows.

That is, on the transmitting side, an input analog signal such as a video signal is converted into a digital signal of a predetermined number of bits at regular intervals using a sampling clock, and then encoded and compressed. Through this coding compression, the digital signal is compressed into a signal whose number of bits is smaller than the predetermined number of bits (constant number of bits), but at this time, the code word as the unit that is actually transmitted to the receiving side is compressed. can be obtained with multiple types of bit numbers.

In this case, the length of the codeword to be actually transmitted can be identified by the codeword, so that a codeword having the above-mentioned fixed number of bits can be obtained at most. The codewords obtained sequentially in this way are converted into continuous serial data by the transmitting device via a transmitting buffer memory as a FIFO under the intervening control of a transmitting clock whose constant period is smaller than that of the sampling clock. This is what is sent to the receiving side in the same state.

On the other hand, on the receiving side, the transmission clock is extracted from the continuous serial data from the transmitting side, and after passing through the receiving buffer memory as FIFO, the continuous serial data is converted to the original predetermined number of bits based on the upper 2 bits. It is designed to be decoded as a parallel-converted digital signal.

By the way, up until now, the
As described in Publication No. 3, in the case of digital transmission in which the information generation rate and the information transmission rate change irregularly over time, the amount of transmitted information written to the transmission buffer memory device during a certain period of time on the transmitting side After counting, the amount of information stored in the transmission buffer memory device and the amount of transmitted information are transmitted to the receiving side as control information together with the transmitted information. On the receiving side, the control information is separated from the received information and compared with the amount of information stored in the receiving buffer memory device, and the comparison result is used to control the reading time of information from the receiving buffer memory device. The information propagation delay time from input to the device to output from the reception buffer 7 memory device is controlled to be constant.

[Problem that the invention seeks to solve]

As described above, until now, the sum of the accumulated amount of transmitted information stored in the transmitting buffer memory device and the accumulated amount of received information stored in the receiving buffer memory device is calculated within a certain period of time. The time at which received information is read from the receiving buffer memory device is controlled using the relationship that it matches the amount of information written in the transmitting buffer memory device. However, since the readout time of the received information from the receive buffer memory device is controlled based on the amount of information stored in the transmitter/receive buffer memory device, the control information is smaller than the information from the sending side by the time it is input to the receive buffer memory device. There was a problem with the complexity of the control, as it had to be separated.

An object of the present invention is to provide a decoding sampling clock regeneration method that can easily and easily match the frequencies of sampling clocks on the transmitting and receiving sides even when the information generation rate and the information transmission rate change irregularly with time. It is to provide.

[Means for solving problems]

The above purpose is to transmit phase difference information between the sampling clock frequency for input signal encoding and the transmission clock frequency for information transmission from the transmitting side to the receiving side, while the receiving side transmits the sampling clock frequency for decoding the received signal to the receiving side. This is achieved by controlling the frequency of the decoding sampling clock according to the difference between the phase difference information between the frequency and the transmission clock frequency and the phase difference information from the transmitting side.

[Effect]

On the transmitting side, the phase difference between the sampling clock frequency for input signal encoding and the transmission clock frequency is determined, and this phase difference information is multiplexed with the code word and transmitted to the receiving side via the transmitting buffer memory device. This is how it is. Furthermore, on the receiving side, the transmitted information from the transmitting side is separated into phase difference information and a code word after passing through a reception buffer memory device, and the frequency of the sampling clock is controlled by this phase difference information. It is something.

That is, the phase difference is calculated from the sampling clock frequency for decoding the code word and the transmission clock frequency, and the phase difference between this phase difference information and the phase difference information from the transmitting side is kept constant. By controlling the sampling clock frequency for decoding, the sampling clock frequency on the receiving side can be made to be the same as the sampling clock frequency on the transmitting side.

〔Example〕

The present invention will be explained below with reference to FIGS. 1 to 6.

First, to explain the principle of the present invention, as shown in FIG. The sum of the amount of information stored in the reception buffer memory section 23 needs to be a constant value. When the sum of this information storage amount is W, the amount written to the transmission buffer memory section 22 is kj
If the amount read from the reception buffer memory unit 23 is V, then when ν,=&/, W=a constant value and the input signal can be reproduced accurately. This amount of writing &71
gReading amount V! are the encoding unit 21 and the decoding unit 2, respectively.
4, but this processing speed is also determined by the sampling clock frequency in the encoding unit 21 and decoding unit 24, and if the sampling clock frequencies are the same, the sum W of the information storage amount is It becomes a constant value.

As is clear from the above principle, if the sampling clock frequency in the encoding section and the decoding section is the same with respect to the transmission clock frequency, the sum of the amount of information stored in the buffer memory section will be constant and the transmission will be stable. FIG. 1 shows a schematic configuration of an example of a transmitting side and a receiving side in a digital transmission system according to the present invention. If this is the case.

When an image signal is input from input terminal 1, encoding device 2
The code word is converted into a code word and then sent to the multiplexer 3. In the multiplexing device 3, the transmission control device 6
The phase difference information between the sampling clock frequency and the transmission clock frequency is multiplexed into the code word and then transmitted from the transmitting device 5 to the receiving side via the transmitting buffer memory device 4. On the other hand, on the receiving side, the transmitted information from the transmitting side is received by a receiving device 7, and is separated into a code word and phase difference information by a separating device 9 via a receiving buffer memory device 8.

The code word is sent to the decoding device 10, and the phase difference information is sent to the reception control device 11, where the reception control device 11 decodes the transmission clock frequency extracted from the transmission information from the transmitting side by the reception device 7. The difference between the phase difference information from the sampling clock frequency for decoding and the phase difference information from the transmitting side is detected, and the frequency of the sampling clock for decoding is controlled so that the difference becomes a constant value. It is what it is. In the decoding device 10, the code word is decoded by a sampling clock whose frequency is controlled and then outputted from the output terminal 12.

The outline of the operation of the digital transmission system according to the present invention is as described above, and FIG. 3 shows a specific example of the phase difference information creation section on the transmitting side, and FIG. 4 shows a specific example of the sampling clock frequency control section on the receiving side. This shows a specific example.

As shown in FIG. 3, within the transmission control device 6, the transmission clock from the transmission clock oscillator 6-1 is counted by the counter 6-2, while the latch timing generation circuit 6-4 uses the transmission clock to count the transmission clock from the transmission clock 6-1. Latch timing is created at appropriate intervals, such as once per horizontal period. At this latch timing, the output of the counter 6-2 is latched in the latch 6-3 as phase difference information and then sent to the multiplexer 3.

FIGS. 5(a) and 5(b) show the latch timing generation circuit 6-
This figure shows the specific configuration and main input/output signal waveforms in an example centered on 4.1 As shown in the figure, the sampling clock is divided by a frequency divider 6-4-1 at a division ratio of 1/n. The divided clock as a frequency-divided output acts as a reset signal on the D-type flip-flop 6-4-3. That is, the D-type flip-flop 6-4-3 is reset at a cycle equivalent to n sampling clocks. on the other hand.

The transmission clock is input as a clock to the D-type flip-flop 6-4-3 via the inverter 6-4-2, and the D-type flip-flop 6-4-3 is set at the falling edge of the clock until the next divided clock is obtained. It has become a state of affairs.

Furthermore, inside the reception control device 11, as shown in FIG.
As in the case of Fig. 3, the transmission clock is the counter 11-1.
On the other hand, the latch timing generation circuit 11-5 calculates the third clock from the transmission clock and the sampling clock.
Latch timing is created at the same interval as in the case of the figure, and the counter 11-1 output at this timing is the latch 11-1.
2 as phase difference information.

After this, the difference between this receiving side phase difference information and the phase difference information from the transmitting side is obtained by a subtracter 11-3, and according to this difference, a voltage controlled oscillator is used to determine the frequency of the receiving side sampling clock. By controlling 11-4, the frequency of the sampling clock on the transmitting side is made to match the frequency of the sampling clock on the receiving side.

FIGS. 6(a) and 6(b) show a specific configuration and main part input/output signal waveforms of an example of the reception control device 11. As shown in the figure, the sampling clock is a frequency divider 1 with a frequency division ratio of 1/n.
The frequency-divided clock, which is frequency-divided by 1-5-1 and output as a 1-frequency output, is input as data to a D-type flip-flop 11-5-3. The frequency-divided clock is set in the D-type flip-flop 11-5-3 at the rising edge of the inverted transmission clock from the inverters 11-5 to 11-2. In the voltage controlled oscillator 11-4, v
C○ Main body 11-4-2 is low pass filter 11-4-1
The output frequency is controlled by the difference in phase difference information transmitted through the .

〔Effect of the invention〕

As explained above, according to the present invention, the sampling clock frequency for encoding an analog signal such as an image signal and the transmission clock frequency, and the transmission clock frequency and the sampling clock frequency for decoding are asynchronous, and digital transmission is performed. In this case, the sampling clock frequency for encoding and decoding can be matched, and the total amount of storage can be kept constant and stable digital transmission can be performed without directly controlling the amount of writing and reading of the transmitting and receiving buffer memory device. It has the effect of allowing you to do this.

[Brief explanation of the drawing]

1 is a diagram showing an example of a schematic configuration of a transmitting side and a receiving side in a digital transmission system according to the present invention; FIG. 2 is a diagram for explaining the present invention in detail; FIGS. 3 and 4. The figures show the configurations of main parts of a transmission control device and reception control device, respectively, and FIGS. Figure 6 (a)
) and (b) are diagrams showing a specific configuration and main part input/output signal waveforms in an example of a reception control device. 2... Encoding device, 3... Multiplexing device, 4... Transmission buffer memory device, 5... Transmission device, 6... Transmission control device, 7... Receiving device, 8... - Reception buffer memory device, 9... Separation device, 10... Decoding device, 11... Reception control device, 6-1... Multi-transmission oscillator, 6-2.11-1. ...Counter, 6-3.1
1-2... Latch, 6-4° 11-5... Latch timing generation circuit, 11-3 peak subtracter, 11-4...
Voltage controlled oscillator.

Claims (1)

[Claims] 1. A sampling clock recovery method for decoding in a digital transmission system in which the sampling frequency used for encoding the analog input signal on the transmitting side and the transmission frequency for codeword transmission are asynchronous, and The phase difference information between the sampling clock frequency for input signal encoding and the transmission clock frequency for information transmission is multiplexed into transmission information and transmitted to the receiving side. For decoding, the frequency of the sampling clock for decoding is controlled according to the difference between the phase difference information between the transmission clock frequency extracted from the transmission information and the phase difference information from the transmitting side. Sampling clock recovery method.