JPS61198988A - Image encoding and transmitting system - Google Patents

Abstract

PURPOSE:To improve transmission efficiency by thinning out every other one of image frames and executing reading from and writing in a transmission/ reception double buffer in an encoded image frame unit to form a data frame with header and by transmitting the said data. CONSTITUTION:From the data outputted from an A/D converter 1, one image frame out of every two is thinned out through an image encoding circuit 100, and is supplied to a transmission buffer 101. The buffer 101 comprises first and second buffers, and its input and output are alternately switched by the control from a controller 107. A header generating circuit 15 generates the header information of the transmital data frame. The said header information is multiplexed with the encoding data etc. by a transmital data multiplexing circuit 16. Thereafter, an error correction code is added to the said multiplexed data, and a frame synchronizing patter is inserted to constitute the transmital frame.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention converts an analog visual signal into digital data and encodes it, and then transmits the encoded data at a predetermined transmission rate through a digital transmission path. The present invention relates to an image encoding and transmitting device.

[Conventional technology]

FIG. 5 is a block diagram showing an example of the configuration of a conventional image encoding and transmitting device. In FIG. 1, (1) is an A/D converter that converts an input analog video signal into digital data, and (2) is Video frame pulse from analog video signal,
A synchronizing signal generation circuit that generates a lock necessary for encoding line pulses, etc. +3+ is an image encoding circuit that converts the output signal of the A converter into encoded data using a high-efficiency encoding method; (4) is one video frame time (1/30 second)
a transmission buffer memory that stores encoded data encoded in the buffer memory and transmits it at a constant transmission rate; t51 is an error correction encoding circuit that performs error correction encoding on the encoded data transmitted from the buffer memory; (6) is a transmission line clock source that outputs a clock for transmitting data onto the transmission line at a predetermined speed, and (7) is a transmission line clock source that outputs a clock for transmitting data onto the transmission line at a predetermined speed. a frame configuration circuit that configures a transmission frame for (8)
) is a frame decomposition circuit that decomposes the data of the transmission frame sent through the transmission path and converts it into an encoded data string, and (9) is an error correction circuit that performs the reverse process of the error correction encoding circuit described above to correct errors. A correction decoding circuit, U is a control information decoding circuit that decodes the encoded control information inserted in the received data and detects the beginning position of the video frame. (111 is a decoding clock necessary for subsequent decoding processing. a clock regeneration circuit for regeneration; a reception buffer memory for storing reception data supplied at a constant α2Vi transmission rate and transmitting reception data in units of one video frame; (131 is for reception data supplied from the buffer memory; An image encoding circuit decodes digital data by performing the inverse processing of the image encoding circuit described above, and α4) is a D/A converter that converts the digital data decoded by the image decoding circuit into an analog video signal and outputs it. It is.

Next, the operation will be explained. The digital data output from the p-/D converter (1) is sent to the 9-image encoding circuit (3).
The signal is encoded using a high-efficiency encoding technique such as interframe encoding in which the encoding speed is not constant, and is sent to buffer memo sound 4). buffer memory.

It is composed of a double buffer that performs read and write operations simultaneously, stores encoded data generated in one video frame time (1/30 seconds), and transmits it at a predetermined transmission speed, and according to the amount of data stored. Encoding control information is generated and the nine image encoding circuits are feedback-controlled to perform speed smoothing. Next, the encoded data is sent out from the buffer memory.

The error correction encoding circuit (5) multiplexes audio data and encoding control information, and collects a certain data string and converts it into BC.
An error correction code such as an H code is added, a frame synchronization pattern is inserted in a frame configuration circuit (7), and a transmission frame is constructed in which data strings are rearranged. The configuration sequence of the transmission frame is shown in Figure 6. The received data sequence transmitted through the digital transmission path is as follows:
In the frame decomposition circuit (8), data strings are rearranged in synchronization with the frame synchronization pattern by the reverse process described above, and after error correction processing is performed in the error correction decoding circuit (9), the audio data is Separated. Next, the control information decoding circuit αl detects the start position of the video frame from within the transmission frame, and reproduces the video frame synchronization pulse at the time of decoding.

Furthermore, the decoding clock is regenerated by the clock regeneration circuit 1).Meanwhile, the received data after the start position of the video frame described above is stored in the buffer memory α2 until the start position of the primary video frame is detected. Using the reproduced decoding clock, the video signal is decoded by the image decoding circuit 0 through the reverse process of the image encoding circuit described above according to the encoding control information, and converted into an analog video signal by the D/A converter α4. It is.

It is played back and output.

[Problem that the invention seeks to solve]

The conventional image encoding and transmitting device is configured as described above (
・Therefore, it is necessary to establish video frame synchronization between the transmitter and receiver, and in order to indicate the start position of the video frame, the transmitter side calculates the time difference between the transmission frame synchronization pattern and the start position of the video frame (number of time slots). ) and transmit it to the receiving side, it is also necessary to count the number of transmission locks within one video frame time and transmit it to the receiving side.

On the receiving side, the start position of the video frame must be detected from this information and the lock required for decoding processing must be regenerated, making the device configuration and transmission control method complicated.
Also, if the transmission speed is low.

The amount of information that can be transmitted in one video frame time is reduced,
Even if speed smoothing is performed in the transmitting side buffer memory, there are problems such as the transmission efficiency of encoded data deteriorates and the synchronization of video frames during transmission and reception cannot be established.

This invention was made to solve the above problems, and it is possible to match the temporal timing of video frames between transmitters and receivers without transmitting the start position information of video frames and decoding clock information to the receiving side. It is an object of the present invention to configure an image encoding and transmitting apparatus that facilitates control of a transmission control method and a transmitting/receiving buffer for speed smoothing.

[Means for solving problems]

The image encoding and transmitting device according to the present invention thins out video frames to be encoded and transmitted every other frame, inserts a header generation circuit on the transmitting side, a header decoding circuit on the receiving side, and A controller controls a transmitting/receiving double buffer that stores encoded data on a frame-by-frame basis, and a decoding synchronization signal generation circuit is also inserted on the receiving side.

[Effect]

The transmitting double buffer in this invention is controlled by the controller so that the read operation is switched alternately at the middle of encoded data for one video frame, and the receiving double buffer is controlled by the controller so that the write operation is identified by the received header. The encoded data for one video I frame is controlled to alternately switch at the middle level.

Encoded data is transmitted without interruption.

Further, on the receiving side, the encoded data written in the reception buffer is read out within one video frame period defined by the video frame synchronization signal supplied from the decoding synchronization signal generation circuit, and then decoded.

By repeatedly outputting the decoded video frames to the other buffer,
Embodiment of the Invention Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1st
In the figure (・te, (1) ~ (bright, (5) ~ (71, +81
~(9).

α4)fi is the same as the above conventional device. (io
O) is an image encoding circuit, (102) is a transmission control unit on the transmission side, and (103) is a transmission control unit on the reception side. q9 is a header generation circuit that generates a header ladder for identifying the data frame to be transmitted; (101) is a header generation circuit that generates a header ladder for identifying the data frame to be transmitted; Store according to the instructions of the controller.

A transmission buffer that transmits data at a predetermined transmission speed;
ae is a transmission data multiplexing circuit that multiplexes the encoded data sent from the transmission buffer and other data such as a header, and at is a header decoding circuit that decodes the header of the transmitted data frame. is a received data separation circuit that separates encoded data and audio data, (
104) stores the received encoded data and sequentially executes the image decoding circuit (105) according to instructions from the controller.
(106) a receive buffer that provides encoded data to the
(107) is a decoding synchronization signal generation circuit that generates various clocks for performing decoding operations asynchronously with the transmitting side, and (107) is a controller that controls the transmitting and receiving buffer. In fig.

(2) and θ are buffers having the same capacity, and (2) and (to) are selectors for switching the operation of the buffers.

Next, the operation of the above embodiment will be explained using FIGS. 1 to 3. The digital data output from the A/D converter (100) is thinned out every other frame, and then sent to a 9-picture encoding circuit (100) where the interframe code is processed at a constant encoding speed ( - It is encoded using a high-efficiency encoding method and supplied to the transmission buffer (101).The transmission buffer is a double buffer that performs read and write operations simultaneously, and is configured as shown in Fig. 2.Buffer 1.2 is Selector 1.2 under control from controller (107)
The human output is switched by , and at the same time the current data storage amount is supplied to the controller. The header generation circuit a5 is a circuit that generates header information of a transmission data frame, and when encoded data at the start position of a video frame is sent to the transmission data multiplexing circuit, it generates a specific header indicating the start position of the video frame. Output. This header information is multiplexed with encoded data, audio data, etc. in the transmission data multiplexing circuit ae (), and after adding an error correction code, a frame synchronization pattern is inserted in the frame configuration circuit +71, and the data The columns are rearranged to form a transmission frame.An example of the structure of a transmission frame with a header is shown in FIG.

The received data string transmitted through the digital transmission path is
In the frame disassembly circuit (8), data strings are rearranged in synchronization with the frame synchronization pattern by the process reverse to that described above, and after error correction processing is performed in the error correction decoding circuit (9), the header are separated. The header is identified by a header decoding circuit αe, audio data is separated by a received data separation circuit α9 according to the structure of the data frame, and the encoded data is sent to a receiving buffer. The reception buffer (104) stores encoded data from the data frame indicating the beginning of the video frame identified by the video frame identification signal to the next similar data frame, and stores the encoded data from the data frame indicating the beginning of the video frame identified by the video frame identification signal, and stores the encoded data from the data frame indicating the beginning of the video frame identified by the video frame identification signal. The encoded data is sent to the image encoding circuit (105) in synchronization with the video frame pulse, and decoding processing is performed using the encoding clock supplied from the decoding synchronization signal generation circuit. +14), it is converted into an analog video signal and reproduced and output.

Next, the relationship between the operation of the transmitting/receiving buffer and the transmitted/received video frames according to the present invention will be explained using FIG. 4. Both the transmitting and receiving buffers have the configuration shown in FIG. On the transmitting side, the controller monitors whether the buffer 1.2 is empty based on the accumulated amount from the buffer 1.2, and provides write and output control signals to the selectors 1 and 2 depending on the status of each buffer. It is assumed that buffer 1 is now in an empty state. *f, the encoded data of frame A is written to buffer 1 in synchronization with the encoding on/off signal that changes at the timing of frame pulses every other movie frame. At this point, buffer 2 is reading frame X. After writing to buffer 1 and reading from buffer 2 is completed,
Buffer 1 immediately starts reading frame A, and buffer 2 writes frame B in synchronization with the next encoding ON signal. Thereafter, the read and write operations are repeated in the same way. At this time, even if writing to buffer 1 has been completed, if reading from buffer 2 is continuing (frame C in the figure), (frame B in the figure) ) frame C of buffer 1
Reading of buffer 2 is in a waiting state, and buffer 2 is empty (), so writing becomes impossible and encoding of frame D is stopped. Conversely, even if reading of buffer 1 is completed (frame F in the figure) , if writing to buffer 2 is not completed (・ri (frame G in the figure), dummy data is read from buffer 1 until writing to buffer 2 is completed,
Output as an idle transmission frame.

As described above, transmission is performed so that the read operations of buffers 1 and 2 are not interrupted.

On the receiving side, the writing operations of buffers 1 and 2 are alternately and continuously switched, and when the writing is completed, the buffer immediately performs reading in synchronization with a frame pulse generated asynchronously with the sending side. Then, until writing to the other buffer is completed, the previously read and decoded video frame is repeatedly output in synchronization with the frame pulse, and the video 1a
Adjust the frame transmission delay amount.

Note that in the above embodiment, it is also possible to configure a data frame in which control data and the like are multiplexed by increasing the number of header information.

Furthermore, in the human input signal of the nine-painter encoding circuit, every other field may be thinned out.

〔Effect of the invention〕

As described above, according to the present invention, the video frames to be encoded and transmitted are thinned out every other frame, the reading and writing of the transmitting and receiving double buffers are performed at the same time as the encoded video frame, and the data frame with header is An image encoding and transmitting device is configured that encodes and decodes video frames between transmission and reception asynchronously.
Transmission control of transmission and reception can be easily performed, speed smoothing by a transmission buffer can be easily controlled, encoded data can be transmitted without interruption, and transmission efficiency can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image coding and transmitting device according to an embodiment of the present invention, FIG. 2 is a block diagram of a transmitting and receiving buffer used in the image coding and transmitting device, and FIG. 3 is an example of a transmission frame with a ladder. The configuration diagram shown. Fig. 5 is a timing diagram for explaining the operation of the transmitting and receiving buffer, Fig. 5 is a configuration diagram of a conventional image encoding and transmitting device, and Fig. 6
The figure is a configuration diagram showing an example of a conventional transmission frame. (10 is the image@shrine/encoding circuit, (101) is the transmission buffer, (102) is the transmission control unit on the transmission side, (ios) is the transmission control unit on the reception side, (104) is the reception buffer, (i
os) is an image decoding circuit. (1 (M) is the decoding synchronization signal generation circuit, (107) is the controller. In Figure 2, the same group number indicates the same or equivalent part.

Claims (4)

[Claims] (1) An image encoding circuit that inputs a video signal, performs frame-by-frame image high-efficiency encoding processing on digital video data that is thinned out every other video frame after A/D conversion, and the image coder. It is composed of a double buffer that simultaneously writes and reads the variable-length encoded data, which is the output of the encoding circuit, where the amount of information generated is not constant, and stores it for one video frame, smoothes the speed, and outputs the encoded data at a constant speed. a transmitting buffer, a transmitting-side transmission control unit configured to frame the encoded data transmitted from the transmitting buffer so that each video frame can be identified for transmission, and transmit the encoded data to a digital transmission path at a constant speed; A reception-side transmission control unit receives the encoded data transmitted from the digital transmission path, and stores the encoded data for one video frame in the received data supplied from the reception-side transmission control unit, and decodes it later. A receiving buffer consisting of a double buffer that simultaneously writes and reads the encoded data for one video frame at a speed different from the input speed using a synchronizing signal supplied from a synchronizing signal generating circuit on the transmitting side; A decoding side synchronization signal generation circuit that generates various clocks necessary for decoding operation asynchronously with the decoding side synchronization signal generation circuit, and decoding of the encoded data for one video frame using the decoding clock supplied from the decoding side synchronization signal generation circuit. An image encoding and transmitting device comprising: an image decoding circuit that performs the above-described image decoding circuit; and a controller that controls input/output operations of the transmitting buffer and the receiving buffer. (2) Regarding the transmission buffer composed of first and second buffer memories that store variable length encoded data for two frames that have been subjected to image high-efficiency encoding in units of video frames in the transmission side image encoding circuit, If the transmission time of variable length encoded data for one frame is more than twice as long as the interval between side video frames, the first and second buffer memories are In addition to switching and controlling reading and writing, high-efficiency image encoding of one video frame is performed by a controller on the transmitting side, a third and a fourth controller on the receiving side, which completes the encoding of the video frame during the transmission period and puts it into a transmission waiting state. Similarly, the third and fourth buffer memories are switched and controlled in synchronization with the transmission time of variable-length encoded data of one video frame, and the previously received third or fourth buffer memory
a receiving side controller that controls the variable length encoded data to be read out in one frame period of a receiving side video frame independent from the transmitting side until reception of the next variable length encoded data is completed from one of the buffer memories of the receiving side; An image encoding and transmitting apparatus comprising an image decoding circuit that repeatedly outputs a reproduced video signal subjected to high-efficiency image decoding until receiving variable length encoded data for the next one frame. (3) If the transmission time of variable length encoded data for one frame is less than twice the video frame time on the transmitting side, the transmission buffer is a transmitting side controller that switches and controls readout; a transmitting side transmission control section that sends out a transmission frame with a header indicating an idle state to inform the receiving side of the waiting state for transmission of variable length encoded data in the transmission buffer; Identifies the transmission frame of the long coded data, and converts the variable length coded data into one
A reception transmission control unit that outputs the data to the third and fourth buffer memories on the reception side in units of frames; a receiving side controller that controls third and fourth receiving buffer memories to send an image decoding circuit in synchronization with the start of a side video frame; Variable-length encoded data is decoded with high efficiency in synchronization with the received video frame time, and video frames without received variable-length encoded data are transmitted and received by repeatedly outputting the reproduced video signal decoded in the previous video frame. 1. An image encoding and transmitting device comprising an image decoding circuit that absorbs phase jitter of independent video frame periods. (4) When the transmission time of one frame of variable-length encoded data is extremely long compared to the video frame time on the transmitting side, image encoding controls the high-efficiency encoding of the image in units of video frames on the transmitting side by dropping frames at two-frame intervals. 4. The image encoding and transmitting apparatus according to claim 3, further comprising a circuit.