JP2596357B2 - Burst data transmission method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for transmitting burst data on a communication line.

[0002]

2. Description of the Related Art A conventional burst data transmission method is described in JP-A-63-198434. FIG. 4 is a diagram showing a frame format in a conventional burst data transmission system.

In FIG. 1, a first frame synchronization signal 7
Is followed by a second synchronizing signal 8 having an error correction capability. On the receiving side, even when the first frame synchronization signal 7 is not detected due to a transmission error, the synchronization word is detected by the second synchronization signal 8 having the error correction capability.

Further, in order to remove the phase ambiguity of data generated at the time of demodulation of received data, a first synchronization signal which has a relatively long length (several + bits) without performing error correction has been used.

[0005]

However, in the conventional frame structure, since the first and second frame synchronization signals are transmitted for each frame, the ratio of the synchronization word increases and the data transmission efficiency decreases as compared with the number of data to be transmitted. There was a problem.

[0006]

According to the burst data transmission method of the present invention, in the burst transmission of framed data, on the transmitting side, data for demodulation of received data and a synchronization word for frame synchronization without error correction are provided. Means for multiplexing data to be transmitted as frame head data, and data to be transmitted and a frame synchronization synchronizing word for performing error correction, and a synchronizing word part for frame synchronization for performing error correction and data to be transmitted. Means for performing error correction coding only on the receiving side, means for detecting a synchronization word on which error correction is not performed on the receiving side, means for detecting a synchronization word on which error correction is performed, and a synchronization word on which error correction is not performed. It has means for performing error correction after detection, and means for separating data to be received from data subjected to error correction.

[0007]

Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a data frame format according to the present invention. The carrier reproduction bit 1 and the clock reproduction bit 2 are signals necessary for demodulating burst format data, and the number of bits takes a value specific to the system used. The first synchronizing word I3 is a synchronizing word which does not perform error correction for removing the phase ambiguity at the time of reception. Data 4 indicates data to be transmitted. The second synchronization word II5 is a synchronization word for performing error correction, and is 1/3 to 1/1 of the first synchronization word I3 due to the error correction function.
The synchronization word can be detected by the number of bits at the 0th place.

In the present invention, data up to the carrier reproduction bit 1, the clock reproduction bit 2, and the synchronization word I3 form a data head pattern, and only the beginning of burst data is transmitted.

FIG. 2 is a block diagram of an embodiment of a transmission data processing unit for generating a data format according to the present invention.
Data to be transmitted is input to the data input terminal 10, and the transmission data is written by being input to the transmission buffer 11. The transmission start signal 20 input from the transmission start signal input terminal 23 is
5 is input. The timing generation circuit 15 outputs a signal 17 for reading the head pattern data to the data head pattern storage unit 12. During this time, the output signals of the output signal 21 of the frame counter 14, the synchronizing word II read signal 18, and the data read signal 24 are not output. The multiplexing circuit control signal 25 of the output signal of the timing generation circuit 15 is input to the multiplexing circuit 16 to receive the head pattern data read signal 17 and then select the data 26 output from the data head pattern storage unit. Is controlled. When all the head pattern data 26 is output, the timing generation circuit 15 stops the read signal 17, then outputs a data read signal 24, and the multiplexing circuit 16 multiplexes the data. The frame counter 14 starts counting the number of bits of the data read signal 24, and outputs a frame pulse 21 each time it finishes counting the number of bits for one frame. This counting is performed until the transmission start signal 20 is in the transmission stop state. While the data read signal 24 is being output, the multiplexing control signal 25 controls the multiplexing circuit 16 to select transmission data correctly. Timing generation circuit 15
Stops the transmission data read signal 24 when the data output for one frame is completed, and outputs the synchronization word II read signal 18
Output. At the same time, the timing generation circuit 15
Controls the multiplexing circuit 16 to select the synchronization word II by the multiplexing control signal 25. When the output of the synchronization word II is completed, the reading of the transmission data is started again, and thereafter, the synchronization word II and the transmission data are read out for each frame.

The output signal of the multiplexing circuit 16 described above is sent to the error correction coding circuit 22, and the data other than the data head pattern is coded by the error correction coding control signal 29.

As described above, in the prior art, data multiplexing is a combination of a data leading pattern composed of carrier reproduced and clock reproduced bit signals and a frame pattern composed of the first and second frame synchronization signals and transmission data. Was. On the other hand, the multiplexing of data according to the present invention indicates that a data head pattern composed of a carrier reproduction / clock reproduction bit signal and a synchronization word I and a frame pattern composed of transmission data and a synchronization word II are synthesized. ing.

FIG. 3 is a block diagram showing a received data processing unit according to the present invention.

In FIG. 1, received data 31 before error correction input to a received data input terminal 30 is sent to a synchronizing pattern / received data selector 36. Here, the number of bits of the synchronization word I is N, and the number of bits of the synchronization word II is M (N).
M). However, both N and M are integers. The synchronizing word pattern / received data selector circuit 36 receives the selector control signal and outputs the output data of the synchronizing word I storage unit 32 or the synchronizing word II.
It has a function of selecting output data of the storage unit 33 and selecting data 31 before error correction or data 34 after error correction.

In this circuit, in the first receiving state, the synchronization word I
The output data of the synchronizing word I storage unit 32 and the data 31 before error correction are selected by a selector control signal 44 which is an output signal of the coincidence pulse control unit 40 in order to detect the error. The comparator 38 compares the two outputs of the selector circuit 36,
This is a circuit for determining coincidence. In this comparison means,
When detecting the synchronization word I and when detecting the synchronization word II, the allowable range of the number of errors included in the synchronization word is selected to be a larger value than the synchronization word II because the synchronization word I has not been corrected. ing. The switching of the error allowable range is performed by the selector control signal 44. When the synchronization word I is detected, the comparator 38 outputs a detection pulse 39 and inputs the detection pulse 39 to the coincidence pulse control unit 40. The coincidence pulse controller 40 controls the pulse to change the signal selected by the selector control signal 44 of the selector circuit 36. That is, the selector circuit 3
6 controls the output of the selector circuit 36 so that a total of N bits of the error-corrected received data (NM) bits and the synchronizing word IIM bits and N bits of the error-corrected data are selected. After the selector control signal 44 changes, when a detection pulse output 47 is generated, error correction is started.

In order to drive the frame counter, the coincidence pulse control section 40 delays the first pulse detected after the data head pattern by the delay required in the error correction processing, and then passes the counter drive pulse 41 unconditionally. It has a function to output. The selector circuit 36 switched by the selector control signal 44 outputs the received data (N−M) bits and the M-bit synchronization word II output from the synchronization word II storage unit 33 to the comparator 38. In the comparator 38, the data is compared with the error-corrected data 34.
(N-M) bits of the two pieces of data input to the memory cell are always identical because they are the same received data, which is the same as when the synchronization word II is compared with the received data. When the synchronizing word II is detected for each frame, a detection pulse 39 is output, and the signal and the count end pulse 43 of the frame counter are input to the coincidence pulse control unit 40. After the detection of the synchronizing word I is completed, the coincidence pulse controller 40 detects the detection pulse 3
It is confirmed that the 9 and the count end pulse 43 are coincident. If the coincidence is detected, that is, if the detection pulse 39 is output for each frame, the signal is output to the frame counter drive pulse 41 without delay.

On the other hand, if the detection pulse 39 is not at the position where the count end pulse is output, the frame counter drive pulse 41 is output at the count end pulse position and the fact that detection was not possible is stored. Conversely, if the detection pulse 39 is output at a position other than the position where the count end pulse is output, it is ignored. If the unsuccessful detection occurs consecutively K times, it is determined that the synchronizing word II has disappeared, and it is determined that the reception has been completed. The value of K is a value specific to each system and is a positive integer of 1 or more. The count end pulse 43 of the frame counter 42 is sent to the frame pulse output terminal 45 as a frame pulse, and the received data output terminal 4
The data is supplied to the data separation circuit together with the reception data 31 output to 6 and is separated into only data from the reception data including the synchronization word.

[0018]

As described above, according to the burst data transmission method of the present invention, the synchronization word indicating the head of the frame is composed of the first synchronization word at the head of the burst data and the second synchronization word after the data to be transmitted for each frame. 1/3 to 1 /
Since the synchronization word can be transmitted with the tenth bit number, the transmission efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a frame format according to the present invention.

FIG. 2 shows an embodiment of a transmission data processing unit of the present invention.

FIG. 3 shows an embodiment of a reception data processing unit of the present invention.

FIG. 4 shows a conventional frame format.

[Explanation of symbols]

 1 Carrier recovery bit 2 Clock recovery bit 3 Synchronization word I 4 Transmission data 5 Synchronization word II 6 Bit synchronization signal 7 First frame synchronization signal 8 Second frame synchronization signal 9 Transmission data 10 Transmission data input terminal 11 Transmission buffer 12 Data Start pattern storage unit 13 Synchronization word II storage unit 14 Frame counter 15 Timing generation circuit 16 Multiplexing circuit 17 Data start pattern read signal 18 Synchronization word II read signal 19 Transmission data write signal 20 Transmission start signal 21 Frame pulse 22 Data output terminal 23 Transmission start signal input terminal 24 Transmission data read signal 25 Multiplexer circuit control signal 26 Data head pattern data 27 Synchronization word II data 28 Transmission data 29 Error correction encoding control signal 30 Received data input terminal before error correction 31 Before error correction No Data 32 synchronization word I storage unit 33 synchronization word II storage unit 34 data after error correction 35 synchronization word II pattern data 36 selector circuit 37 selector output 38 comparator 39 detection pulse 40 coincidence pulse control unit 41 frame counter drive pulse 42 frame Counter 43 Count end pulse (frame pulse) 44 Selector control signal 45 Frame pulse output terminal 46 Receive data output terminal 47 Detection pulse output terminal 48 Received data input terminal after error correction 49 Selector control signal output terminal

Claims (3)

(57) [Claims] 1. A method of transmitting burst data of framed data, comprising: a data used for demodulation of a receiver, a first synchronization word for frame synchronization, and a period immediately after the burst data head. Burst data transmission, comprising: means for multiplexing a transmission signal and a frame signal composed of a second synchronization word for frame synchronization, and means for performing error correction coding only on the frame signal. Method. 2. After receiving the burst data by the multiplexing and encoding means according to claim 1, detecting the first synchronizing word, correcting the error of the received data, and executing the second synchronizing word in a frame cycle. And a means for separating received data from the error-corrected data. 3. Transmission of framed burst data
Burst data transmission equipment that performs
Data used for demodulation of receiver and frame synchronization at the beginning of data
A first synchronization word for the burst data and immediately after the beginning of the burst data
A second synchronization word for transmitting data and frame synchronization periodically
Means for multiplexing a frame signal composed of
Means for performing error correction coding only on the frame signal;
Multiplexing means and means for performing the error correction coding
And detects the first synchronizing word.
After that, error correction of the received data is performed, and the
Decoding means for detecting the second synchronization word;
Having means for separating received data from subsequent data
A burst data transmission device , characterized in that: