JP3240155B2 - Parallel data transmission method and parallel data receiving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation reference phase ambiguity elimination system and a data separation system, and more particularly to a parallel data transmission system and a parallel data reception device in a digital radio communication system or the like for performing error correction.

[0002]

SUMMARY OF THE INVENTION According to the present invention, when encoding / decoding a high-speed data stream by separating it, or when transmitting parallel data streams, unique words added to the data stream are also subjected to error correction coding and transmitted. On the receiving side, the decoder detects a unique word from the error-corrected decoded data string and synchronizes the frames. When frame synchronization is not established for a certain period of time, the decoder controls the phase ambiguity remover and the data separation circuit to determine the demodulation standard. The phase ambiguity is removed, and at the same time, the timing of data separation can be correctly taken. The circuit required for this can be realized only by adding a timer circuit having a small circuit scale to the frame synchronization circuit originally provided in the digital communication system.

[0003]

2. Description of the Related Art In a high-speed digital radio communication system or the like, parallel data is multiplexed and then transmitted as a modulated signal.
On the receiving side, a data string obtained by demodulating a received signal is often separated into a plurality of data strings by a data separation circuit.

For example, due to the limitation on the operation speed of the decoding device, one data string to be transmitted is separated into a plurality of data strings by a data separation circuit, and each data string is convolutionally coded to form two data strings. Then, these data strings are multiplexed into one data string by a data multiplexing circuit, and the carrier signal is four-phase-modulated with these data strings and transmitted. On the receiving side, the four-phase modulated signal, which is a received signal, is synchronously detected to obtain two data strings, separated into a plurality of data strings by a data separation circuit, and these data strings are corrected for errors by a Viterbi decoder. Then, the data is returned to a single data string by the data multiplexing circuit.

[0005] A demodulator on the receiving side reproduces a demodulation reference carrier signal from the input four-phase modulated signal, and performs synchronous detection using the demodulation reference carrier signal. The data separation circuit on the reception side adjusts the separation timing so as to synchronize with the data multiplexing circuit on the transmission side, and separates the data.

As is well known, a demodulation reference carrier signal reproduced from a quadrature modulation signal such as a four-phase modulation signal has a phase ambiguity of an integral multiple of 90 degrees. If this demodulation reference phase ambiguity is not removed, the data sequence output from the encoder to the modulator on the transmission side and the demodulator to the decoder on the reception side even if the data separation timing on the reception side is synchronized. (Even if there is no transmission error)
If they do not match, error correction decoding cannot be performed.

If the difference between the demodulation reference phases is 180 degrees, both data strings from the demodulator are inverted. or,
If the discrepancy is 90 degrees or 270 degrees, the order of the two data strings is reversed, and one of the data strings is inverted. Therefore, it is necessary to detect a discrepancy in the demodulation reference phase by any method and correct the discrepancy.

The need to correct the discrepancy in the demodulation reference phase is not limited to the above-described example, as long as a modulation method involving phase modulation such as a two-phase modulation method or a multilevel quadrature amplitude modulation method is used. This is a common problem regardless of the type of error correction system and modulation system.

When encoding and decoding parallel data in this way, the discrepancy in the demodulation reference phase on the receiving side is corrected, and at the same time, each decoder is connected to the corresponding encoder on the transmitting side. Must be correctly synchronized. Further, prior to code synchronization, it is necessary to correctly set the timing for data multiplexing / demultiplexing between the data multiplexing circuit on the transmitting side and the data separating circuit on the receiving side.

A first conventional method for correcting a difference between demodulation reference phases and adjusting data separation timing is a method for detecting an increase in an error occurrence rate in a decoder and correcting the difference. If the demodulation reference phase is different and the data separation timing is shifted, it is equivalent to the occurrence of an extremely large number of errors. It is determined that the phases are different or the data separation timing is shifted, and the data sequence from the demodulator is logically operated so as to correct the difference and adjust the data separation timing.

The second conventional method of correcting the difference in the demodulation reference phase and adjusting the data separation timing transmits the unique word without performing error correction coding, transmits the unique word, detects the unique word on the receiving side, and detects the difference. And the timing of data separation is adjusted. In a digital communication system, generally, a data sequence to be transmitted is framed, and a unique word for frame synchronization is added for transmission. On the receiving side, the unique word is detected by a frame synchronization circuit to achieve frame synchronization.

In the second conventional method, a unique word is transmitted without error correction coding. Therefore, on the receiving side, a unique word can be detected from the data sequence output from the demodulator, even though the sequence of the data sequence is reversed or the data sequence is reversed. When the unique word is detected, it is possible to estimate the discrepancy of the demodulation reference phase from the information on the reversal of the column order of the data sequence and the inversion of the data sequence.Based on this estimation, the data sequence from the demodulator is logically operated and Correct and adjust the timing of data separation.

A third conventional method for correcting a difference in demodulation reference phase and adjusting data separation timing is to perform error correction encoding of a unique word, transmit the unique word, perform error correction decoding on the receiving side, and then perform unique word correction. This is a method for detecting discrepancies and correcting discrepancies.

In the third conventional method, a unique word is transmitted after being subjected to error correction coding. Therefore, on the receiving side, it is possible to detect a unique word by correcting an error in the data string output from the demodulator and logically operating the data string from the demodulator to correct any discrepancy in the demodulation reference phase. At the same time, the timing of data separation is adjusted.

[0015]

The first conventional method of correcting the above-mentioned difference in the demodulation reference phase and adjusting the timing of data separation is to count the occurrence of error correction in the decoder. A circuit for comparing the value with the value is required, and a protection circuit for performing forward protection and backward protection of the operation of logically operating the data string from the demodulator based on the comparison result of the circuit is also required. There are disadvantages.

Also, in the second conventional example, the unique word detection is inherently complicated, and the unique word is transmitted without error correction coding. You need to detect it,
Therefore, the circuit for detecting unique words becomes complicated,
There is still a disadvantage that the circuit scale becomes large.

The third conventional example also needs to process error correction decoding and unique word detection at high speed.
Due to the limitation of the operation speed of the decoding device, there is a disadvantage that error correction decoding cannot be performed if the transmission speed is high.

Accordingly, an object of the present invention is to provide a demodulation reference phase ambiguity elimination method capable of removing ambiguity of a demodulation reference phase with a small circuit scale even during data transmission at a high transmission rate, and a method for correctly setting the timing of data separation. In particular, it is an object of the present invention to provide a parallel data transmission system and a parallel data receiving device in a digital radio communication system or the like for performing error correction.

[0019]

According to the parallel data transmission method of the present invention, an encoder for error-correcting and encoding a data sequence including a unique word on the transmitting side and a parallel data sequence including the data sequence are provided on the transmission side. A data multiplexing circuit for multiplexing,
A modulator for outputting a modulated signal modulated with a data sequence from the data multiplexing circuit using at least a modulation method involving phase modulation, and a receiving side synchronously detects the modulated signal transmitted from the transmitting side. A demodulator that demodulates and demodulates; a phase ambiguity remover that logically operates and outputs a data sequence from the demodulator when a control signal is input to remove a difference in demodulation reference phase of the demodulator; When the control signal is input to synchronize the column separation timing, the data separation circuit that adjusts the data column separation timing from the phase ambiguity remover and separates the data,
A decoder for performing error correction decoding of the data stream from the data separation circuit, and detecting the unique word contained in the data stream from the decoder to obtain frame synchronization and performing predetermined time-frame synchronization when the predetermined time-frame synchronization is not established. A frame synchronization circuit for outputting a control signal.

The parallel data receiving apparatus according to the present invention provides
Side performs error correction encoding of a data string containing unique words
Parallel data including the error-correction-encoded data string.
Multiplex the data sequence and use at least a modulation method with phase modulation.
To receive a modulated signal modulated by the multiplexed data sequence.
A receiving device for receiving the modulated signal.
A demodulator for performing period detection and demodulation, and a demodulation reference position of the demodulator
When a control signal is input to remove the phase difference,
Phase ambiguity that outputs the data stream from the demodulator by logical operation
Synchronize the timing of data string separation with the data remover
When the control signal is input, the phase ambiguity remover
The timing of the separation of the data string from the
A data separation circuit to separate the data from the data separation circuit.
A decoder for performing error correction decoding of the data sequence,
Detects the unique word contained in the data string and
Time synchronization is not established.
A frame synchronization circuit that outputs the control signal when the
It is characterized by having. Here, the frame synchronization circuit includes a unique word detection circuit that outputs a detection signal each time the same bit pattern as the unique word is detected in the data string from the decoder, and the detection from the unique word detection circuit. A protection circuit that outputs synchronization information indicating whether frame synchronization is established based on the input state of the signal, and when the detection signal is input from the unique word detection circuit, an initial value is set from the demodulator. And a frame synchronization counter that outputs a frame pulse by counting clocks, and is always reset while frame synchronization is established based on the synchronization information from the protection circuit, while the frame synchronization is not established. The frame pulse from the frame synchronization counter is counted, and when the count value reaches a predetermined value, the control pulse And a control signal generating circuit that outputs the control signal to the phase ambiguity remover or the data separation circuit when the control pulse signal is input from the timer counter. Is preferred.

[0021]

According to the present invention, a unique word added to a data string is also error-correction-encoded and transmitted, and a decoder detects a unique word from the error-corrected data string on the receiving side, synchronizes the frame, and establishes frame synchronization. When the frame synchronization is not established, the phase ambiguity remover and the data separation circuit are controlled to remove the ambiguity of the demodulation reference phase, and at the same time, correct the data separation timing.

[0022]

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 and 2 are block diagrams showing one embodiment of the present invention. In this embodiment, one data string to be transmitted is separated into three data strings by a data separation circuit, and each data string is convolutionally coded and consequently encoded into two data strings by the limitation of the operation speed of the decoding device. And multiplexing these data strings into one data string by a data multiplexing circuit.

In this embodiment, the transmitting side 1 includes a data separation circuit 2 for separating a data string to be transmitted, a unique word adder 3 for adding a unique word for frame synchronization, and an output of the unique word adder 3. An encoder 4 that convolutionally encodes the data string to which the unique word is added and outputs the data string as two columns, and an encoding that convolutionally encodes the data string without adding the unique word and outputs the two data strings. Units 5, 6 and encoders 4, 5, 6
And the data multiplexing circuits 7 and 8 for multiplexing the two data strings output by
The modulator 9 includes a modulator 9 that outputs a modulation signal that has been subjected to four-phase modulation with a data sequence of a column, and a transmitter 10 that wirelessly transmits the modulation signal from the modulator 9.

The receiving side 11 receives a radio wave from the transmitting side 1 and outputs a modulated signal;
A demodulator 13 that synchronously detects and demodulates the modulated signal from the demodulator to output a two-column data sequence and outputs a two-column data sequence from the demodulator 13 to perform a logical operation on the demodulation reference phase in the demodulator 13 A phase ambiguity remover 14 for correction;
Data separation circuits 15, 16 for adjusting the timing of separation of the two data strings from the phase ambiguity remover 14, and error correction of the two data strings from the data separation circuits 15, 16 by the Viterbi algorithm. The decoder 17 for decoding and the decoder 1 corresponding to the encoders 5 and 6 of the transmitting side 1
8, 19, a unique word remover 20 for removing a unique word from the data string decoded by the decoder 17 in accordance with a timing signal given from the frame synchronization circuit 21 and outputting the same, and a data string output by the decoder 17 When a unique word is detected, frame synchronization is performed, and when frame synchronization is not established for a certain period of time, a control signal is output to operate the phase ambiguity remover 14 and the data separation circuit 15,
16 and a data multiplexing circuit 22 for multiplexing the data string output from the unique word remover 20 and the data strings output from the decoders 18 and 19.

Since the input data string of the encoder 4 includes the unique word added by the unique word adder 3, the unique word is also subjected to error correction coding, and the transmission error is corrected by the decoder 17. .

The modulator 9 generates a carrier signal in the intermediate frequency band, and divides the carrier signal into two signals from the data multiplexing circuits 7 and 8.
Four-phase modulation is performed on the data sequence of the column, and the modulated signal is output. The transmitter 10 frequency-converts the modulated signal in the intermediate frequency band from the modulator 9 into a microwave band, amplifies the signal, and transmits the signal from an antenna (not shown).

The receiver 12 converts the frequency of a signal received from an antenna (not shown), amplifies the signal, and outputs it as a modulated signal in the intermediate frequency band.

The demodulator 13 reproduces a demodulation reference carrier signal in synchronization with the modulation signal from the receiver 12 by a carrier wave, and performs quadrature detection of the modulation signal using the demodulation reference carrier signal to obtain two baseband signals. AD baseband signal
The data is converted into two data strings.

As described above, when encoding and decoding such continuous data, in each decoder on the receiving side, the code synchronization between the encoder and the corresponding encoder on the transmitting side is correctly performed. Must be taken. Further, prior to code synchronization, it is necessary to correctly set the timing for data multiplexing / demultiplexing between the data multiplexing circuit on the transmitting side and the data separating circuit on the receiving side. Further, since the reproduced demodulation reference carrier signal has a phase ambiguity of an integral multiple of 90 degrees, the phase ambiguity must be removed.

Here, the data multiplexing circuits 7 and 8 of the transmitting side 1
It is assumed that the timing for data multiplexing / separation between the receiver and the data separation circuits 15 and 16 on the receiving side 11 is properly set. The carrier signal in the modulator 9 and the demodulation reference carrier signal in the demodulator 13 may be different in phase by an integral multiple of 90 degrees. There is no discrepancy in the demodulation reference phase, and the phase ambiguity remover 14
Assuming that the data sequence of the column is output as it is, the two data sequences input to the decoder 17 are, except for the transmission error,
It matches the two data strings output by the encoder 4.

Therefore, the data string output from the decoder 17 coincides with the data string output from the unique word adder 3, except for a very small number of transmission errors that could not be corrected, and is added to this data string. Errors in existing unique words are negligible. Further, the data separating circuits 15 and 16 separate the data into three columns, thereby reducing the operating speed of the decoder 17 to 1/3.

As will be described in detail later, the frame synchronization circuit 21 detects a unique word included in the data string from the decoder 17 and synchronizes the frames, and the phase ambiguity remover 14
Output a control signal to

On the other hand, the unique word remover 20 removes a unique word from the data string from the decoder 17 in accordance with the timing signal from the frame synchronization circuit 21 and outputs it as a transmitted data string.

The phase ambiguity remover 14 is a first operation mode in which the two data strings from the demodulator 13 are directly output, and the phase of the demodulated reference carrier signal from the demodulator 13 is 90.
, 180, and 270 degrees, and has four operation modes of a second, a third, and a fourth operation mode in which a logical operation equivalent to a change of 180 degrees is performed on the two data strings from the demodulator 13 and output. Unless the control signal is input from the frame synchronization circuit 21, the current operation mode is maintained, and when the control signal is input, the operation is shifted to the operation mode in the next order of the current operation mode.

The phase ambiguity remover 14 takes the first operation mode and outputs the two data strings from the demodulator 13 as they are. If there is a discrepancy in the demodulation reference phase, the data is input to the decoder 17. Since the column data sequence is reversed in column order from the two data sequences output from the encoder 4 or the logical value (polarity) of the data sequence is reversed, the decoder 17 cannot decode. And output a meaningless data string. As a result, the frame synchronization circuit 21 cannot detect a unique word from the input data string, and cannot achieve frame synchronization.

When this state continues for a predetermined time, the frame synchronization circuit 21 outputs a control signal. With this control signal, the operation mode of the phase ambiguity remover 14 shifts to the second operation mode. As a result, the two data strings from the phase ambiguity remover 14 to the decoder 17 match the two data strings output by the encoder 4.

In other words, when the discrepancy of the demodulation reference phase is corrected, the decoder 13 performs normal decoding and outputs the same data string as that output by the unique word adder 3 to the frame synchronization circuit 21. Frame synchronization circuit 21
Frame synchronization can be achieved.

Even if the phase ambiguity remover 14 enters the second operation mode, if the difference between the demodulation reference phases cannot be corrected, the frame synchronization circuit 21 cannot perform frame synchronization. Output. As a result, the operation mode of the phase ambiguity remover 14 shifts to the third operation mode. If the difference between the demodulation reference phases is still not corrected, the frame synchronization circuit 21 further outputs a control signal, and the operation mode of the phase ambiguity remover 14 becomes the fourth operation mode.

This time, the difference in the demodulation reference phase is always corrected, and the frame synchronization is performed by the frame synchronization circuit 21.
Regardless of the value of the difference between the demodulation reference phases and the initial state of the operation mode of the phase ambiguity remover 14, if the control signal is output from the frame synchronization circuit 21 up to three times in the same manner, the demodulation reference phase Can always be removed.

Further, the data separating circuit 15 of the receiving side 11,
If the timing of step 16 is not correct, the error correction of the decoder cannot be performed. Therefore, the data separation can always be performed correctly by setting the data separation timing by the control signal from the frame synchronization circuit 21 similar to that described above. . Further, by detecting the frame synchronization, the code synchronization can also be correctly performed at the same time.

Phase ambiguity remover 14 and data separation circuit 1
The control signals to 5 and 16 may be output first,
For example, the control signal is output to the phase ambiguity remover 14 three times, and if the frame synchronization is still not achieved, the control signal is output to the data separation circuits 15 and 16 once, for example. These four control signal output operations are repeated until frame synchronization is achieved.

FIG. 3 is a block diagram showing a detailed configuration of the frame synchronization circuit 21. With reference to FIG. 3, the frame synchronization circuit 21 will be further described.

The frame synchronization circuit 21 shown in FIG.
A unique word detection circuit 31 which comprises a shift register 32 to which the data string from the input 7 is inputted, and an AND circuit 33 to which the output of each stage of the shift register 32 is inputted, and which outputs a detection signal every time a unique word is detected; A protection circuit 34 that outputs synchronization information indicating whether or not frame synchronization is established based on the input state of the detection signal from the detection circuit 31, and an initial value is set and demodulated when a detection signal is input from the unique word detection circuit 31 A frame synchronization counter 35 that outputs a frame pulse by counting a clock from the unit 13, an AND circuit 36 that receives synchronization information from the protection circuit 34 and a frame pulse from the frame synchronization counter 35 as inputs, and a protection circuit 34. Is reset by the synchronization information, and the input from the AND circuit 36 is counted and controlled. A timer counter 37 that outputs a pulse signal and is reset, and a control signal generation circuit that outputs a control signal to the data separation circuits 15 and 16 or the phase ambiguity remover 14 when a control pulse signal is input from the timer counter 37. 39, and a timing generator 38 that generates a timing signal based on the synchronization information from the protection circuit 34 and the frame pulse from the frame synchronization counter 35 and outputs the timing signal to the unique word remover 20.

The number of stages of the shift register 32 is the same as the length (bit number) of the unique word, and the output of each stage becomes "1" when the entire unique word is stored in each stage. I have. In FIG. 3, the pattern of the unique word is “1”, “0”,..., “1”, “0”,
The case where it is “1” is exemplified.

When the entire unique word included in the data string from the decoder 17 is stored in the shift register 32, A
All inputs of the ND circuit 33 become “1”, and the AND circuit 33
Outputs “1”. Since the data string from the decoder 17 has been error-corrected and errors in the unique word are extremely small, the unique word can be detected by the unique word detection circuit 31 having such a simple configuration.

In a state where frame synchronization is established, "1" of one clock width, which is a detection signal, from the unique word detector 31 continues to be output in a frame cycle.

If the detection signal "1" is not input from the unique word detection circuit 31 for at least one continuous m1 frame (for example, 4 frames), the protection circuit 34 determines that frame synchronization is lost. (Forward protection established), the output synchronization information is set to “1”. If a detection signal “1” is input for each frame over m2 consecutive frames (for example, three frames), it is determined that frame synchronization has been established (rear protection has been established), and the synchronization information is set to “0”. .

The frame synchronization counter 35 is provided for the demodulator 13
Is input to a terminal CK and counted, and a pulse is output from a terminal CR every time the counted value reaches the number of clocks of one frame. Therefore, as long as the clock is normally input from the demodulator 13, the frame synchronization counter 35 outputs a pulse at a frame cycle. Also, the frame synchronization counter 35 sets the count value to a predetermined initial value when "1" is input to the terminal L from the unique word detection circuit 31, so that the output pulse is at a predetermined position of the frame, for example, at the beginning of the frame. The frame pulse indicates the position.

The AND circuit 36 outputs the frame pulse from the frame synchronization counter 35 to the timer counter 37 only when the synchronization information from the protection circuit 34 is "1", in other words, only when the frame synchronization is lost. I do.

The timer counter 37 is reset while the synchronization information of “0” is input to the terminal R from the protection circuit 34, in other words, while the frame synchronization is established, and the frame synchronization is lost. While the terminal CK is
The pulses input from the circuit 36 are counted, and a control pulse signal is output from the terminal CR to the control signal generation circuit 39 every time the counted value reaches a constant value m3.

The control signal generation circuit 39 selects and outputs a control signal when a control pulse signal is input. First, the control signal is output three times to the phase ambiguity remover 14, and the fourth control signal is output to the data separation circuit 16. These four control signal output operations are repeated until frame synchronization is achieved.

As described above, the embodiment shown in FIGS. 1 and 2 uses the frame synchronization circuit 21 shown in FIG.
The frame synchronization is performed by detecting the unique word included in the data string from the frame synchronization, and when the frame synchronization is not achieved and the forward protection is established by the protection circuit 34, a control signal is output from the frame synchronization circuit 21 every m3 frame periods. By changing the operation mode of the phase ambiguity remover 14 and the data separation timing of the data separation circuits 15 and 16 in a trial and error manner by the signal, the difference between the demodulation reference phases, the data separation timing and the code synchronization are corrected.

The timing generator 38 generates a timing signal indicating the timing of a specific position of a frame when the frame is synchronized. This timing signal is used by the unique word remover 20 for removing a unique word.

In the frame synchronization circuit 21, the unique word detection circuit 31, the protection circuit 34, and the frame synchronization counter 35 are circuits that are originally necessary for a digital communication system for frame synchronization. By adding a small-scale circuit such as the timer counter 37 and the control signal generation circuit 39, the demodulation reference phase ambiguity can be removed, and the timing of data separation and the code synchronization can be matched.

The embodiment has been described above in which data is separated, convolutional coding and Viterbi decoding are used as error correction methods, and four-phase modulation is used as a modulation method.
In other cases, a modulation method with ambiguity in the demodulation reference phase is used, and an error correction method in which decoding is disabled due to a difference in the demodulation reference phase is used, and an error correction method in which decoding is disabled at a data separation timing. The same effect can be obtained by applying the present invention also when using.

Further, the operating speed of the decoder 17 can be reduced by increasing the number of data separations. Thereby, regardless of the operation speed limitation of the decoder 17,
High-speed data transmission is possible.

The data separation circuit 2, the encoders 5, 6, the decoders 20 and 21, and the data multiplexing circuit 22 can be used not only for transmitting high-speed one-row data but also for transmitting parallel data. The same effect can be obtained even without.

[0059]

As described above , according to the present invention , when a high-speed data stream is separated and encoded / decoded, or when a parallel data stream is transmitted / received , it is added to the data stream. unique word is also transmitted <br/> by error correction coding, on the receiving side, the decoder takes a frame synchronization by detecting the unique word from the error correction decoded data sequence, the phase when the fixed time frame synchronization is not established The ambiguity remover and the data separation circuit are controlled by trial and error to remove the ambiguity of the demodulation reference phase, and at the same time , correct the data separation timing .

The circuit required for this can be realized only by adding a timer circuit having a small circuit scale to the frame synchronization circuit originally provided in the digital communication system.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a transmitting side according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a receiving side according to an embodiment of the present invention.

FIG. 3 is a block diagram of a frame synchronization circuit 21 in FIG. 2;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transmission side 2 Data separation circuit 3 Unique word adder 4,5,6 Encoder 7,8 Data multiplexing circuit 9 Modulator 10 Transmitter 11 Receiver 12 Receiver 13 Demodulator 14 Phase ambiguity remover 15,16 Data separation circuit 17, 18, 19 Decoder 20 Unique word remover 21 Frame synchronization circuit 22 Data multiplexing circuit 31 Unique word detection circuit 32 Shift register 33, 36 AND circuit 34 Protection circuit 35 Frame synchronization counter 37 Timer counter 38 Timing generator 39 Control signal generation circuit

Claims (3)

(57) [Claims] An encoder for error correction coding a data string including a unique word on a transmission side, a data multiplexing circuit for multiplexing parallel data strings including the data string, and at least modulation involving phase modulation A modulator for outputting a modulated signal modulated with a data sequence from the data multiplexing circuit using a system, and a demodulator for synchronously detecting and demodulating the modulated signal transmitted from the transmitting side at a receiving side. A phase ambiguity remover that logically operates and outputs a data sequence from the demodulator when a control signal is input to remove a difference in demodulation reference phase of the demodulator; and A data separation circuit that adjusts the timing of separation of a data string from the phase ambiguity remover and separates data when the control signal is input for synchronization; A decoder that performs error correction decoding of the data stream from the demultiplexing circuit, and detects the unique word included in the data stream from the decoder, performs frame synchronization, and sets the control signal when predetermined time frame synchronization is not established. And a frame synchronizing circuit for outputting the same. 2. A data sequence including a unique word is error-correction-coded on a transmission side, a parallel data sequence including the error-correction-coded data sequence is multiplexed, and the multiplexing is performed using at least a modulation method involving phase modulation. A receiving device for receiving a modulated signal modulated with a data sequence that has been converted, comprising: a demodulator that synchronously detects and demodulates the input modulated signal; and a control signal that removes a difference in a demodulation reference phase of the demodulator. Is input, a phase ambiguity remover that performs a logical operation on the data sequence from the demodulator and outputs the result, and the phase ambiguity remover when the control signal is input to synchronize the timing of separating the data sequence. A data separation circuit that adjusts the timing of separation of a data string from the data stream to separate data; a decoder that performs error correction decoding on the data string from the data separation circuit; and Parallel data receiving apparatus characterized by comprising a frame synchronization circuit in which the unique word detected time frame synchronization predetermined taking frame synchronization by the included in the data string outputs said control signal when no established. 3. The unique word detection circuit according to claim 2, wherein the frame synchronization circuit outputs a detection signal each time the same bit pattern as the unique word is detected in the data string from the decoder. A protection circuit that outputs synchronization information indicating whether or not frame synchronization has been established based on the input state of the detection signal from the word detection circuit, and an initial value when the detection signal is input from the unique word detection circuit. A frame synchronization counter that outputs a frame pulse by counting a clock from the demodulator that is set, and is always reset while frame synchronization is established based on the synchronization information from the protection circuit, and frame synchronization is established. While not, the frame pulse from the frame synchronization counter is counted and the count value is predetermined. A timer counter that outputs a control pulse signal when reset to a value and is reset, and a control signal that outputs the control signal to the phase ambiguity remover or the data separation circuit when the control pulse signal is input from the timer counter. A parallel data receiving device comprising a generating circuit.