KR0134338B1 - Detection method and apparatus of synchronizing signal in a digital transmission system - Google Patents

Abstract

The present invention relates to a synchronous detection apparatus of a digital transmission system which can reduce the time required for synchronous detection by preventing the synchronous phase from being affected by intermittent errors when a synchronization is detected at the receiving side of the digital transmission system. will be. The present invention includes a continuous error signal determining unit that determines whether the set number of synchronization signals has been continuously generated by delaying the synchronization signals output from the grid decoding unit, and thus, only when the synchronization signals are continuously generated. By enabling the synchronization detector, the synchronization phase of the input data is slid to move during deinterleaving.

Description

Synchronous Detection Method of Digital Transmission System and Its Apparatus

1 is a block diagram of a conventional digital receiving apparatus combining a lattice code modulation technique and a deinterleaver.

2 is a block diagram of a digital receiver of the present invention.

FIG. 3 is a detailed circuit diagram of the continuous error signal determining unit in FIG.

4 is a graph showing the relationship between the number of successive desynchronization signals and the deinterleaver operation state, where (a) is the prior art and (b) is the case of the present invention.

* Description of the symbols for the main parts of the drawings *

10,20: deinterleaver, 30: grid decoding unit,

40,60: synchronization detection unit, 50: block deinterleaver,

70: RS decoding unit, 80: continuous error signal determining unit,

DL ₁ -DL _n1 : Delay element, AND1: And gate

The present invention relates to a method and apparatus for detecting synchronization at a receiving side of a digital transmission system. In particular, in case of an error occurring intermittently, the phase of the synchronization signal is not affected and only a deviation signal due to continuous error is detected. The present invention relates to a synchronization detection method and an apparatus for a digital transmission system for providing a stable synchronization signal. In general, digital signal processing and transmission technology has been developed to use digital modulation for transmission of high-definition television signals as well as communication systems and communication networks in the field of data communication and transmission such as digital modem and satellite communication. This digital transmission method is capable of delivering digital data reliably at a high speed, and has a merit that the transmission power is lower than that of the analog transmission method. However, an error in transmission data is caused by the noise imposed on the channel during transmission. Has a disadvantage that can have a fatal effect on the data transmission system. In order to solve such drawbacks, conventional digital transmission systems add an error correction code and introduce a technique called Trellis Coded Modulation. Grid code modulation is a modulation technique and an error correction coding. ), Which allows for significantly higher power gain than without being coded without increasing bandwidth.

FIG. 1 shows an example of a conventional digital receiving apparatus incorporating a deinterleaver as a means for improving the lattice code modulation technique and error correction efficiency. As shown in the figure, the first and second deinterleaver 10 for performing reinterleaving corresponding to the interleaving of the transmitting apparatus on the data I and Q input through the demodulator and rearranging them to the data before being interleaved. 20 performs decoding corresponding to the encoding of the transmitting apparatus on the output data I 'and Q' of the first and second deinterleavers 10 and 20, and determines whether the data to be decoded are synchronized. It is connected to the grid decoding unit 30. The grid decoding unit 30 outputs a control signal for adjusting the deinterleaving synchronization to the first and second deinterleavers 10 and 20 whenever a synchronization departure signal is input from the grid decoding unit 30. The synchronous detection unit 40 is connected to a block deinterleaver 50 that receives the decoded data from the grid decoding unit 30 and performs deinterleaving in units of blocks corresponding to block interleaving of the transmission apparatus. In addition, the second synchronous detection unit 60 which operates according to the synchronization signal and the synchronous departure signal output from the grid decoding unit 30 to detect the synchronization of the block data deinterleaved by the block deinterleaver 50 is the second synchronous detection unit ( RS decoding unit 70 that performs decoding corresponding to Reed-Solomon (RS) encoding of the transmitting apparatus on the block data output from the block deinterleaver 50 in accordance with the block synchronization signal outputted from (60). Is connected to. The data (I, Q) input to the receiving apparatus configured as described above are data demodulated by a demodulator, the first data (I) is the first deinterleaver 10, and the second data (Q) is the second deinterleaver. Each is applied to (20).

The first and second deinterleavers 10 and 20 receive the data IQ and deinterleave the array of data reversed by interleaving in the transmitter again to deinterleave the grid decoding unit 30 in order of data before being interleaved. Will output

The reason for the interleaving in the transmitting apparatus and the deinterleaving in the receiving apparatus is to improve the error correction capability by distributing a burst error occurring in a dense manner in a random form.

The grid decoding unit 30 decodes the input data I 'and Q' and outputs the decoded data to the block deinterleaver 50. At this time, the grid decoding unit 30 determines whether the data of the grid decoded are synchronized. This synchronous discrimination method uses a well-known Viterbi Algorithm, which repeatedly selects a path having the smallest Hamming distance among the paths input to each state in the grid diagram. In general, find a path with a minimum hamming distance.

Then, if the cumulative distance of the found path is larger than the predetermined reference value, it recognizes that the input bits are out of sync due to noise on the channel and generates a predetermined deviation signal. Generate. The reference value is determined by the system designer. The desynchronization signal output from the grid decoding unit 30 is applied to the first synchronization detector 40 and the second synchronization detector 60.

The first synchronous detection unit 40 outputs a predetermined control signal to the first and second deinterleavers 10 and 20 whenever a synchronization departure signal is input.

Here, the control signal is a signal for adjusting the deinterleaving synchronization, and each time the first and second deinterleavers 10 and 20 receive the control signal, the control signal slides, that is, stored in the deinterleaver. Deinterleaving is performed by moving data by 1 bit.

Then, the deinterleaved data I 'and Q' are applied to the grid decoder 30 according to the phase shifted synchronization, and the grid decoder 30 decodes the data again to determine whether the synchronization is correct. .

By repeatedly performing such a series of synchronization detection processes, the grid decoding unit 30 finds synchronization data from the input data. When the synchronization is detected, the grid decoding unit 30 outputs the decoded data to the block deinterleaver 50, and the block deinterleaver 50 again interleaves the data interleaved block by block in the modulation unit of the transmitting apparatus. Deinterleave and reorder the original data.

The second synchronization detector 60 detects the synchronization of the block data deinterleaved by the block deinterleaver 50. In this case, the second synchronization detector 60 detects the synchronization departure signal and the synchronization signal output from the grid decoding unit 30. FIG. Is disabled by the desynchronization signal.

The block data output from the block deinterleaver 50 is applied to the RS decoding unit 70, and the RS decoding unit 70 decodes the RS-coded data in order to enhance the error correction function of the transmission data in the transmitter. .

At this time, the RS decoding unit 70 decodes the block data in accordance with the block synchronization signal supplied from the second synchronization detector 60 and outputs the decoded block data.

However, this method generates a predetermined control signal every time a sync break signal occurs in the grid decoding unit and slides the sync phase of input data during deinterleaving. Since the processing time for performing the iterative process for detecting the lengthens, there is a problem that the data properly received therebetween cannot deinterleave.

The present invention is to solve the conventional problems as described above, the object of the present invention is to determine whether the number of the de-synchronization signal set by the designer is continuously generated by ignoring the discontinuous de-synchronization signal is a continuous number of synchronization The present invention provides a synchronous detection method and apparatus for a digital transmission system having a hysteresis function to reduce the time required for synchronous detection by sliding a phase only with respect to a deviation signal.

A feature of the present invention for achieving the above object is a synchronous detection device of a digital transmission system that receives encoded data and decodes it to a state before it is encoded, wherein the received digital data is received in accordance with a synchronous control signal applied from the synchronous detection unit. A deinterleaving unit for deinterleaving the lattice decoding unit for performing grid lattice decoding on the data applied from the deinterleaving unit and determining whether the data is synchronized, and generating a synchronization signal or a desynchronization signal; A continuous error signal determining unit for applying the enable signal to the synchronous detection when the escape signals are applied by a predetermined number; And a synchronization detector for applying a synchronization control signal to the deinterleaving unit when an enable signal from the continuous error signal determination unit is applied.

In still another aspect of the present invention, there is provided a synchronous detection method of a digital transmission system that receives encoded data and decodes it to a state before it is encoded, the method comprising: deinterleaving received digital data; whether synchronization is performed from the deinterleaved data. Determining, and generating a departure signal when the synchronization is not correct; And sliding the synchronization phase of data when the synchronization departure signal occurs continuously by a predetermined number.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 4 as follows.

2 is a block diagram of a digital receiver of the present invention combining a lattice code modulation technique and a deinterleaver.

As shown in the figure, the first and second deinterleavers, which perform deinterleaving corresponding to interleaving of the transmitter for data I and Q input through the demodulator, are redistributed to data before deinterleaving ( 10) 20 performs decoding corresponding to the encoding of the transmitting apparatus with respect to the output data I ', Q' of the first and second deinterleavers 10 and 20, and checks whether the data to be decoded is in sync. It is connected to the grid decoding unit 30 for discriminating.

In addition, the first synchronous detection unit 40 outputs a control signal for adjusting the deinterleaving synchronization to the first and second deinterleavers 10 and 20 only when a continuous deviating signal is input. 2 is connected to the deinterleaver 10, 20.

The block deinterleaver 50, which receives the decoded data from the grid decoding unit 30 and performs deinterleaving in units of blocks corresponding to block interleaving of the transmitting apparatus, according to the synchronization signal output from the grid encoding unit 30 The block deinterleaver 50 operates in accordance with the second synchronization detector 60 for detecting synchronization of the block data deinterleaved by the block deinterleaver 50 and the block synchronization signal output from the second synchronization detector 60. It is connected to an RS decoding unit 70 for decoding the output block data corresponding to RS coding of the transmitting apparatus.

Here, the configuration as described above is the same as that of the conventional receiver.

According to the present invention, the output unit price of the grid decoder 30 is delayed between the input terminals of the first synchronization detector 40 and the second synchronization detector 60 to delay the synchronization departure signal output from the grid decoder 30. The continuous error signal determination unit 80 for outputting a signal for enabling the first synchronization detection unit 40 only when the synchronization departure signal is input is configured.

The operation of the other blocks except for the continuous error signal determining unit 80 in the receiving device configured as described above is the same as the above description of the related art, and thus will be described schematically. When the data I and Q through the demodulator are input, the first and second deinterleavers 10 and 20 perform deinterleaving with a decoding depth, and the data is ordered in the data order before being interleaved. The rearrangement is performed to the lattice decoding unit 30. In this case, the greater the depth of the deinterleaving, the greater the effect, but since the processing time takes longer during grid decoding, the average relationship is maintained. The grid decoding unit 30 decodes the input data I 'and Q' and outputs the decoded data to the block deinterleaver 50. At this time, it is determined whether the data of the grid-decoded data is synchronized.

If the synchronization is not correct when deinterleaving, the data is further interleaved with an unwanted data bitstream.If the data is not synchronized due to noise on the channel, the synchronization output signal is output. If the synchronization is not correct, the synchronization signal is output. If correct, a synchronous signal is output. The desynchronization signal output from the trellis encoder 30 is applied to the continuous error signal determination unit 80, and in the continuous error signal determination unit 80, the synchronization deviation signal generated discontinuously is ignored and continuously generated synchronization. Only the departure signal is detected to output a signal for enabling or disabling the first synchronization detector 40 and the second synchronization detector 60. 3 is a circuit diagram showing a detailed configuration example of the continuous error signal determination unit 80. The continuous error signal determining unit 80 is connected in series to a plurality of delay elements DL ₁ -DL _n-1 and the lattice decoding unit 30 which continuously delays the synchronous deviation signal input from the lattice decoding unit 30. Outputting a signal for controlling the first and second synchronization detectors 40 and 60 by performing a logical AND on the desynchronization signal inputted from the decoupling signal and the delayed desynchronization signals output from the delay elements DL ₁ -DL _n-1 . It consists of an AND gate AND1.

When the synchronization error signal is input, the continuous error signal determining unit 80 configured as described above inputs the AND gate AND1 to the delay element, and repeats the above process every time the synchronization departure signal is inputted. To be input to the gate AND1.

Then, the AND gate and1 output a signal for enabling the first synchronous detection unit 40 only when the number of the synchronous departure signals that are one greater than the number of the serially connected delay elements DL1 -DLn-1 is continuously input. do. When the enable signal is input from the continuous error signal determining unit 80, the first synchronous detection unit 40 outputs a control signal for adjusting the deinterleaving synchronization to the first and second deinterleavers 10, 20. .

Each time the first and second deinterleavers 10 and 20 receive the control signal, the first and second deinterleavers 10 and 20 perform a deinterleaving by sliding the synchronization phase of the input data I and Q.

Then, the deinterleaved data I 'and Q' are applied to the grid decoding unit 30 according to the phase shifted synchronization, and the grid decoding unit 30 performs grid lattice decoding on the data to determine whether the synchronization is correct.

When the synchronization is detected, the grid decoding unit 30 outputs the decoded data to the block deinterleaver 50, and the block deinterleaver 50 deinterleaves the input data in block units to the RS decoding unit 70. Output

The second synchronization detector 60 detects the synchronization of the block data deinterleaved by the block deinterleaver 50. When the control signal is input from the continuous error signal determination unit 80, the second synchronization detector 60 is disabled by this signal.

The RS decoding unit 70 decodes and outputs the block data input from the block deinterleaver 50 in accordance with the block synchronization signal supplied from the second synchronous detection unit 60.

4 is a graph showing the relationship between the number of continuous de-synchronization signals and the operating state of the deinterleaver, (a) according to the prior art, and (b) according to the present invention.

As shown in the related art, in the conventional art, the synchronization of the input data is performed by sliding the phase of the input data every time a desynchronization signal is generated during deinterleaving, whereas in the present invention, the deinterleaver only generates n desynchronization signals continuously. In order to synchronize, the phase is moved by sliding the phase.

For example, some bitstreams A1 to A10 generate discontinuous errors during channel transmission, resulting in A1, A2, A3,... Assume that an error occurs in the bitstream A4 at this time, deinterleaving in the order of A10. Conventionally, a deviation signal is generated while lattice decoding A4, and according to this signal, the first synchronization detector outputs a control signal to the deinterleaver and slides the phase by the decoding depth.

However, while the error-free bitstreams A5, A6, A7, A8, A9, and A10 are error-free bitstreams, they cannot be decoded properly by the block deinterleaver due to the influence of A4.

According to the present invention, even if a deviation signal is generated while lattice decoding A4, the continuous error signal determination unit ignores this signal and does not slide the phase, thereby performing block deinterleaving. As described above, the present invention ignores the discontinuous desynchronization signal when the digital receiving apparatus detects the synchronization and slides the phase only for the continuous desynchronization signal, thereby reducing the time required for the synchronization detection. There is an effect that can provide a stable synchronization signal.

Claims (3)

A synchronous detection apparatus of a digital transmission system that receives encoded data and decodes it to a state before it is protected, comprising: a deinterleaving unit for deinterleaving the received digital data according to a synchronous control signal applied from the synchronous detection unit; A lattice decoding unit for lattice decoding the data applied from the deinterleaving unit, and determining whether or not the data is synchronized to generate a synchronization signal or a departure signal; A continuous error signal determining unit for applying an enable signal to the synchronization detecting unit when a predetermined number of deviation signals generated by the grid decoding unit are applied; And a synchronization detector for applying a synchronization control signal to the deinterleaving unit when an enable signal from the continuous error signal determination unit is applied. 2. The apparatus of claim 1, wherein the continuous error signal judging unit comprises: a predetermined number of delay elements connected in series for continuously delaying the desynchronization signal applied from the grid decoding unit; And a logic element for generating an enable signal when the out-of-synchronization signal and a signal from each of the plurality of delay elements are applied to the synchronism detection device of the digital transmission system. A synchronous detection method of a digital transmission system that receives encoded data and decodes it to a state before encoding, the method comprising: deinterleaving the received digital data; Determining whether synchronization is de-interleaved from the deinterleaved data and generating a deviation signal when synchronization is not corrected; And sliding the synchronization phase of data when the synchronization departure signal occurs continuously by a predetermined number.