JP2871140B2 - Demodulation reference phase ambiguity removal system and receiving apparatus therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation reference phase ambiguity elimination system and a receiver thereof, and more particularly to a demodulation reference phase ambiguity elimination system in a digital radio communication system or the like for performing error correction.

[0002]

2. Description of the Related Art In a digital radio communication system or the like, a data sequence to be transmitted is error-correction-coded on a transmission side and then transmitted as a modulated signal, and a data sequence obtained by demodulating a received signal is error-correction decoded on a reception side. It is common practice to eliminate errors during transmission.

For example, one data string to be transmitted is convolutionally encoded to obtain two data strings, and a carrier signal is four-phase-modulated with these data strings and transmitted. On the receiving side, the four-phase modulated signal, which is a received signal, is synchronously detected to obtain two data strings, and these data strings are error-corrected and decoded by a Viterbi decoder.

[0004] A demodulator on the receiving side reproduces a demodulation reference carrier signal from the input 4-phase phase modulated signal, and performs synchronous detection using the demodulation reference carrier signal.

As is well known, a demodulation reference carrier signal reproduced from a quadrature modulation signal such as a four-phase modulation signal has a phase ambiguity that is an integral multiple of 90 degrees. If this demodulation reference phase ambiguity is not removed, the data sequence output from the encoder to the modulator on the transmission side matches the data sequence output from the demodulator to the decoder on the reception side (even if there is no transmission error). Otherwise, error correction decoding cannot be performed. If the difference between the demodulation reference phases is 180 degrees, both data strings from the demodulator are inverted. If the difference is 90 degrees or 270 degrees, the order of the two data strings is reversed, and one of the data strings is inverted. Therefore, it is necessary to detect a difference between the demodulation reference phases by any method and correct the difference.

The necessity of correcting the difference between the demodulation reference phases is not limited to the above-described example, and the error correction is performed and the modulation method involves a phase modulation such as a two-phase modulation method or a multilevel quadrature amplitude modulation method. As long as the modulation method is used, it is a common problem regardless of the type of the error correction method or the modulation method.

FIG. 2 shows a conventional system for correcting a difference between demodulation reference phases.

In this conventional example, an encoder 52 for convolutionally encoding a data string containing a unique word for frame synchronization and a modulation method using at least phase modulation are used.
2, a transmitting side 50 having a modulator 53 for outputting a modulated signal modulated by the data sequence from 2, a demodulator 62 for synchronously detecting and demodulating the modulated signal transmitted from the transmitting side, and a demodulation reference of the demodulator 62. When a control signal is input to remove the phase difference, the data sequence from the demodulator 62 can be logically phase-converted in a predetermined order. A decoder 64 for performing error correction using the Viterbi algorithm, detects a unique word included in the data string from the decoder 64, synchronizes the frames, and outputs a control signal unless a predetermined time frame synchronization is established. Circuit 66, and
The unique word remover 6 receives a unique word removal timing generated from the frame synchronization established in the frame synchronization determination circuit 66, and outputs a data string obtained by removing the unique word from the data string output by the decoder 64.
5 having a receiving side 60.

[0009]

The conventional demodulation reference phase ambiguity removal system has the following problems.

An example of the encoder 52 is as shown in FIG.
Shift register 520 and exclusive OR circuits 521, 5
22. The data sequence obtained by encoding the data sequence input to the register 523 of the shift register 520 includes an I data sequence that takes the exclusive OR of the current bit and the immediately preceding bit, and a current bit and one bit. This is a Q data sequence that takes the exclusive OR of the previous bit and the two previous bits. Further, an exclusive OR of bits output at the same time in the I data sequence and the Q data sequence is obtained to obtain an input data sequence (hereinafter, this code is referred to as Q
LI code). FIG. 4 is a grid-like representation of a data sequence encoded by the encoder of FIG. In FIG. 4, the numbers in the circles represent the internal state of the shift register 520 in decimal, and the values on the lines representing the transitions between the nodes represent I and Q data, respectively.

Here, since the same can be said from the linearity of the convolutional code, a case where an all-zero coded data sequence is transmitted will be considered. A part of the all-zero coded data sequence coded by the coder 52 is indicated by a thick solid line in the grid-like representation of FIG. If the signal modulated with this coded data sequence is input to the decoder 64 with the correct phase, it can be correctly decoded using the Viterbi algorithm. The surviving path of each node is stored in the path memory, and the maximum likelihood path determination circuit outputs decoded bits.

The Viterbi algorithm discards the most probable path among the plurality of paths input to each node in the lattice representation representing the state of the convolutional encoder as a surviving path. This operation is performed for all states over all time series. In selecting a path, first, a metric of each branch is calculated and added to each metric of the surviving path of each node, thereby calculating a total metric of each path. Here, the metric is a quantity indicating the certainty of a branch or a path. Each node compares the metric of each input path, leaves the path with the larger metric, and discards others. When a plurality of path metrics have the same value, one is arbitrarily selected (for example, edited by the Institute of Electronics, Information and Communication Engineers, Yamamoto, Kato “TDMA Communication” (Head 1-4-5) Corona, P.S. 10
3).

Therefore, the difference between the demodulation reference phases is 180.
In other words, it is assumed that the two data strings from the demodulator 62 are both inverted, and a sequence of all “1” is output.
At this time, as shown by a dotted line in FIG. 4, if a path that diverges from a path obtained when the phase is correct and merges again after 3 hours becomes a surviving path that exists individually for each time, it is stored in the path memory. Depending on the method of determining the maximum likelihood path among the surviving paths, a correct result is output. Further, depending on the data series following the unique word, if both data strings are inverted and input to the Viterbi decoder after encoding, the unique word is correctly decoded.
In general, in a conventional system using a QLI code such as that output from the encoder of FIG. 3, when two data strings in which both correct-phase data strings are inverted are input to a decoder, data following a unique word is input. Depending on the sequence pattern and the maximum likelihood path determination method, only unique words can be correctly decoded, or all input data sequences can be correctly decoded, and frame synchronization is established and phase ambiguity cannot be removed.

What has been described above is a phenomenon in which there is no transmission error in the output data sequence from the demodulator 62.
In the case where a transmission error occurs in the output data sequence from, the received data sequence having a transmission error that is normally input to the decoder 62 at the correct phase and can be decoded into a substantially correct input data sequence is inverted and transmitted to the decoder 62. Once entered,
Frame synchronization can be established, and a decoding error is generated to the extent that frame synchronization is not lost.

As described above, in the conventional demodulation reference phase ambiguity removal system, when the error correction code is a QLI code, and when the difference between the demodulation reference phases is 180 degrees, the input to the decoder is changed to the correct phase. In some cases, depending on the number of transmission errors, there is a problem that a considerable number of decoding errors occur as compared with the case where the phase is correct.

An object of the present invention is to provide a demodulation reference phase ambiguity elimination system capable of always obtaining a correct demodulation reference phase even when an error correction code is a QLI code, and a receiving apparatus therefor.

[0017]

SUMMARY OF THE INVENTION A demodulation reference phase ambiguity removal system according to the present invention comprises an n-stage shifter for convolutionally encoding a data string including a unique word for frame synchronization.
And n shift registers of the n stages are provided.
Perform exclusive OR of k outputs from the output, and
A first exclusive OR circuit for outputting the first exclusive OR circuit;
One less than the result input to the OR circuit (k-1)
XOR is performed and a second output for outputting Q data is performed.
A code that can easily obtain input data with another OR circuit
A modulator for inputting an encoder, the I data and the Q data, and outputting a modulated signal modulated with a data sequence from the encoder using at least a modulation method involving phase modulation. A transmitting side, a demodulator that synchronously detects and demodulates the modulated signal transmitted from the transmitting side, and when a first or second control signal is input to remove a difference in demodulation reference phase of the demodulator, A phase converter that outputs the data sequence from the demodulator by performing a logical operation on a trial and error basis, and a decoder that performs error correction decoding on the data sequence from the phase converter using the Viterbi algorithm. A frame synchronization judging circuit for outputting the first control signal when the predetermined time frame synchronization is not established by detecting the unique word including the unique word, A second encoder that encodes the data sequence from the decoder in the same manner as the first encoder performs after the synchronization of the frames has been established, and the two data sequences from the second encoder and the second encoder. A counter for counting the number of inconsistencies at predetermined time intervals by comparing at least one data row corresponding to at least one of the two data rows from the demodulator with matching phases, and an output of the counter; before the second control signal when the threshold is exceeded than a predetermined threshold value when
And a receiving side provided with a code synchronization determination circuit for outputting to the phase converter .

A receiving apparatus according to the present invention receives a modulated signal modulated by a convolution-encoded data string including a unique word for frame synchronization using at least a modulation method involving phase modulation, and performs synchronous detection. A demodulator for demodulating,
When a first or second control signal is input to remove the difference in the demodulation reference phase of the demodulator, a phase converter that performs a logical operation on the data sequence from the demodulator by trial and error and outputs the data sequence;
A decoder that performs error correction decoding of the data sequence from the phase converter using the Viterbi algorithm, and a predetermined time-frame synchronization is established by detecting the unique word contained in the data sequence from the decoder and performing frame synchronization. Otherwise, a frame synchronization determination circuit that outputs the first control signal, and an encoder that encodes a data sequence from the decoder in the same manner as performed on the transmission side after frame synchronization is established by the frame synchronization determination circuit. At least one of the two data strings from the coder and the two data strings from the demodulator are compared in phase with each other, and the data strings are compared at predetermined time intervals. A counter for counting the number, and a code for outputting the second control signal when the output of the counter exceeds a predetermined threshold. And a synchronization determination circuit.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.

In this embodiment, the transmitting side 10 includes a unique word adder 11 for adding a unique word for frame synchronization to a data string to be transmitted, and a data string output from the unique word adder 11 as a QLI code structure. An encoder 52 for performing convolutional coding so as to output two data strings and outputting a modulated signal obtained by performing four-phase modulation on the two data strings output from the encoder 52; 1
And a transmitter 14 for wirelessly transmitting the modulated signal from the transmitter 3. The encoder 52 is a non-systematic code as shown in FIG.
The two I data and Q data of the encoder 52 shown in FIG.
The output is subjected to an addition operation using exclusive ORs 521 and 522.
By doing so, the input data string can be understood. QLI mark
The data string of all "0" is used as an encoder except for the data string.
When input, the two outputs of the encoder 12 output a "00"
Outputs encoded data string and codes data string of all "1"
When the encoder is input, the code of "10" is output from the two outputs of the encoder.
Configuration to output encrypted data string (not transparent
).

The receiving side 20 receives a radio wave from the transmitting side 10 and outputs a modulated signal.
The demodulator 22 synchronously detects and demodulates the modulated signal from 1 and outputs the data as two columns of data. The demodulator 22 performs logical operations on the two columns of data from the demodulator 22 to extract the demodulation reference phase in the demodulator 22. A phase converter 23 for correcting the difference, a decoder 24 for performing error correction using the two data strings from the phase converter 23 for the Viterbi algorithm, and a frame synchronization from the data string decoded by the decoder 24. Judgment circuit 26
A unique word remover 25 that removes and outputs a unique word by using a timing signal given from the controller, and a unique word included in the data string output by the decoder 24 are detected and frame synchronization is established, so that frame synchronization is not established for a certain period of time. And a first control signal to control the operation of the phase converter 23 to control the operation of the phase converter 23, and to decode one of the two data strings from the phase converter 23 for the operation after the frame synchronization. 24, a delay unit 27 for delaying the output by a decoding delay, an encoder 28 for performing the same convolutional encoding as the encoder 12 outputs from the decoder 24, and a two-column data sequence output from the encoder 28 Out of the phase converter 23 to the delay unit 2
7, an exclusive OR circuit 29 for determining the difference between the corresponding bit of the data string corresponding to the data extracted to 7 and the output of the delay unit 27; a counter 30 for counting the output from the exclusive OR 29; The counter 30 is read at the same time as reading the value of the counter 30 at regular time intervals, and the read value is compared with a preset threshold value. The signal is output to the phase converter 23
And a code synchronization determination circuit 31 that controls the operation of

Since the demodulation reference carrier signal reproduced by the demodulator 22 from the modulated signal from the receiver 21 has a phase ambiguity of an integral multiple of 90 degrees, the carrier signal in the modulator 13 and the demodulation reference carrier in the demodulator 22 are different. 90 phase with the signal
Sometimes they differ by an integral number of degrees. The phase converter 23
A first operation mode in which the two data strings from demodulator 22 are output as they are, and a logical operation equivalent to the fact that the demodulation reference carrier signal of demodulator 22 has changed to 90 degrees, 180 degrees, and 270 degrees. It has four operation modes, that is, the second, third and fourth operation modes for performing and outputting the two data strings from 22. The current operation mode is maintained unless the first and second control signals are input. Then, when the first and second control signals are input, the operation mode is shifted to the operation mode next to the current operation mode. When the phase of the data sequence input to the decoder 24 is not correct, the decoder 24 generally cannot decode and outputs a meaningless data string. As a result, the frame synchronization determination circuit 26
Cannot detect the unique word from the input data string,
Frame synchronization cannot be achieved. When this state continues for a certain period of time, the frame synchronization determination circuit 26 outputs a first control signal. The operation mode of the phase converter 23 shifts to the next operation mode according to the first control signal. In the course of performing the above operation sequentially for the four operation modes, the difference between the demodulation reference phases is corrected. That is, irrespective of the operation mode in which the initial state starts, generally, the ambiguity of the demodulation reference phase can be removed by outputting the first control signal at most three times.

In accordance with the shift of the operation mode, the correct data or two data trains inverted from the correct data are decoded.
4 and the frame synchronization is established, a frame synchronization signal is supplied to the code synchronization determination circuit 31 to operate the code synchronization determination circuit 31. If the data sequence having the correct phase and the inverted two-line transmission error is correctly decoded by the maximum likelihood path determination inside the decoder 24, the decoded data sequence is convolutionally coded by the encoder 28. Is different from the data sequence obtained by delaying the output from the phase converter 23 by the delay unit 27. Therefore,
Since the value obtained by the counter 30 far exceeds the threshold value given in advance, the code synchronization determination circuit 31 outputs the second control signal to the phase converter 23 to shift to the next operation mode. it can. If there is no transmission error and only the unique word is correctly decoded, the encoder 2
8 and the phase converter 23
The comparison with the one that delayed the output from is quite wrong. Further, when there is a transmission error, two data strings of the correct phase are input to the decoder 24, and the decoder 24 receives the data string of the correct phase with respect to the number of transmission errors that become an almost correct decoded data string. And the value of the counter 30 obtained at a fixed time when frame synchronization is established, and the count value obtained at a fixed time when frame synchronization is established by inputting a data sequence of the correct phase to the decoder 24. Since the value can be separated from the value of 30, the code synchronization determination circuit 31 inverts the data string to the decoder 24 and establishes the second data when the frame synchronization is established by the correctly selected threshold value. The control signal can be output to the phase converter 23 to shift to the next operation mode without error.

[0024]

As described above, according to the present invention, when the error correction code is the QLI code, the correct phase of 2 is used.
Even when the inverted data sequence becomes an input to the decoder and frame synchronization is erroneously established, the inverted data sequence and the data sequence obtained by re-convolution-encoding the output from the decoder are used. A code synchronization determination circuit capable of detecting a difference between the two by comparison is added, and a second control signal capable of performing phase conversion can be output at this time, so that the phase uncertainty can always be removed. Having.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of an example of a conventional demodulation reference phase ambiguity removal system.

FIG. 3 is a block diagram illustrating an example of an encoder 52 in FIG. 2;

FIG. 4 is a diagram in which a data sequence obtained by an encoder 52 in FIG. 3 is represented in a grid pattern.

[Explanation of symbols]

 Reference Signs List 10 transmitting side 11 unique word adder 12 encoder 13 modulator 14 transmitter 20 receiving side 21 receiver 22 demodulator 23 phase converter 24 decoder 25 unique word remover 26 frame synchronization determination circuit 27 delay unit 28 encoder 29 Exclusive OR circuit 30 Counter 31 Code synchronization determination circuit

Claims (2)

(57) [Claims] 1. Includes a unique word for frame synchronization
In order to convolutionally encode a data string, an n-stage shift register
A shift register, and n outputs of the n-stage shift register
Perform exclusive OR of k outputs and output I data
A first exclusive OR circuit, and the first exclusive OR circuit
(K-1) discharges one less than the result input to the circuit
A second exclusive logic that performs another OR operation and outputs Q data
An encoder that can easily obtain input data with a logical sum circuit
A transmitter having a modulator that inputs the I data and the Q data and outputs a modulated signal modulated by a data sequence from the encoder using a modulation method that involves at least phase modulation. A demodulator for synchronously detecting and demodulating the transmitted modulated signal, and when a first or second control signal is input to remove a difference in the demodulation reference phase of the demodulator, a data sequence from the demodulator is tried. A phase converter that outputs a logically operated logical operation, a decoder that performs error correction decoding on the data sequence from the phase converter using the Viterbi algorithm, and detects the unique word included in the data sequence from the decoder. A frame synchronization determining circuit that outputs the first control signal when frame synchronization is established and a predetermined time frame synchronization is not established; frame synchronization by the frame synchronization determining circuit A second encoder that, after establishment, encodes the data stream from the decoder in the same way as the first encoder does, the two data streams from this second encoder and the data stream from the demodulator A counter that compares at least one data row corresponding to at least one of the two data rows in phase with each other and counts the number of mismatches at predetermined time intervals; and
If the output of the counter exceeds a threshold value as compared with a predetermined threshold value, the second control signal is output to the position.
A demodulation reference phase ambiguity elimination system, comprising: a receiving side including a code synchronization determination circuit that outputs the code synchronization to a phase converter . 2. A modulated signal obtained by modulating at least a data sequence including a unique word for frame synchronization using a modulation method involving phase modulation by a data sequence obtained by convolutionally encoding the data sequence using the encoder, and performing synchronous detection. A demodulator for demodulating
When a first or second control signal is input to remove the difference in the demodulation reference phase of the demodulator, a phase converter that performs a logical operation on the data sequence from the demodulator by trial and error and outputs the data sequence;
A decoder that performs error correction decoding of the data sequence from the phase converter using the Viterbi algorithm, and a predetermined time-frame synchronization is established by detecting the unique word contained in the data sequence from the decoder and performing frame synchronization. Otherwise, a frame synchronization determination circuit that outputs the first control signal, and an encoder that encodes a data sequence from the decoder in the same manner as performed on the transmission side after frame synchronization is established by the frame synchronization determination circuit. At least one of the two data strings from the coder and the two data strings from the demodulator are compared in phase with each other, and the data strings are compared at predetermined time intervals. A counter for counting the number, and a code for outputting the second control signal when the output of the counter exceeds a predetermined threshold. The receiving apparatus includes a synchronization determination circuit
2. The demodulation reference phase ambiguity according to claim 1, wherein
Disambiguation system.