JPS60177732A - Error detecting system by viterbi decoder - Google Patents

Abstract

PURPOSE:To detect exactly an error in case a punctured system is applied, by inhibiting the output of an erroneous pulse due to a dummy code, by a metric calculation inhibiting signal. CONSTITUTION:Data I, Q to which a dummy code is inserted, which are inputted to terminals T1, T2 are decoded by a viterbi decoder 1, corrected as to its error, attains a data equal to a transmitting data D,encoded convolutionally by a convolutional encoder 2. attain data I', Q' an in EX-OR circuits 5, 6, the dissidence to the data I, Q delayed by delaying circuits 3, 4, and in case of a dissidence bit, the pulse of an I level is inputted to AND circuits 10, 11. Also, at the time point when the dummy code is inserted, metric calculation inhibiting signals R, S for sending out a ''0'' level are delayed by delaying circuits 8, 9, inputted to the circuits 10, 11 so as to execute synchronization with a code restored to a code which has erased the dummy signal, of the data I', Q', the output of the pulse of the dissidence bit in a dummy code position is inhibited, and only an error detecting pulse before inserting the dummy code is outputted through an OR circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a convolutional coding system mainly used for automatically correcting errors in digital information of #star communications.
The present invention relates to an error detection circuit using a Viterbi decoder in the Viterbi decoding method, and particularly to an error detection method using a Viterbi decoder that can be used even when a puncturing method is applied.

(b) Technical background In satellite communications, transmitting stations and receiving stations are far apart. For this reason, the transmitting side must transmit with high power, but in order to increase this transmit power, the device must be made larger. For this reason, the transmission power is kept to a level that allows reception at the receiving station. Therefore, the current level of incoming calls at the receiving station is low, and the signal-to-noise ratio (hereinafter referred to as S/N) becomes poor due to the thermal noise of the receiver. Since this thermal noise is random noise, it is necessary to use a code/decoding method that is resistant to this random noise for the digital information to be transmitted.

Therefore, a system in which convolutional codes are used for encoding and Viterbi decoding, which has excellent error correction ability, is used for decoding, has become popular in recent years. In satellite communications, 4-phase PSK (Phase 5hif't
Keying method is used.

For this reason, in convolutional coding for satellite communication, transmission data is convolutionally coded into I (Inphase)CH (
Channel ) data and Q (Quadrature
e) CH data is divided into two binary data and transmitted 0 Therefore, if you add up the l-CH and Q-CH, twice as much information has to be sent, and the transmission efficiency becomes 1/2. In order to increase the transmission efficiency, a punctured method is used in which a portion of the coded bits are appropriately erased. In this punctured method, each bit is one cycle, and the first bit is
H is not erased, but the remaining 11 bits are used to alternately erase the bits of one of the CHs. On the receiving side, the dummy signal insertion unit inserts an arbitrary dummy code into the erased bit position, and prohibits metric calculation of the inserted signal and dummy code. The signal is decoded by a Viterbi decoder, errors are corrected, and then received. In the case of this decoding, the inserted dummy code is also corrected in the decoder so that it becomes the code deleted on the transmitting side so that it matches the data transmitted on the transmitting side.

(C) Prior Art and Problems In the case of a method in which convolutionally encoded ICH and QCH data is transmitted as is and Viterbi decoding is performed on the receiving side, there is a conventional error detection method shown in FIG. 1.

The ICH and QCH data obtained by convolutionally encoding the transmission data D by the convolutional encoder on the transmitting side pass through various transmission paths and are sent to the terminals T, T, and T of the Tobi decoder 1 shown in FIG. The data is inputted as received data D, decoded and error corrected by the Viterbi decoder 1, and outputted as received data D. In order to detect errors in data I and Q, this data D is convolutionally encoded by convolutional encoder 2.
M, Q are input to exclusive OR (hereinafter referred to as EX-OR) circuits 5 and 6 as data I' and Q' of CM, and -10,000 data I.

Q is delayed by the delay circuit 3.4, and the Tavi decoder 1.
It is synchronized with data E' and Q' that have passed through the convolutional encoder 2, and is input to an EX-OR circuit 5.6.

In the EX-OR circuits 5 and 6, data I including error bits,
Error bits are found by detecting mismatch between Q and error-corrected data I/ and Q/ bit by bit, and a pulse of the special electric 1 level is output when the mismatched bit is detected, and OR is performed.
Errors are detected by outputting them as error pulses through the circuit 7. However, there is a probability of a mismatch between the code restored to the error-corrected code in the Batapi decoder 1 and the dummy code, which is an arbitrary code, and the dummy code, which is an arbitrary code, is about 50. Therefore, if we compare the data I and Q into which the dummy code has been inserted and the data x/Q7 which has been convolutionally encoded again after Viterbi decoder error correction, there is a probability of mismatch in the dummy code part with approximately 50% probability. Ru. Therefore, in this case, the circuit shown in FIG. 1 cannot be used as an error detection circuit for data before inserting the dummy code.

Note that T, , T4 are input terminals for a metric calculation prohibition signal.

(d)〉Object of the Invention In view of the above-mentioned problems, an object of the present invention is to provide an error detection method using a tabi decoder that can be used even when a punctit method is applied.

(e) Structure of the Invention In order to achieve the above object, the present invention includes a first signal in which a dummy code is inserted in place of the code erased by the puncturing method, and a metric calculation prohibition signal for the dummy code. The first signal is input to the Tavi decoder, the error is corrected by decoding the first signal, and the second signal is compared with the first signal. The present invention is characterized in that the output is blocked by the metric calculation prohibition signal.

That is, by doing this, the dummy code is compared with the code corrected to the code from which the dummy code has been deleted.

(f) Examples of the invention Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 2 is a block diagram of an error detection circuit according to an embodiment of the present invention, in which the same functions as those in FIG. 1 are indicated by the same symbols.
8 and 9 are delay circuits, 10.11 is an AND circuit, and 12 is an O
R1 road +'rs and T4 are each ICH.

This shows the input terminal of the QCH metric calculation prohibition signal. Figure 3 is a pattern diagram of erasing a code and inserting a dummy code as an example of the puncturing method.The upper row shows the ICl1 side, the lower row shows the QCH side, and in the case of %O'', the code is deleted and a dummy code is inserted. It shows the case.

Figure 2 shows a loss detection circuit using a Viterbi decoder that can be used even when the bank dead method is applied, and a dummy code is inserted into the terminals TI and T2 at the position of the code erased by the dummy signal insertion section. data I and Q are input to terminals Ts and 1'*, and a 10" level metric calculation prohibition signal R8, which prohibits metric calculation of the dummy codes inserted into ICH and QCH, respectively, is applied at the time of dummy code insertion. Input from the dummy code insertion section.

The data I and Q inputted to the terminals TI and T2, into which dummy codes have been inserted, are decoded and error-corrected by the tabi decoder 1 in the same way as in the case of FIG. 1, and become data D equal to the transmission data D. The data is convolutionally encoded by the convolutional encoder 2 to become data I' and Q', and in the case of a matching bit, the Lebel pulse is input to the AND circuit 10, l'l. However, the dummy codes of data I, Q and the data I', 'Q which are error-corrected and restored to the erased codes.
', there are 503 errors, so if the pulse of the mismatched bit is used as error detection, it will not be the error detection of the data before inserting the dummy code, so the mismatched bit at the tummy code position Pulse Ltd). For this reason, at the time of inserting the dummy code, the metric calculation prohibition signal R1S that sends out the ``0'' level is delayed by the delay circuits 8 and 9, respectively, and the data 1/.

The code from which the dummy code of Q' has been deleted is synchronized with the restored code, and is input to the AND circuits 10 and 11, and the output of the pulse of the mismatched bit at the dummy code position is prohibited. Only the error detection pulse before dummy code insertion is outputted via the OR circuit 12.

In this way, incorrect detection of error pulses due to dummy code insertion can be avoided. Of course, if the puncturing method is not applied, error pulses can be detected in the same way as in the case of FIG. 1 by applying 1 level to the T, , T4 terminals.

In the above explanation, the amount of delay in the delay circuits 8 and 9 is the amount of delay for data 1. Q is the Viterbi decoder 1. Convolutional encoder 2.
Although it is necessary to delay the data through EX-OR circuit 5 or 6, since the amount of delay in Viterbi decoder 1 (the number of processing stages with 7 logic flops) is large, for example, delay circuit 8
．． If 9 is constructed with a shift register, the circuit scale will be considerably large.

Therefore, we focused on the punctured dead method shown in FIG.
By setting the number N of shift register stages corresponding to , to the remainder when M is divided by k, the number of shift register stages of the delay circuits 8 and 9 can be extremely reduced.

For example, assuming that there is no delay due to the number of delay stages M = 70° in Viterbi decoder 1, what is the dummy code insertion situation at the four points in Figure 3, which is delayed by 70 stages, and the current dummy code insertion situation at point A? Since they are equal, if the current metric calculation prohibition signal which is not delayed by the delay circuit 8.9 is used, the output of the error detection signal in the case of a dummy code can be prohibited by the AND circuit 10.11. Next, if the number of delay stages of the Viterbi decoder 1 is M = 71, the dummy code insertion situation at point C in Figure 3, which is delayed by 71 stages, is the same as the dummy code insertion situation at two points, where the current point A is delayed by one stage. Therefore, the number of delay stages of the delay circuits 8.9 may be set to 1.

This is 0, which corresponds to the remainder when M is divided by k. Therefore, the number of delay stages in delay circuits 8 and 9, which corresponds to Viterbi decoder 1, is the number of delay stages M in Viterbi decoder 1. The delay circuits 8 and 9 can be made extremely compact by setting the number of stages to the remainder after dividing by the number k.

FIG. 4 is a block diagram of an error detection circuit according to another embodiment of the present invention, in which the same functions as in FIG. 1 are indicated by the same symbols, 13.15 is an AND circuit, and 14 is a delay circuit. .

In FIG. 4, one delay circuit 14 is used instead of the two delay circuits 8 and 9 in FIG. 2 to inhibit the output of mismatched bits at dummy code positions.

That is, when no dummy code is inserted, the metric calculation prohibition signals R and S are at the 1 level as shown in FIG. , the metric calculation prohibition signals R and S are input to the AND circuit 13, and the AND circuit 13 outputs a level of %0 when a dummy code is inserted, and the AND circuit 15 detects the mismatch bit at the dummy code position. The output of pulses is prohibited.

FIG. 5 is also a block diagram of an error detection circuit according to another embodiment of the present invention. Components having the same functions as those in FIG. ,
19 is an AND circuit, and SWI to SW3 are interlocking switches.

The circuit shown in FIG. 5 detects error bits in data before inserting a dummy code for either ICH or QCH, and switches SWI, SW2. If SW3 is the connection side shown by the solid line, the error bit on the ICH side can be detected in the same way as explained in the case of FIG. 2, and switches SWI, SW2 . S
If W3 is on the connection side shown by the dotted line, error bits on the QCH side can be detected.

(g) Effects of the Invention As explained in detail above, according to the present invention, the IJ hook calculation prohibition signal eliminates the output of erroneous error pulses due to dummy codes, so even when the puncturing method is applied, errors can be corrected. This has the effect of providing an error detection circuit using a Viterbi decoder that can detect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an error detection circuit using a conventional Viterbi decoder, FIGS. 2, 4, and 5 are block diagrams of an error detection circuit using a Viterbi decoder according to an embodiment of the present invention. This is a turn diagram for erasing codes and inserting dummy codes in an example of the chunk-tailed method. In the figure, 1 is a Viterbi decoder, 2 is a convolutional encoder, and 3 is a convolutional encoder.
, 4, 8, 9, 14, 16.17 are delay circuits, 5.6.
, -18 is an exclusive OR circuit, r, x2 is an OR circuit, 1
0゜11, 13.15.19 are AND circuits, SWI, S
W2°SW3 indicates a switch. Closed

Claims (1)

[Claims] The bankcharac computation prohibition signal of the convolutional encoding Vitapi decoding method is input to the Viterbi decoder, and the output obtained by decoding the first signal and correcting errors is input to the convolutional encoder and re-encoded. Among the outputs in which an error pulse is detected by comparing the signal with the first code, the output of the error pulse when compared with the dummy code is blocked by the IJ Cook calculation prohibition signal. An error detection method using a Viterbi decoder characterized by the following.