JPH0783280B2 - Error correction device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an error correction method using convolutional coding / Viterbi decoding in continuous mode digital communication.

[Conventional technology]

FIG. 3 and FIG. 4 are block diagrams showing a conventional continuous mode error correction method using convolutional coding / Viterbi decoding, and show a transmitting side and a receiving side, respectively. In FIG. 3, 1 is a transmission data input terminal, 3 is a frame synchronization pattern generation circuit for generating a frame synchronization pattern, 2 is a speed conversion (multiplexing) for making a frame from this frame synchronization pattern and multiplexing this with transmission data. ) Circuit 4, 4 is a convolutional encoder, 5 is a modulator which modulates a carrier wave by the encoded data output from the convolutional encoder 4, and 6 is a modulated wave output terminal. Further, in FIG. 4, reference numeral 7 is a received modulated wave input terminal, 8 is a demodulator for demodulating coded data from the modulated wave, and 9 is a demodulator.
Is a Viterbi decoder for decoding multiplexed data from encoded data. In this Viterbi decoder 9, 10 is a branch metric calculation circuit, 11 is an ACS circuit (ACS = Add Compare Se
lect: addition / comparison / selection), 12 is a path memory circuit, 13 is a maximum likelihood state detection circuit, and 14 is a traceback control circuit. Reference numeral 15 is a frame synchronization circuit for frame synchronization from the multiplexed data decoded by the Viterbi decoder 9, 16
Is a speed conversion (separation) circuit for speed-converting and separating the original received data according to the frame timing from the frame synchronization circuit 15.

Next, the operation will be described.

First, the transmitting side of FIG. 3 will be described. The transmitted data is
The speed conversion (multiplexing) circuit 2 multiplexes together with the frame synchronization pattern from the frame synchronization pattern generation circuit 3 to form a frame. Furthermore, this multiplexed data is convolutionally coded in the convolutional encoder 4 to perform error correction coding, and redundant bits are added. Further, the coded data is guided to the modulator 5 so as to be easily adapted to the transmission path, and a carrier wave is modulated by the coded data and output from the modulated wave output terminal 6.

Before explaining the receiving side of FIG. 4, the Viterbi decoder will be described first. Generally rate 1 / n, constraint length K
The convolutional encoder of is represented as shown in FIG. That is, at time i, when the transmission data ui is input from the left end of the K shift registers, the shift register shifts the data to the right by 1 bit, and the data ui and the past data in the registers are shifted.
An appropriate combination of n modulo 2 is added from ui-1 to ui-k + 1, and the n data are output to the transmission path as encoded data. At this time, the ratio 1 / n of 1 information bit to n bits of coded data is called a rate (coding rate), and the number K of shift register stages is called a constraint length.

For simplification of description, a case of rate 1/2 and K = 3 will be described here. A rate 1/2, K = 3 convolutional encoder is shown in FIG. Of the stored contents of the shift register at a certain time i (i is an integer), the contents from the left to K-1 (= 2) are called a state. In the example of FIG. 6, the state at the current time i is 01, and the state at the next time i + 1 after the shift register is shifted by 1 bit is 00. There are 2 ^K-1 kinds of states in all. As is clear from this example, the coded symbol output at time i + 1 is determined by the state 01 at time i and is not related to the rightmost data.

Here, taking four states (00, 01, 10, 11) as an example, consider a trellis diagram showing transitions between these states as shown in FIG.
In the figure, the first start state is 00, that is, the two contents from the left of the register are 00, the upper branch is 0 data, and the lower branch is 1 data is input to the register at the next time. Represents the state transition of. That is, if the data 0 is input at the time 1 at the time 00 at the time 0, the state at the time 1 becomes 00, and if the data 1 is input, the state at the time 1 becomes 10. The coded symbol output at this time is written on each branch, and 00 is output as the upper branch and 11 is output as the lower branch as encoded data. That is, the trellis diagram of FIG. 7 can be thought of as showing the transitions between all possible states of the convolutional encoder.

The Viterbi decoding method is one decoding method of the above convolutional code,
It was proposed by AJ Viterbi of the United States, and details of its operation are described in, for example, the paper “GD Forney Jr.“ Viterbi Algorithm ”” (“G.
D.Forney, J _R .; “The Viterbi Algorithm”, Proceeceing
of the IEEE, Vol.61, No.3, March 1973, pp.268-278 ")
It is described in. Now, as an example, rate 1/2, K in Fig. 6
Consider the case where information symbols 00000 ... Are transmitted in a convolutional encoder of = 3. The coded symbols output at this time are 00 00 00 00 ... As shown in FIG.
Now, these coded symbols are output to the transmission line, and 2 bits are erroneously received due to noise, and as shown in FIG.
Let's say 00 10 00 00 ... At this time, the receiving side performs the following operation to decode the transmitted information symbol. That is, the receiving side calculates the likelihood (metric) of each state on the trellis diagram starting from state 00.

Here, as the metric, for example, the Hamming distance (the number of mismatches) between the coded symbol in the trellis diagram (FIG. 7) of the convolutional encoder and the actually received coded symbol is used. This will be described with reference to FIG. 9. First, in FIG. 9A, the metric of the state 00 is set to 0. In the trellis diagram of FIG. 7, the state 0 at time 0 to the state 1 at time
The coded symbol when transiting to 00 is 00, and when transitioning to state 10 is 11, the data actually received at this time is from FIG. 8 to 10, so the Hamming distance ( Each of them is 1).
This value is stored as a metric for state 00 and state 10 at time 1 (this is called a state metric).
In the transition from time 1 to time 2, the coded symbols on the branch on the trellis diagram of FIG. 7 and the Hamming distance (= branch metric) of the actually received data are calculated in exactly the same way,
The metric of the state before transitioning to that state is added to obtain the metric of that state. This is shown in FIG. 9 (a). Next, in the transition of time 2 → 3, the metric calculation of each branch is performed in the same manner, but as is clear from the trellis diagram of FIG. 7, the branch transitioning to one state is at time 3 There are two. Therefore, here, for two branches that make a transition to a certain state, the metric of the state before the transition (state metric) and the metric of the branch (branch metric) are added, and the number of metrics is small. One (that is, one with higher likelihood) is left and the others are discarded, and the remaining metric is used as the state metric of the new state. This procedure is the addition / comparison / selection procedure (ACS procedure = Add S
elect Compare). This state is shown in FIG. 9 (b). Thereafter, when the time is advanced in exactly the same manner, it becomes as shown in FIGS. 9 (c), (d), and (e).

Next, a method of actually outputting data will be described. As described above, the addition / comparison / selection procedure is repeated for each state at each time, and the result of addition, comparison, and selection at each time is selected by the upper branch for each state. When it is done, it is set to 0, and when the lower branch is selected, it is set to 1 and so on. Next, when such memory is accumulated to some extent, the state with the least state metric,
That is, from the high likelihood state, the path is added to the stored addition,
It traces back according to the result of comparison and selection, and at a stage traced back by a certain number of times, the data of the result of addition, comparison and selection stored in the memory at that time is output as decoded data. This method is called path traceback. This is, for example, the state 00 at the right end in FIG. 9 (e).
This is equivalent to outputting the result 0 of the ACS procedure stored in the state 00 when the traceback is started from 9 and going back to the 9th time as decoded data. In FIG. 9 (e), no matter which state is started, the correct path within 2 hours,
That is, it can be seen that the path converges to the transmitted path. It should be noted that the number of times that need to be traced back, that is, the number of times that the improvement in coding gain cannot be obtained by tracing back more than that, is (constraint length-
It is about 5 times that of 1), which is called the truncation depth.

Next, the operation on the receiving side in FIG. 4 will be described. The modulated wave received along with noise through the transmission line is input from the input terminal 7 and demodulated by the demodulator 8 into the original encoded data. Since this coded data contains many errors due to noise on the transmission path, it is guided to the Viterbi decoder 9 and the errors are corrected. In the Viterbi decoder 9, as described above, every time the transmitted compound word is received, the receiving side generates code words of all the branches that the encoder can take, and the correlation with the received code word (described above). Corresponding to the number of disagreements). This correlation value is called a branch metric, and the branch metric calculation circuit 10 performs this operation. This branch metric is then added to the stored current metric for each state to calculate a new metric, and the ACS procedure (Add Compare Select:
The addition / comparison / selection) is executed by the ACS circuit 11. In addition,
As described above, the metric increases every time one codeword is received, so that the metric does not overflow,
It is necessary to periodically perform the metric subtraction, but since it is not a particularly essential problem here, it was deleted in FIG. Further, the result of addition, comparison, and selection of each state obtained by the ACS procedure is stored in the path memory circuit 12 for each state.

Next, the data output is the maximum likelihood state detection circuit as described above.
From the state having the maximum likelihood metric found during one decoding cycle (time to decode one bit of data) by 13, the traceback control circuit 14 traces back the path memory circuit 12 by the depth of the truncation of the path. Finally, 1 bit of data stored in the path memory circuit 12 is output as decoded data. That is, according to this method, in order to decode 1 bit of data, it is necessary to access the path memory a number of times corresponding to the truncation depth during one decoding cycle.

The multiplexed data decoded by the traceback of the path is frame-synchronized by the frame synchronization circuit 15, and the original transmission data is separated by the speed conversion (separation) circuit 16 according to this frame synchronization timing, and then the data output terminal. It is output from 17.

[Problems to be solved by the invention]

Since the conventional error correction method using convolutional coding / Viterbi decoding in continuous mode digital communication is configured as described above, in the Viterbi decoder, path traceback is performed during one decoding cycle. It is necessary to perform the truncation over the entire length of the truncation depth (about 5 times the (constraint length-1)). Therefore, it is difficult to increase the data transmission rate of the transmission path.

The present invention has been made in order to solve the above problems, and the decoding speed of a Viterbi decoder is defined by setting the number of tracebacks performed to the path memory of the Viterbi decoder to be one during one decoding cycle. It is an object of the present invention to obtain an error correction method using convolutional coding / Viterbi decoding which can speed up the transmission speed, and as a result, can dramatically increase the data transmission rate of the transmission path.

[Means for solving problems]

The error correction system according to the present invention resets the shift register of the convolutional encoder at the start of data in a frame, and (constraint length-1) dummy data (end of code) at the end of data in a frame. )
A control circuit for convolutionally coding the data in units of one frame as shown in FIG. 2 and means for adding a frame pattern for indicating a frame delimiter to the coded data are provided in the transmission device, and the frame pattern is A frame synchronization circuit that obtains frame synchronization by detection, and calculates a branch metric between states based on the actually received encoded data and the encoded data that can be taken by the convolutional encoding means of the transmitter. Circuit, the branch metric value of the branch metric calculation circuit, and the metric value of the state before the transition to the state are added to calculate the metric value in the state, and the state before the transition to the state is plural. In some cases, each addition result is further compared, and an ACS circuit that selects the smallest metric value as the metric value in the state and an addition that is the output of the ACS circuit,
The first and second path memory circuits capable of storing the result of comparison and selection for one frame, and addition, comparison, and selection which are outputs of the ACS circuit to either one of the two path memory circuits in a certain frame period. The result of 1 is stored for one frame, and the addition, comparison, and selection data of one frame before stored in the other path memory circuit during that period are traced back in all states, and in the next frame, the above two A Viterbi decoder having a traceback control circuit for changing the role of a memory and decoding data is provided in the receiving device.

[Action]

According to the present invention, in the Viterbi decoder, two path memory circuits are provided, and while writing the result of ACS to one path memory, the other path memory traces back the entire frame length in one frame period. From
The number of tracebacks performed on the path memory during one decoding cycle is once, and the decoding speed is dramatically increased. In addition, since the most recent state detection circuit can be omitted, the hardware scale can be greatly reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
The figure shows the transmitting side, and FIG. 2 shows the receiving side. In FIG. 1, 31 indicates resetting the register of the convolutional encoder 4 at the frame start point according to the frame delimiter transmitted from the frame synchronization pattern generating circuit 3. The control circuit adds the end data of (constraint length-1) codes at the end of the frame. In FIG. 2, reference numerals 21 and 22 denote first and second path memory circuits that store the results of addition, comparison, and selection for one frame for each state, and 23 denotes these two path memories 21 and 22. Traceback control circuit that outputs the data by alternating the functions of addition / comparison / selection result storage and traceback on a frame-by-frame basis, and 24 is an output that rearranges the decoded data for one frame on the time axis It is a buffer circuit. Further, 25 is a Viterbi decoder.

Next, the operation will be described.

In this embodiment, when the data is convolutionally encoded, the data is divided into frames, the register of the convolutional encoder 4 is reset at the start of the frame, and (constraint length-1) at the end of the frame. Is added to the end of the code (usually all 0s). This control is performed by the control circuit 31 on the transmission side. As a result, each data is convolutionally coded in a complete form for each frame, and the rate conversion (multiplexing) circuit 2 inserts a frame pattern for each frame to divide the frame and send it to the modulator 5. After modulation output terminal 6
Is transmitted to the transmission line. FIG. 10 shows the trellis diagram showing the completion of the convolutional code for each frame. However, the figure shows the case where the rate is 1/2 and the constraint length is 3.

Next, the receiving side will be described. First, the baseband signal demodulated by the decoder 8 in FIG.
The frame is synchronized by 15 and divided into frames, and the Viterbi decoder 25 performs the following processing for each frame. That is, a case of rate 1/2 and constraint length 3 will be described. First, at the start of a frame, the ASC circuit 11 of the Viterbi decoder sets the state metric of the state 00 to 0, and the state metric for other states. ∞
(A sufficiently large number). This is because, as is clear from the trellis diagram in FIG. 10, the transmission side encoder is configured so that the trellis structure of the code starts from the state 00 at the start of the frame.

Next, the operations of the first path memory circuit 21 and the second path memory circuit 22 of FIG. 2 are controlled as follows to output data. That is, all the results of addition, comparison, and selection of the output of the ACS circuit 11 in a certain frame period are stored in the first path memory circuit 21. During this time, the second path memory circuit 22
The traceback of is performed over the entire length of the data for one frame using the results of addition, comparison and selection stored one frame before. The start state of the traceback at this time is
It always corresponds to the end of the code. This is the rate
In the trellis diagram with 1/2 and constraint length 3 (Fig. 10), it corresponds to starting the traceback from the final state 00 of the trellis structure of one frame. That is, on the transmitting side (the constraint length-
1) Since the end of the code of bits is added to the end of the frame, the receiving side knows that the frame always ends in the maximum likelihood state corresponding to the end of the code. Therefore, traceback is started from this state. By doing so, it is possible to perform decoding with little deterioration. Further, in the next frame period, the roles of the first path memory circuit 21 and the second path memory circuit 22 are changed, and this time, the second path memory circuit 22 performs addition / comparison in one frame. The selection result is stored, and the first path memory circuit 21 traces back one frame. The trace-back control circuit 23 controls the writing to the path memory in units of frames and the trace-back control based on the frame synchronization pulse from the frame synchronization circuit 10.

Next, the data for each frame read out by the traceback is stored once in the output buffer circuit 24 and rearranged on the time axis, that is, rearranged in the original order, and then the received data is output. Output from terminal 12.

In this embodiment, in the Viterbi decoder,
Instead of tracing back the number of truncation depths during one decoding cycle, the entire frame length is traced back during the period of one frame, so the number of tracebacks required to output 1 bit of decoded data is only once. Good. As a result, the decoding data rate can be greatly increased, and an error correction method with a high transmission rate can be realized.

Further, according to the present embodiment, since the traceback is always started from the state corresponding to the end of the code, it is not necessary to find the maximum likelihood state, and there is an effect that the maximum likelihood state detection circuit, which has conventionally been large in hardware scale, can be omitted. .

In the above embodiment, the method of multiplexing with the frame synchronization pattern by the rate conversion (multiplexing) circuit immediately after the convolutional encoder is shown. However, an interleave circuit is provided after the convolutional encoder to prevent a burst error in the transmission line. In contrast, strong error correction may be possible. This is particularly effective because the conventional convolutional coding / Viterbi decoding is susceptible to deterioration due to burst errors in the transmission path. In this case, on the receiving side in FIG. 2, a circuit for deinterleaving according to the frame synchronization pulse from the frame synchronization circuit is provided after the demodulator.

〔The invention's effect〕

As described above, according to the present invention, on the transmission side, the register of the convolutional encoder is reset at the start of the frame, dummy data is added at the end, and the convolutional encoding is completed for each frame. On the receiving side, a circuit for calculating branch metrics of all states based on the coded data actually received by the Viterbi decoder and the coded data that can be taken by the convolutional coding means of the transmitter, and the branch The branch metric value of the metric calculation circuit and the metric value of the state before the transition to the relevant state are added to calculate the metric value in the relevant state, and if there are multiple states before the transition to the relevant state, An ACS circuit that compares addition results and selects the smallest metric value as the metric value in this state, and the result of addition, comparison, and selection that is the output of the ACS circuit can be stored for one frame. 2 path memory circuits are provided, the roles of writing and traceback are alternated for each frame, and data for one frame is traced back over the entire length of one frame during one frame period. The number of tracebacks to be performed on the memory while decoding all data for one frame is one, which dramatically increases the decoding speed, and since the maximum likelihood state detection circuit can be omitted, the hardware scale is reduced. There is an effect that a small error correction method can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a transmission side of an error correction system according to an embodiment of the present invention, FIG. 2 is a block diagram showing its reception side, and FIG. 3 is a block diagram showing a transmission side of a conventional error correction system. , FIG. 4 is a block diagram showing the receiving side, FIG. 5 is a block diagram of a convolutional encoder with a rate 1 / n, constraint length k, and FIG. 6 is a convolutional code with a rate 1/2, K = 3. Block diagram of the vessel,
FIG. 7 is a trellis diagram of a rate 1/2, K = 2 convolutional encoder, FIG. 8 is a diagram showing an example of transmission symbols and reception symbols, and FIG. 9 is a trellis diagram for explaining the Viterbi decoding method. Fig. 10 shows an example of the rate in the method of the present invention.
It is a trellis diagram showing the state transition for 1 frame of the convolutional encoder of 1/2, constraint length 3. 2 ... Velocity conversion (multiplexing) circuit, 3 ... Frame synchronization pattern generation circuit, 4 ... Convolutional encoder, 5 ... Modulator, 8
…… Demodulator, 10 …… Branch metric calculation circuit, 11 …… ACS
Circuit, 15 ... Frame synchronization circuit, 21, 22 ... Path memory circuit, 23 ... Traceback control circuit, 24 ... Output buffer circuit, 25 ... Viterbi decoder, 31 ... Control circuit. The same reference numerals in the drawings indicate the same or corresponding parts.

Continuation of the front page (56) References JP-A-63-78439 (JP, A) JP-A-62-233933 (JP, A) US Patent 4583078 (US, A) International Publication 87-6081 (WO, A) COMSAT TECHNICAL R EVIEW VOLUME 13 NUMBE R2, (1983) "Serial implmentation of Viter bi decoders" P. 315-330; A. SHENOY, P.M. JOHNSON

Claims (2)

[Claims] 1. An error correction device for use in continuous mode digital communication, comprising convolutional coding means for performing convolutional coding by dividing transmission data into frames, and at the time of starting a frame at the time of convolutional coding. Control means for setting an initial value of a register of the convolutional coding means and inserting dummy data indicating the end of the frame at the end time of the frame; convolutional code for each frame output from the convolutional coding means Frame pattern inserting means for inserting a frame pattern into the converted data; frame generating means for supplying frame timing to the control means and frame pattern inserting means; and a modulating means for modulating a carrier wave by the output of the frame pattern inserting means. And a demodulation means for demodulating the original baseband signal from the received modulated wave. Frame synchronization means for establishing frame synchronization connected to the adjustment means, and between the states based on the actually received encoded data and the encoded data that can be taken by the convolutional encoding means of the transmitter. Before the transition to the relevant state, the circuit that calculates the branch metric, the branch metric value of the branch metric calculation circuit, and the metric value of the state before the transition to the relevant state are added to calculate the metric value in the relevant state When there are a plurality of states, an addition, comparison, and selection circuit (Add Compare Select, hereinafter referred to as ACS circuit) that further compares each addition result and selects the smallest metric value as the metric value in that state, One of the first and second path memory circuits capable of storing the addition, comparison, and selection results output from the ACS circuit for one frame, and one of the two path memory circuits in a certain frame period. One side stores the addition, comparison, and selection results output from the ACS circuit for one frame, and all the addition, comparison, and selection data for one frame before stored in the other path memory circuit during the period. Traceback in the above state, and in the next frame period, the traceback control circuit that alternates the roles of these two path memory circuits and the time order of the decoded data for each frame obtained by this traceback are rearranged and output. An error correction device comprising: a receiving device including a Viterbi decoder having an output buffer circuit. 2. The transmitting apparatus is provided with an interleaving means for interleaving data in each frame in an appropriate order between the convolutional coding means and the frame pattern inserting means, and in the receiving apparatus, Deinterleaving means is provided between the demodulation means and the Viterbi decoder for deinterleaving data in each frame in the original order according to a frame synchronization pulse output from the frame synchronization means. The error correction device according to claim 1.