JP3267581B2 - Frame synchronization method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to frame synchronization, and more particularly, to a simple frame synchronization method and apparatus in a multi-frame configuration.

[0002]

2. Description of the Related Art In recent wireless communication systems, error correction techniques are often used to improve transmission quality.
In particular, among error correction techniques, a technique using a block code is widely adopted due to easiness of a circuit and the like. When such an encoding technique is employed, in order to prevent erroneous synchronization of words in blocks (hereinafter, referred to as “words”), a specific bit is inverted with respect to an encoded signal. There are times when measures are taken.

On the other hand, overhead bits are added to a transmission signal in order to transmit an auxiliary signal and information necessary for operating the line in a multiplexed manner on a main line. In many cases, a multi-frame configuration that configures a line without deteriorating the transmission efficiency of the line is used by making the frame a multi-configuration according to the capacity and capacity. However, when a multi-frame configuration is adopted, it is necessary to establish synchronization of the multi-frames in order to recognize a plurality of frames as one group and to recognize the delimiter.

[0004]

In a system that handles transmission signals of a multi-frame configuration that requires two functions, word synchronization and multi-frame synchronization, the use of dedicated synchronization bits in each system reduces transmission efficiency. There are drawbacks. In addition, there is a disadvantage in that the configuration of preparing circuits corresponding to the respective functions increases the scale of the device.

(Object of the Invention) It is an object of the present invention to provide a method and apparatus for synchronizing a frame having a multi-frame structure with high transmission efficiency.

Another object of the present invention is to provide a method and apparatus for synchronizing frames in a digital radio communication system having a multi-frame configuration with high transmission quality using block codes.

[0007]

SUMMARY OF THE INVENTION A frame synchronization method according to the present invention is a frame synchronization method for a multi-frame composed of a plurality of words in a block code unit in which error correction is performed using a block code. By inverting the bit at a different position for each word with respect to the signal after block encoding, the signal is transmitted as a multi-frame transmission signal, and the receiving side divides the received signal by a polynomial according to the block code. The obtained syndrome pattern is sequentially corrected to remove the effect on the syndrome pattern due to bit inversion according to the bit inversion position of each word, and the corrected syndrome pattern is free from errors due to bit inversion. The pattern correction is controlled so as to establish multi-frame synchronization.

According to the frame synchronization system of the present invention, in a multi-frame frame synchronization system composed of a plurality of words in a block code unit in which error correction is performed using a block code, a transmitting side converts an input signal into a block code. And a bit inverting circuit for inverting a bit at a different position for each word with respect to the signal after block encoding and transmitting the inverted signal as a multi-frame transmission signal. A division circuit that divides by a polynomial according to the block code to output a syndrome pattern; a syndrome pattern correction circuit that corrects the syndrome pattern obtained from the division circuit with a correction pattern; The correction pattern for each word that removes the effect on the syndrome pattern A pattern correction control circuit that outputs to the correction circuit, and a synchronization detection circuit that controls the pattern correction control circuit and establishes multi-frame synchronization so that a state in which there is no error due to bit inversion in the corrected syndrome pattern is detected. It is characterized by having.

The frame synchronization apparatus according to the present invention comprises a plurality of words in a block code unit for performing error correction using a block code, and inverts bits at different positions for each word in a signal after block coding. A frame synchronization device for a multi-frame transmitted as a transmission signal, a division circuit that divides a reception signal by a polynomial according to the block code and outputs a syndrome pattern;
A syndrome pattern correction circuit that corrects the syndrome pattern obtained from the division circuit with a correction pattern, and the correction pattern for each word that removes an effect on the syndrome pattern according to the bit inversion position is sent to the syndrome pattern correction circuit. A pattern correction control circuit for outputting, and a synchronization detection circuit for controlling the pattern correction control circuit so as to detect a state in which no error due to bit inversion is detected in the corrected syndrome pattern, thereby establishing multi-frame synchronization. It is characterized by.

In the frame synchronization apparatus, the output of the syndrome pattern by the division of the division circuit is the same as that of the received signal until the synchronization detection circuit detects a state where there is no code error in the corrected syndrome pattern. It is performed every bit, and when the synchronization detection circuit detects a state in which there is no error due to bit inversion in the corrected syndrome pattern, the detection is performed every one word of the received signal. Until the synchronization detection circuit detects a state in which there is no error due to bit inversion in the corrected syndrome pattern, a predetermined correction pattern is fixed and output, and the synchronization detection circuit outputs a bit of the corrected syndrome pattern to the corrected syndrome pattern. A multi-frame word-order correction pattern is sequentially output each time an error-free state is detected. It is characterized in. (Operation) In a digital radio communication system having an error correction function using a block code, in order to recognize each word as a multi-frame, an arbitrary position different for each word with respect to the signal after block coding on the transmission side. Performs bit inversion to invert the bits of the received signal, and performs control to correct the syndrome pattern obtained from the received signal according to the bit inversion position of each word on the receiving side, and inverts the bits to the corrected syndrome pattern. The multi-frame synchronization is established by making no error due to.

More specifically, on the transmission side of the radio system, after an input signal is subjected to error correction coding by a coding circuit, a bit from a different position for each word in the same multi-frame is input by a signal from a bit inversion control circuit. Is inverted by a bit inversion circuit, and on the receiving side of the wireless system, the received signal is temporarily stored in a memory circuit, and a syndrome obtained from a division circuit that performs division by a generator polynomial according to the adopted block code. The pattern is corrected by the syndrome pattern correction circuit. This correction is to remove the influence on the syndrome pattern due to the bit inversion operated by the bit inversion circuit on the transmission side, and the position of the inversion bit different for each word controlled by the bit inversion control circuit on the transmission side. By the pattern correction control circuit according to
A synchronization detection circuit establishes multi-frame synchronization.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Explanation of Configuration) An embodiment of a frame synchronization method and apparatus according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the frame synchronization circuit of the present invention. The present embodiment is roughly divided into two parts, a transmitting side and a receiving side.
The transmitting side includes an encoding circuit 11, a bit inversion circuit 12,
And a bit inversion control circuit 13. The receiving side includes a memory circuit 21, a division circuit 22, a syndrome pattern correction circuit 23, and a pattern correction control circuit 24.
, A synchronization detection circuit 25, and a decoding circuit 26. The outline of the functions of the transmitting side and the receiving side is as follows.

On the transmitting side, an encoding circuit 11 performs an encoding for performing an error correction on the input signal 101 using a block code. Since the adopted code is a block code,
The encoding circuit 11 outputs a signal having a delimiter for each block (word) as an encoded signal, and outputs a word timing signal 103 indicating a delimiter of a word. The bit inversion circuit 12 performs an operation of inverting a bit at a different position for each word on the encoded signal output from the encoding circuit 11 based on a control signal from a bit inversion control circuit 13 described later. By doing
Transmission signal 1 of multi-frame configuration composed of a plurality of words
Output as 02. The bit inversion control circuit 13 outputs a word timing signal 103 output from the encoding circuit 11.
, A signal indicating the position of the bit to be inverted by the bit inversion circuit 12 for each word is output to the bit inversion circuit 12, and the configuration of the multi-frame is controlled.

On the receiving side, the memory circuit 21 receives the received signal 201 and temporarily stores it. Division circuit 22
Is the received signal 2 according to a predetermined generator polynomial.
01 is divided for each word, and the remaining syndrome pattern is output. The syndrome pattern correction circuit 23 corrects the syndrome pattern determined by each inverted bit position in order to remove the influence on the syndrome pattern due to the bit inversion operated by the bit inversion circuit 12 on the transmission side. The pattern correction control circuit 24 needs to perform correction in accordance with the position of the inverted bit that is different for each word controlled by the bit inversion control circuit 13 on the transmission side. Based on the frame timing signal 203 which is a multi-frame timing signal from the detection circuit 25, the correction pattern is switched and output for each word. The synchronization detection circuit 25 includes a syndrome pattern correction circuit 23.
It detects whether or not the word synchronization and the multi-frame synchronization have been established based on the syndrome pattern 202 after the correction, and generates and outputs the frame timing signal 203 when the multi-frame synchronization is established. Is detected, the decoding circuit 2 described later
6 to output an error correction control signal 204. Decoding circuit 2
6 executes error correction on the signal stored in the memory circuit 21 based on the error correction control signal 204 and decodes the signal.

(Explanation of Operation) Next, the operation of the present embodiment will be described using an example of a specific multi-frame configuration. FIG. 2 is a diagram illustrating a multi-frame configuration including two words as an example of the multi-frame. Here, each word is composed of n bits (n is an integer), and the first word is the i-th word (i is 1 ≦ i ≦ (n
The operation of the multi-frame configuration will be described, assuming that the (integer satisfying -1) bit is inverted and the (i + 1) th bit is inverted in the second word.

First, on the transmitting side, the bit inversion control circuit 1
3 alternately for each word based on the word timing signal 103 output from the encoding circuit 11.
A control signal for inverting the (+1) th bit is output to the bit inversion circuit 12. As a result, the transmission signal 102 output from the bit inversion circuit 12 is multi-framed as a signal in which an error is added to a predetermined position for each bit for each encoded word.

Next, on the receiving side, the received signal 201 transmitted from the wireless transmission path is input to the memory circuit 21 and also to the division circuit 22. Here, it is assumed that no error has occurred on the wireless transmission path, and that the word division is correct, that is, the word synchronization has been established, the syndrome for each word output from the division circuit 22 is output. The pattern is either a pattern indicating that the i-th bit is incorrect due to an operation in the bit inverting circuit 12 on the transmission side, or a pattern indicating that the (i + 1) -th bit is incorrect.

The pattern correction control circuit 24 has two types of correction patterns for correcting the two types of syndrome patterns output from the division circuit 22 by the bit inversion on the transmission side into correct patterns, and has a certain word. At this point, the correction pattern is output to one of the syndrome pattern correction circuits 23 of the two types of correction patterns. The synchronization detection circuit 25 detects whether or not the output of the syndrome pattern correction circuit 23 is all "0" for each word.
Frame timing signal 2 only when the state of
03 is output. When the frame timing signal 203 is input, the pattern correction control circuit 24 outputs the two types of correction patterns to the other syndrome pattern correction circuit 23 at the time of the next word. The synchronization detection circuit 25 detects whether or not the output of the syndrome pattern correction circuit 23 is all "0" for each word.
3 is output. The pattern correction control circuit 24 as described above
Are performed alternately, the synchronization detection circuit 25
The word synchronization and the multi-frame synchronization are simultaneously detected, and an error for each word is detected from the division operation result of each word, and an error correction control signal 204 is output to the decoding circuit 26.

As described above, the correction pattern when the i-th bit is wrong and the correction pattern when the (i + 1) -th bit is wrong are alternately output from the pattern correction control circuit 24, and the syndrome is output. The synchronization detection circuit 25 detects from the output of the pattern correction circuit 23 whether or not a state of "0", which indicates that the syndrome pattern 202 is "error free", is transmitted as a result. Each incoming word is the first in a multiframe.
It can be determined whether the word is the second word or the second word, and multi-frame synchronization can be established. When the multi-frame synchronization is established, the frame timing signal 203 is continuously output from the synchronization detection circuit 25 for each word, and the operations of the division circuit 22 and the pattern correction control circuit 24 are performed as described above. Is controlled.

Next, a state in which word synchronization indicating the delimitation of each word is established but multiframe synchronization is not established, that is, each word is the first word or the second word. The operation of establishing multi-frame synchronization when it is not determined whether or not there is a frame will be described.

First, when the synchronization of the multi-frame is not established, the correction pattern output from the pattern correction control circuit 24 is fixed to one correction pattern. Here, the i-th word corresponding to the first word
It is assumed that the correction pattern to be output is fixed and output when the ith bit is incorrect.

If the divider 22 outputs a syndrome pattern for the second word in a state where the correction pattern is fixed, that is, a pattern indicating that the (i + 1) th bit is incorrect, the pattern correction control is performed. Since the correction pattern in the case where the first bit is incorrect is output from the circuit 24, the syndrome pattern 202 after the correction by the syndrome pattern correction circuit 23 indicates "no error". “0”
It does not become the state of.

Therefore, in this word, the synchronization detection circuit 2
5, the frame timing signal is not output, and the output of the pattern correction control circuit 24 remains fixed and waits for the next division result. Since the next division result is the division result for the first word of the next multiframe, a pattern indicating that the i-th bit is incorrect is output, and the pattern correction control circuit 24 outputs i
Since the correction pattern in the case where the second bit is incorrect is output, the syndrome pattern 202 as the output result of the syndrome pattern correction circuit 23 is all “0” indicating “no error”.

Here, for the first time, the synchronization detection circuit 25 determines that the first word has been detected, outputs a frame timing signal 203, releases the fixed state of the pattern correction control circuit 24, and On the basis of this, the correction pattern is switched to a correction pattern corresponding to the bit inversion of the subsequent word. Thereafter, the syndrome pattern 202 as an output result of the syndrome pattern correction circuit 23 for each word continues to be all “0” indicating “no error”.
, The multi-frame timing signal is continuously output to establish synchronization.

In the above embodiment, the operation of establishing multi-frame synchronization according to the present invention has been described as an operation in a state where word synchronization is established by a specific method. As an example of the operation, a commonly used hunting operation can be applied.

That is, the operation of the division circuit 22 is performed every time one bit of the received signal elapses, and a hunting operation is performed in units of 1 bit so as to detect word synchronization from the division result.
Frame timing signal 203 from synchronization detection circuit 25
Establishes word synchronization. In this case, after the word synchronization is established, the division operation is performed by the division circuit every time one word elapses, and the above-described operation of establishing the multiframe synchronization is performed, so that the synchronization operation is changed from the word synchronization to the multiframe synchronization. It can be configured to perform switching. Further, by performing the division operation of the division circuit 22 every bit, and detecting the synchronization state by the detection circuit 25, the hunting operation of bit unit synchronization can be performed without separating the word synchronization operation and the multi-frame synchronization operation. It can be configured to perform until multi-frame synchronization can be established. According to this method, synchronization is established in the synchronization detection circuit 25 by a hunting operation for a period of up to one multiframe.
Even in this case, since the frame timing signal is continuously output from the synchronization detection circuit 25 after the synchronization is established,
It goes without saying that the division circuit 22 can be configured to output the division result at the timing of the original word break after the continuous output of the frame timing signal.

Further, in the above embodiment, an example in which two words are used as a multi-frame configuration has been described. However, it is clear that a multi-frame configuration including three or more words can be used. In this case, it is needless to say that the above-described technical method for establishing synchronization of word synchronization and multi-frame synchronization according to the present invention can be applied. As a form of bit inversion on the transmission side in such a multi-frame configuration, the i-th bit is inverted for the first encoded word, and the bits at different positions are sequentially inverted for the second and subsequent words. Can be configured. The second and subsequent bits can be configured to invert the (i + 1) th bit up to the last word of the multiframe.

In any case, the synchronization of the multi-frame
It is possible to apply the method described above. That is, in the former case, in the pattern correction control circuit 24, the synchronization detection is performed by the synchronization detection circuit using the correction pattern corresponding to the i-th and subsequent one inverted word, and the synchronization state is detected. Sometimes, a frame timing signal is output to cancel the correction pattern of the pattern correction control circuit 24. In the latter case, the i-th
The correction pattern corresponding to either the inversion word of the i-th bit or the inversion word of the (i + 1) -th bit is set to a fixed state, and the correction pattern is obtained from the detection result of the synchronization detection circuit 25 according to the known number of words in one frame. It can be configured to release the fixed state of the pattern and establish synchronization.

In the above embodiment, it is assumed that no error has occurred on the transmission line. However, an error may actually occur. It goes without saying that the above operation is performed by detecting whether there is no error due to inversion.

[0030]

As described above, according to the present invention,
Since word synchronization is performed in units of block encoding, and a multi-frame is realized by inverting bits at different positions for each word using a bit inversion function to prevent erroneous synchronization. Since it is not necessary to add special information for word synchronization and multi-frame synchronization, it is possible to improve transmission efficiency in addition to improving transmission quality by block coding.

Further, the size of an additional circuit for the synchronization function can be reduced, and a multi-frame synchronization apparatus and a digital radio communication system can be realized with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a frame synchronization circuit of the present invention.

FIG. 2 is a diagram showing an example of a time chart illustrating an operation of the present embodiment.

[Explanation of symbols]

 Reference Signs List 11 encoding circuit 12 bit inversion circuit 13 bit inversion control circuit 21 memory circuit 22 division circuit 23 syndrome pattern correction circuit 24 pattern correction control circuit 25 synchronization detection circuit 26 decoding circuit 101 input signal 102 transmission signal 103 word timing signal 201 reception Signal 202 Syndrome pattern 203 Frame timing signal 204 Error correction control signal

Continuation of front page (56) References JP-A-5-122210 (JP, A) JP-A-4-208735 (JP, A) JP-A-5-336100 (JP, A) JP-A-5-327645 (JP) JP-A-5-336099 (JP, A) JP-A-2-35841 (JP, A) JP-A-63-10837 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H04L 7/08 H03M 13/00 H04J 3/06

Claims (5)

(57) [Claims] In a method of synchronizing a multi-frame composed of a plurality of words in a block code unit in which error correction is performed using a block code, a transmitting side transmits a signal after block encoding to each word. Are transmitted as a multi-frame transmission signal by inverting the bits at different positions, and the receiving side divides the reception signal by a polynomial according to the block code, and obtains the obtained syndrome pattern for each word. Correction for removing the effect of the bit inversion on the syndrome pattern is sequentially performed in accordance with the bit inversion position, and the pattern correction is controlled so that the corrected syndrome pattern has no error due to the bit inversion. A frame synchronization method characterized by establishing frame synchronization. 2. A multi-frame frame synchronization system comprising a plurality of words in a block code unit in which error correction is performed using a block code, wherein a transmitting side includes an encoding circuit for performing block encoding of an input signal. A bit inversion circuit for inverting bits at different positions for each word with respect to the signal after block encoding and transmitting the inverted signal as a multi-frame transmission signal, wherein the reception side converts the reception signal according to the block code. A division circuit that divides by a polynomial to output a syndrome pattern, a syndrome pattern correction circuit that corrects the syndrome pattern obtained from the division circuit with a correction pattern, and an effect on the syndrome pattern according to the bit inversion position. For outputting a correction pattern for each word for removing the noise to the syndrome pattern correction circuit. A correction control circuit, and a synchronization detection circuit that controls the pattern correction control circuit so as to detect a state in which no error due to bit inversion is detected in the corrected syndrome pattern and establishes multi-frame synchronization. Frame synchronization method. 3. A signal composed of a plurality of words in a block code unit in which error correction is performed using a block code, and inverting a bit at a different position for each word with respect to a signal after block encoding, and transmitting the inverted signal as a transmission signal. A frame synchronization device for multi-frames, wherein a division circuit that divides a received signal by a polynomial according to the block code and outputs a syndrome pattern, and corrects the syndrome pattern obtained from the division circuit with a correction pattern. A syndrome pattern correction circuit,
A pattern correction control circuit that outputs a correction pattern for each word that eliminates the effect on the syndrome pattern according to the bit inversion position to the syndrome pattern correction circuit, and a state in which the corrected syndrome pattern has no error due to bit inversion. A synchronization detection circuit for controlling the pattern correction control circuit so as to be detected to establish multi-frame synchronization. 4. The output of the syndrome pattern by the division of the division circuit is performed every one bit of the received signal until the synchronization detection circuit detects a state in which there is no error due to bit inversion in the corrected syndrome pattern. 4. The frame synchronization apparatus according to claim 3, wherein when the synchronization detection circuit detects a state in which there is no error due to bit inversion in the corrected syndrome pattern, the detection is performed every time one word of the received signal elapses. 5. The pattern correction control circuit fixes and outputs a predetermined correction pattern until the synchronization detection circuit detects a state in which there is no error due to bit inversion in the corrected syndrome pattern. 5. The frame synchronization device according to claim 4, wherein each time the circuit detects a state in which the corrected syndrome pattern has no error due to bit inversion, the correction pattern is sequentially output in a multi-frame word order.