JP2000201123A - Multidirectional time-division multiplex radio data communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a multidirectional time-division multiplex radio data communication device capable of reducing the influence of a bit error in transmission data even when the bit error is caused due to interference or the like generated in a radio section. SOLUTION: A continuous signal SIG1 is converted into a burst signal by a continuous/burst signal conversion circuit 21, the burst signal is sent to a multiplex circuit 25, the signal SIG1 is simultaneously corrected at its error by an error correction encoding circuit 23 and an error correcting redundant bit is sent to the circuit 25. When the circuit 25 multiplexes the burst signal with a specific time slot, multiplexes the error correcting redundant bit with the slot and sends a burst signal SIG2 to a burst/continuous signal conversion circuit 31, the circuit 31 converts the burst signal SIG2 into a continuous signal and inputs the continuous signal to a division circuit 33, which outputs a syndrome to an error position detection circuit 34. An addition circuit 36 executes bit inversion for a bit on a specified bit error generation position out of the continuous signal, based on the syndrome and outputs the bit-inverted continuous signal to a data terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-point communication system in which radio time slots to be used are fixedly allocated between a master station device and a slave station device, and data communication is performed between data terminal devices connected to those devices. In a time-division multiplexing wireless data communication system, even if a bit error occurs in a transmitted data signal due to interference or fading occurring in a wireless section, multi-directional time-division multiplexing can greatly reduce the effect. The present invention relates to a wireless data communication device.

[0002]

2. Description of the Related Art Generally, in a radio system for performing multi-directional multiplex communication, 1: N time-division multiplex communication is performed between one master station and a plurality of slave stations facing the master station. . At this time, especially in a system in which telephone communication and data communication coexist, with respect to telephone communication, a wireless communication channel is established between the master station device and the slave station device only when a call is generated in the master station device or the slave station device. Channel assignment control is performed by a demand assignment method. Regarding data communication, a wireless communication channel for performing data communication between a data terminal connected to a master station and a data terminal connected to a slave station opposite to the data terminal is fixed in advance. , Channel allocation control is performed by a pre-assignment method.

[0005] That is, in FIG. 5, a multi-way time-division multiplexing wireless data communication system includes a master station apparatus 1 and a plurality of data terminal apparatuses 1 a, 1 b, 1 c connected to the master station apparatus 1.
And a plurality of slave station apparatuses 10 and 1 wirelessly opposed to the master station apparatus 1.
1 and 12 and data terminal apparatuses 10a, 11a and 12a connected to the respective slave station apparatuses 10, 11 and 12. Data communication is performed by the TDM method in the down direction from the master station device 1 to the slave station devices 10, 11, and 12, and by the TDMA method in the up direction from the slave station devices 10, 11, and 12 to the master station device 1.

Here, the data terminal device 1a and the data terminal device 10a, the data terminal device 1b and the data terminal device 11
a, the operation when the data terminal device 1c and the data terminal device 12a face each other and perform data communication will be described. First, a radio time slot to be used as a radio communication channel is fixedly allocated in advance to each of the opposing data terminal devices. That is, as shown in FIG. 6, the wireless time slot TS0 for the data terminal device 1a and the data terminal device 10a, the wireless time slot TS1 for the data terminal device 1b and the data terminal device 11a,
A wireless time slot TS2 is fixedly assigned to each of the data terminal device 1c and the data terminal device 12a.

[0005] As shown in FIG.
The S0, the radio time slot TS1, and the radio time slot TS2 are allocated to different positions that do not overlap with each other on the time axis, and signals transmitted using the respective radio time slots do not collide. When a call is made to any of the data terminal devices in the system, since a wireless time slot is allocated to each data terminal device, it is inevitable to perform data communication with the opposite data terminal device. It has a configuration that can be performed.

For data transmission in the downlink direction, the data terminal device 1a, the data terminal device 1b, and the data terminal device 1
c is input to the master station device 1,
After being multiplexed by the master station device 1, the multiplexed data signal is transmitted to the slave station device 10, the slave station device 11, and the slave station device 12 using the TDM method. That is, the data terminal device 1
The data signal from a is multiplexed into the radio time slot TS0, the data signal from the data terminal device 1b is multiplexed into the radio time slot TS1, and the data signal from the data terminal device 1c is multiplexed into the radio time slot TS2. The multiplexed burst data signal is transmitted to each of the slave station apparatuses 10, 11, and 12.

[0007] All the same signals are transmitted to each of the slave station devices 10, 11 and 12. Each of the slave station devices 10, 11, and 1 separates and selects only the data signal addressed to itself, extracts the data signal, and connects to the connected data terminal device 1.
Data signals are sent to 0a, 11a and 12a. That is, the data signal multiplexed in the radio time slot TS0 is separated by the slave station device 10 to the data terminal device 10a, and the data signal multiplexed in the radio time slot TS1 is separated by the slave station device 11 to the data terminal device 11a. The data signal multiplexed in the radio time slot TS2 is
2 and transmitted to the data terminal device 12a.

[0008] Regarding the data transmission in the up direction, the data terminal device 10 connected to the slave station devices 10, 11, 12
a, 11a, and 12a transmit data signals from the slave station devices 10,
At 11 and 12, the signals are multiplexed to the assigned radio time slots, and are transmitted to the master station device 1 as burst signals using the TDMA method. That is, the data signal from the data terminal device 10a is input to the slave station device 10, multiplexed into the radio time slot TS0, and transmitted to the master station device 1. Similarly, a data signal from the data terminal device 11a is input to the slave station device 11 and multiplexed into the radio time slot TS1. The data signal from the data terminal device 12a is input to the slave station device 12, multiplexed into the radio time slot TS2, and transmitted to the master station device 1, respectively.

In the master station device 1, each of the slave station devices 10, 11,.
The data signals from the data terminals 12 are separated and taken out, and the corresponding data signals are transmitted to the connected data terminal devices.
That is, the data signal multiplexed in the radio time slot TS0 is transmitted to the data terminal device 1a by the radio time slot T0.
The data signal multiplexed on S1 is sent to the data terminal 1b.
The data signal multiplexed in the radio time slot TS2 is transmitted to the data terminal device 1c. For convenience of explanation, in FIG. 5, the number of slave station devices is 3, the number of data terminal devices connected to each slave station device is 1, and circuits and signal lines that are not particularly important are omitted. It is clear that the same operation is performed when the number of slave station devices is other than three and when a plurality of data terminal devices are connected to one slave station device.

Here, the one-way data transmission operation will be further described. Conventionally, a multi-directional time-division multiplexing wireless data communication device shown in FIG. 7 is well known as this kind of technology. In FIG. 7, at one station, a low-speed continuous signal SIG1 input from the data terminal device {FIG.
(A) is input to the continuous / burst signal conversion circuit 21 based on the timing signal generated by the timing signal generation circuit 22, where the data is stored. The timing signal generation circuit 22 outputs the continuous signal SIG1
A timing signal required when the continuous signal SIG1 is periodically input to the continuous / burst signal conversion circuit 21 from the clock signal synchronized with the above.

The data stored in the continuous / burst signal conversion circuit 21 is read out based on a timing signal generated by a timing signal generation circuit 24, and is read as a high-speed burst signal SIG2 {FIG. Sent to When the timing signal generation circuit 24 periodically reads data stored in the continuous / burst signal conversion circuit 21 from a clock signal synchronized with the high-speed burst signal SIG2 on the wireless side in units of bits required for unit burst data. To generate the necessary timing signals. That is, the timing relationship between the low-speed continuous signal SIG1 and the high-speed burst signal SIG2 is as shown in FIG.
8A and FIG. 8B.

Next, at the other station, the burst signal SIG2 transmitted from the one station is received by the burst / continuous signal conversion circuit 31 as a burst signal SIG3 {FIG. Then, based on the timing signal generated by the timing signal generation circuit 32, it is input to the burst / continuous signal conversion circuit 31, where the data is stored. The timing signal generation circuit 32 determines the timing required when the burst signal SIG3 is periodically input to the burst / continuous signal conversion circuit 31 from the clock signal synchronized with the burst signal SIG3 in units of the number of bits required for the unit burst data. It generates a signal. The data stored in the burst / continuous signal conversion circuit 31 is read out based on the timing signal generated by the timing signal generation circuit 35 and output to the data terminal device as a low-speed continuous signal SIG4 {FIG. 8 (d)}. Is done.

The timing signal generating circuit 35 generates a timing signal necessary for periodically reading data stored in the burst / continuous signal conversion circuit 31 from a clock signal synchronized with the low-speed continuous signal SIG4. is there. That is, the timing relationship between the high-speed burst signal SIG3 and the low-speed continuous signal SIG4 is shown in FIGS.
The relationship shown in FIG. Regarding the above description, the same operation is performed without distinction between the direction from the master station device to the slave station device and the direction from the slave station device to the master station device.

[0014]

The above-mentioned conventional multi-way time-division multiplexing wireless data communication apparatus performs only rate conversion between low-speed continuous data on the data terminal apparatus side and high-speed burst data on the wireless section side. Since data transmission is performed through the wireless section, when interference or fading occurs, the data transmission is directly affected, and a bit error occurs in a transmitted data signal. As a result, an erroneous data signal appears on a data communication line. There is a problem of being transmitted. Note that Japanese Patent No. 2751751 (wireless communication system) includes:
As means for transmitting the interleave period signal from the transmitting side to the receiving side, it is described that a means for transmitting an ID based on the presence or absence of bit inversion for each codeword is provided in units of N codewords. There is no suggestion about a solution for improving the influence of interference or fading in such a wireless section.

The present invention has been made to solve the above-mentioned conventional problems, and does not require a speed conversion circuit accompanying the addition of redundant bits, and does not require a word synchronization circuit for error correction decoding on the receiving side. In addition, it is possible to selectively use the presence or absence of error correction according to the type of signal to be transmitted.Furthermore, even if burst-like interference occurs in the radio section and continuous bit errors occur in the data signal, error correction can be performed. In addition to greatly reducing the effect on the data communication line due to continuous bit errors when performing processing, even when accommodating multiple subscribers in the same time slot, the error correction effect can be adjusted and overall It is an object of the present invention to provide a multi-way time-division multiplexed wireless data communication device capable of economically improving transmission quality.

[0016]

To achieve the above object, a multi-way time division multiplexed wireless data communication apparatus according to the present invention converts a continuous signal input from a data terminal into a burst signal at one station. A continuous / burst signal conversion circuit, an error correction coding circuit for performing error correction coding of the continuous signal, and a specific time slot of a specific frame on a radio multiplex frame which converts the burst signal converted by the continuous / burst signal conversion circuit. And a multiplexing circuit for multiplexing the redundant bits for error correction generated by the error correction coding circuit into a specific empty slot on the radio multiplex frame and transmitting a burst signal. A burst / continuous signal conversion circuit for converting a burst signal multiplexed by the multiplexing circuit into a continuous signal on the station side; A division circuit for performing an operation on a bit sequence constituting an error correction code in the continuous signal converted by the continuous signal conversion circuit with a determined polynomial to generate a syndrome for the error correction code; and the division circuit An error position detection circuit for specifying a position where a bit error has occurred in the continuous signal converted by the burst / continuous signal conversion circuit based on the syndrome generated by the burst / continuous signal conversion circuit; An adder circuit for performing bit inversion on a bit in which an error has occurred in the signal and outputting a continuous signal to the data terminal.

According to the present invention, in one station, the continuous / burst signal conversion circuit converts the continuous signal input from the data terminal into a burst signal, and this continuous signal is also input to the error correction coding circuit. Then, error correction is performed by the error correction coding circuit. The burst signal converted from the continuous signal by the continuous / burst signal conversion circuit and the redundant bits for error correction generated by the error correction encoding circuit are sent to the multiplexing circuit. In the multiplexing circuit, a burst signal is multiplexed in a specific time slot of a specific frame on a radio multiplex frame, and redundant bits for error correction are multiplexed on a specific empty slot on the radio multiplex frame to output a high-speed burst signal. I do.

On the opposite station side to one station, when a high-speed burst signal is input to the burst / continuous signal conversion circuit, the burst is converted into a continuous signal, and this continuous signal is sent to a division circuit. . The division circuit performs an operation on a continuous signal using a predetermined polynomial for a bit sequence constituting an error correction code in the continuous signal, generates a syndrome for the error correction code, and sends the syndrome to the error position detection circuit. The error position detection circuit performs burst /
A position where a bit error has occurred in the continuous signal converted by the continuous signal conversion circuit is specified. An error occurs in the continuous signal converted by the burst / continuous signal conversion circuit. The bit at the specified position is bit-inverted by the addition circuit, and the continuous signal is output to the data terminal.

Therefore, according to the present invention, a speed conversion circuit for adding redundant bits is not required, and a word synchronization circuit for error correction decoding on the receiving side is not required.
Depending on the type of signal to be transmitted, it is possible to selectively use the presence or absence of error correction.Furthermore, even when continuous bit errors occur in the data signal due to bursty interference occurring in the radio section, error correction processing is performed. In addition to greatly reducing the effect on the data communication line due to consecutive bit errors, even when accommodating multiple subscribers in the same time slot, the error correction effect can be adjusted for each subscriber, It is possible to economically improve transmission quality.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a multi-way time-division multiplex wireless data communication apparatus according to an embodiment of the present invention. FIG. 1 is a block diagram showing the configuration of the first embodiment according to the present invention. In this FIG.
The same parts as those in FIG. First,
Prior to the description of specific embodiments, an outline of the present invention will be described.

In FIG. 1, in one station, a continuous signal SIG1 input from a data terminal device (not shown) is converted into a burst signal by a continuous / burst signal conversion circuit 21 and, at the same time, error correction is performed by an error correction encoding circuit 23. Perform encoding. The multiplexing circuit 25 multiplexes the burst signal converted by the continuous / burst signal conversion circuit 21 into a specific time slot of a specific frame on the wireless multiplex frame. Further, the redundant bits for error correction generated by the error correction coding circuit 23 are multiplexed into a specific empty slot of a specific frame on the wireless multiplex frame.

Here, the continuous / burst signal conversion circuit 21
Does not convert a bit sequence of an input continuous signal into a burst signal in the same order, but performs an interleaving operation and replaces the bit sequence to convert it into a burst signal. The high-speed burst signal SIG2 multiplexed by the multiplexing circuit 25 is transmitted to the other opposite station.

At the other opposite station, the high-speed burst signal SIG2 transmitted from the multiplexing circuit 25 of one station is received, and the received burst signal SIG2 is converted to a burst / continuous signal. The signal is converted by the circuit 31 into a continuous signal. Here, the burst / continuous signal conversion circuit 31 performs a de-interleaving operation in the same manner as the above-described continuous / burst signal conversion circuit 21 and exchanges bit strings to convert them into continuous signals.

The continuous signal obtained by the burst / continuous signal conversion circuit 31 is input to a division circuit 33, which generates a syndrome and sends it to an error position detection circuit 34. The error position detection circuit 34 specifies a position where a bit error has occurred in the continuous signal converted by the burst / continuous signal conversion circuit based on the syndrome, and inverts the bit at the specified position by an adder circuit. And outputs a continuous signal to the data terminal. Therefore, even when interference occurs in the radio section and a burst-like bit error occurs in the data signal, the effect can be greatly reduced by the interleave function and the error correction function.

Next, the first embodiment will be described in more detail. In the embodiment shown in FIG. 1, the configuration of one opposed multi-directional time-division multiplex wireless data device in a multi-directional time-division multiplex wireless data communication system is shown. As shown in FIG. 1, in one station,
The burst signal conversion circuit 21 stores the low-speed continuous signal SIG1 input from the data terminal device based on the timing signal generated by the timing signal generation circuit 22, and stores the low-speed continuous signal SIG1 based on the timing signal generated by the timing signal generation circuit 24. As a high-speed burst signal.

At the same time, the error correction encoding circuit 2
3 performs an error correction encoding operation such as a BCH code on the continuous signal SIG1 in units of the number of bits required for the unit burst data, and outputs the resulting error correction redundant bits to send to the multiplexing circuit 25. To do. From the clock signal synchronized with the continuous signal SIG 1, the timing signal generation circuit 22 determines the timing signal required when the continuous signal SIG 1 is periodically input to the continuous / burst signal conversion circuit 21 and the timing signal generated by the error correction encoding circuit 23. Timing signals necessary for performing the error correction coding operation are generated.

The timing signal generation circuit 24 reads data stored in the continuous / burst signal conversion circuit 21 from a clock signal synchronized with the high-speed burst signal SIG2 on the radio side, and reads an error from the error correction encoding circuit 23. A timing signal necessary for outputting the redundant bit for correction is generated. The multiplexing circuit 25 multiplexes the burst data output from the continuous / burst signal conversion circuit 21 into a specific time slot of a specific frame that has been allocated in advance on the wireless multiplex frame. The multiplexing circuit 25 multiplexes the redundant bits for error correction output from the error correction encoding circuit 23 into a specific empty slot in a specific frame on the wireless multiplex frame.

Next, in the other station opposite to the one station, the burst / continuous signal conversion circuit 31 converts the radio-side high-speed burst signal SIG2 output from the multiplexer 25 in the one station into a burst signal. The received burst signal SIG3 is stored based on the timing signal generated by the timing signal generation circuit 32, and is read out as a low-speed continuous signal based on the timing signal generated by the timing signal generation circuit 35. The timing signal generation circuit 32 determines the timing required when the burst signal SIG3 is periodically input to the burst / continuous signal conversion circuit 31 from the clock signal synchronized with the burst signal SIG3 in units of the number of bits required for the unit burst data. Generate a signal.

The division circuit 33 divides a bit sequence constituting an error correction code in the continuous signal output from the burst / continuous signal conversion circuit 31 by a predetermined polynomial to obtain a syndrome for the error correction code. Is generated and output to the error position detection circuit 34. Here, the error position detection circuit 34 specifies the position where the bit error has occurred in the data based on the syndrome output from the division circuit 33, and the addition circuit 36 reads from the burst / continuous signal conversion circuit 31. The bit in which the error has occurred in the output low-speed continuous signal is subjected to bit inversion and error correction. The timing signal generation circuit 35 includes a timing signal necessary for periodically reading data stored in the burst / continuous signal conversion circuit 31 from a clock signal synchronized with the low-speed continuous data SIG4, and a division circuit 33.
And a timing signal required for the operation of the error position detection circuit 34.

Next, the operation of the first embodiment configured as described above will be described. In one station,
Low-speed continuous signal SIG1 input from the data terminal device
Is input to the continuous / burst signal conversion circuit 21 based on the timing signal generated by the timing signal generation circuit 22, where the data is stored. At the same time, the continuous signal SIG1 is subjected to an error correction coding operation such as a BCH code in the error correction coding circuit 23 in units of the number of bits required for the unit burst data, and the resulting error correction redundant bits are generated. Is output.

The timing signal generating circuit 22 converts the clock signal synchronized with the continuous signal SIG1 into the continuous signal SIG.
1 and a timing signal required when an error correction encoding operation is performed in the error correction encoding circuit 23, respectively. The data stored in the continuous / burst signal conversion circuit 21 is read based on a timing signal generated by the timing signal generation circuit 24. In the multiplexing circuit 25, the burst signal output from the continuous / burst signal conversion circuit 21 is
It is multiplexed in a specific time slot of a specific frame previously allocated on the wireless multiplex frame.

The redundant bits for error correction output from the error correction encoding circuit 23 are multiplexed in a specific empty slot in a specific frame on the radio multiplex frame, and sent to the radio section as a high-speed burst signal SIG2. When the timing signal generation circuit 24 periodically reads data stored in the continuous / burst signal conversion circuit 21 from a clock signal synchronized with the high-speed burst signal SIG2 on the wireless side in units of bits required for unit burst data, It generates a necessary timing signal and a timing signal required when outputting error correcting redundant bits from the error correction encoding circuit 23.

The timing relationship between the low-speed continuous signal SIG1 and the high-speed burst signal SIG2 is as shown in FIG. FIG. 2A shows a low-speed continuous signal SIG1, and FIG. 2B shows a high-speed burst signal SIG2.
The hatched portions in FIG. 2 indicate the redundant bits. In this multiplexing, the radio frame is multiplexed for effective use of the time slot, and one subscriber uses only a specific time slot of a specific frame of the radio multiplex frame to multiplex signals. In this case, for example, when a multiplex frame is formed in units of 40 frames, one time slot can accommodate up to 40 subscribers.

Here, the continuous / burst signal conversion circuit 21
Will be described with reference to FIG. FIG.
FIG. 3A shows the data format of the low-speed continuous signal SIG1. FIG. 3B shows the data format of the low-speed continuous signal SIG1 in the continuous / burst signal conversion circuit 21 composed of a RAM.
3 (c) shows the data format of the burst signal output from the continuous / burst signal conversion circuit 21. FIG. The continuous / burst signal conversion circuit 21 is usually composed of a RAM, and has a low speed continuous signal SI.
G1 is stored in the RAM in the order of the input bit string in FIG.
The data is written as shown in FIG.

That is, the bits of the RAM address are shifted from the smaller value to the larger value (in the direction of X in FIG. 3C) in accordance with the time series of the input bit string, and the bits are respectively shifted by the timing signal generating circuit. It is written in accordance with the timing signal output from 22. When the written bit is read as a high-speed burst signal, the address value is not cyclically changed from a smaller one to a larger one according to the timing signal generated from the timing signal generation circuit 24. In (b), Y
, The input bit string is dispersed in a time-series manner, subjected to an interleaving operation, and output. At this time, the output signal is multiplexed in a specific time slot of a specific frame of the above-described wireless multiplex frame.

Next, at the other station, the burst signal SIG2 transmitted from the opposite station is received by the burst / continuous signal conversion circuit 31 as the burst signal SIG3 via the radio section, and is generated by the timing signal generation circuit 32. Based on the generated timing signal, the signal is input to a burst / continuous signal conversion circuit 31, where the data is stored. The timing signal generation circuit 32 determines the timing required when the burst signal SIG3 is periodically input to the burst / continuous signal conversion circuit 31 from the clock signal synchronized with the burst signal SIG3 in units of the number of bits required for the unit burst data. Generate a signal.

The data stored in the burst / continuous signal conversion circuit 31 is read out as a low-speed continuous signal based on the timing signal generated by the timing signal generation circuit 35. The continuous signal output from the burst / continuous signal conversion circuit 31 is input to a division circuit 33, in which a bit string constituting an error correction code in the continuous signal is divided by a predetermined polynomial to perform error division. A syndrome for the correction code is generated. Here, division circuit 3
3, the position where a bit error has occurred in the data is specified in the error position detection circuit 34, and the error in the low-speed continuous data read from the burst / continuous signal conversion circuit 31 is detected. The generated bit is subjected to bit inversion in the adder circuit 36,
Perform error correction.

The timing signal generating circuit 35 includes a timing signal necessary for periodically reading data stored in the burst / continuous signal conversion circuit 31 from a clock signal synchronized with the low-speed continuous signal SIG4, and a dividing circuit. A timing signal required for the operation of the
And a timing signal necessary for outputting an error position detection signal from the CPU. The data after the error correction is output to the data terminal device as a continuous signal SIG4. High-speed burst signal SIG3 and low-speed continuous signal S
The timing relationship of IG4 is the relationship shown in FIG.
FIG. 2C shows the data format of the high-speed burst signal SIG3, and FIG. 2D shows the data after the error correction is a continuous signal SIG4.

Here, the burst / continuous signal conversion circuit 31
Will be described with reference to FIG. FIG.
4A shows the data format of the high-speed burst signal SIG3. FIG. 4B shows the high-speed burst signal SIG3 in the RAM constituting the burst / continuous signal conversion circuit 31.
, And FIG. 4C shows the data format of the low-speed continuous signal SIG4.
The burst / continuous signal conversion circuit 31 is usually composed of a RAM, and the high-speed burst signal SIG3 is written in the RAM in the order of the input bit string as shown in FIG.

That is, bits are written from the smaller value of the RAM address to the larger value (in the direction of Y in FIG. 4B) in accordance with the time series of the input bit string. At this time, the high-speed burst signal SIG3 is a signal multiplexed in a specific time slot of a specific frame of the wireless multiplex frame.
When the written bit is read as a low-speed continuous signal, the address value is not changed from the smaller value to the larger value, but is discretely circulated so as to perform the reverse operation of FIG. In b), by shifting in the X direction, the input bit sequence is deinterleaved, converted into the original continuous signal, and output. Regarding the above description, the same operation is performed without distinction between the direction from the master station device to the slave station device and the direction from the slave station device to the master station device.

As described above, the first embodiment according to the present invention is described.
In the embodiment, since a redundant bit for error correction is multiplexed in a specific empty slot on a radio frame, a speed conversion circuit accompanying the addition of the redundant bit is unnecessary. Since the positions of the redundant bits are known, a word synchronization circuit for error correction decoding on the receiving side is unnecessary. Also, error correction is not performed for all radio frames.
Since only the necessary subscribers can perform error correction for each unit subscriber line, depending on the type of signal to be transmitted, for example, when a voice signal is converted into a digital signal and transmitted, the error correction is not performed. In the case of transmitting a digital data signal from such a device, it is possible to selectively use error correction.

Further, even when a burst-like interference occurs in the radio section and a continuous bit error occurs in the data signal, the data signal is dispersed and transmitted in the radio section by the interleave function, so that the error correction processing is performed. When performing this, bit errors are discrete, and the effect on the data communication line due to continuous bit errors can be greatly reduced. In addition, even when a plurality of subscribers are accommodated in the same time slot by the multiplexing configuration of the radio frame, the interleave depth can be set for each subscriber line depending on the importance of the subscriber line, and the error can be reduced. You can adjust the correction effect.
As described above, the multi-way time-division multiplexing wireless data communication apparatus has an effect that transmission quality can be economically improved by adding a small-scale circuit.

Although the first embodiment has been described as applied to a case where the number of slave stations is three and one data terminal is connected to each slave station, However, the present invention is not limited to the first embodiment, and the same applies to a case where the number of slave station devices is other than three and a case where a plurality of data terminal devices are connected to one slave station device. It is clear that the effect is obtained.

[0044]

As described above, according to the present invention, a burst signal obtained by converting a continuous signal input from a data terminal device at one station by a continuous / burst signal conversion circuit is specified by a multiplexing circuit as a radio frame. In addition to multiplexing in a specific time slot in the frame, redundant signals for error correction generated by inputting a continuous signal to the error correction coding circuit and performing error correction coding are multiplexed in a specific empty slot in a specific frame of the wireless multiplex frame. Then, the high-speed continuous signal is sent to a burst / continuous signal conversion circuit on the opposite station side to be converted into a continuous signal, and the continuous signal is subjected to a polynomial operation by a division circuit to generate a syndrome for an error correction code. To the error position detection circuit, identify the position where the bit error occurred in the continuous signal based on the syndrome, and Since the bit generated at the specified position is bit-inverted by the adder circuit and a continuous signal is output to the data terminal, the speed conversion circuit accompanying the addition of redundant bits is unnecessary and the receiving side corrects errors. A word synchronizing circuit for compounding is not required, and it is possible to selectively use whether or not to correct an error according to the type of a signal to be transmitted. In addition, even when burst-like interference occurs in the wireless section and continuous bit errors occur in the data signal, the effect of the continuous bit errors on the data communication line can be significantly reduced when performing error correction processing. ,
Even in the case where a plurality of subscribers are accommodated in the same time slot, the error correction effect can be adjusted, and the transmission quality can be comprehensively and economically improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a multidirectional time-division multiplex wireless data communication apparatus according to the present invention.

FIG. 2 is a timing chart of a continuous signal and a burst signal applied to the first embodiment of the multidirectional time-division multiplex wireless data communication apparatus according to the present invention.

FIG. 3 is a timing diagram of a continuous signal stored in a continuous / burst signal conversion circuit and a burst signal converted into a burst signal and read out in the continuous / burst signal conversion circuit in the first embodiment of the multi-way time division multiplexed wireless data communication apparatus according to the present invention; It is an explanatory view of a writing / reading situation.

FIG. 4 is a timing chart of a burst signal stored in a burst signal / continuous signal conversion circuit and a continuous signal converted into a continuous signal and read out in the first embodiment of the multi-way time division multiplexed wireless data communication device according to the present invention; FIG. 4 is an explanatory diagram of a write / read situation.

FIG. 5 is a block diagram showing a configuration of a conventional multi-directional time-division multiplexing wireless data communication system.

FIG. 6 is an explanatory diagram of the timing of a wireless time slot allocated to each opposing data terminal device applied to the multidirectional time-division multiplexed wireless data communication system of FIG. 5;

FIG. 7 is a block diagram showing a configuration of a conventional multidirectional time-division multiplex wireless data communication device.

8 is a timing chart of a continuous signal and a burst signal applied to the multi-way time division multiplexed wireless data communication device of FIG. 7;

[Description of Signs] 1... Master Station Device, 1a to 1c, 10a, 11a, 12a
... data terminal devices, 10 to 12 slave station devices, 21 ...
... Continuous burst signal converter, 22, 24, 32, 34
... Timing signal generation circuit, 23 error correction encoding circuit, 25 multiplexing circuit, 31 burst / continuous signal conversion circuit, 33 division circuit, 34 error position detection circuit, 36 ... Addition circuit.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H04L 1/00 H04B 7/26 105D F-term (Reference) 5J065 AA03 AB01 AC02 AE06 AH02 AH03 5K014 AA01 BA05 EA01 HA10 5K028 AA14 BB06 KK33 LL41 MM09 RR04 5K067 AA02 CC04 EE22 EE71 GG03 HH26

Claims (14)

[Claims] In one station, a continuous / burst signal conversion circuit for converting a continuous signal input from a data terminal into a burst signal, an error correction coding circuit for performing error correction coding of the continuous signal, The burst signal converted by the continuous / burst signal conversion circuit is multiplexed in a specific time slot of a specific frame on the radio multiplex frame, and the redundant bits for error correction generated by the error correction coding circuit are transmitted on the radio multiplex frame. A multiplexing circuit for transmitting a burst signal by multiplexing the burst signal in a specific empty slot; and a burst / continuous signal converter for converting a burst signal multiplexed by the multiplexing circuit into a continuous signal on the side opposite to the one station. Circuit, and a bit string constituting an error correction code in the continuous signal converted by the burst / continuous signal conversion circuit. A division circuit that performs an operation on the obtained polynomial to generate a syndrome for the error correction code; and a bit in the continuous signal converted by the burst / continuous signal conversion circuit based on the syndrome generated by the division circuit. An error position detection circuit for specifying a position where an error has occurred, and an addition for performing bit inversion on a bit in which an error has occurred in the continuous signal converted by the burst / continuous signal conversion circuit and outputting the continuous signal to a data terminal A multi-directional time-division multiplexed wireless data communication device, comprising: a circuit; 2. The multidirectional time-division multiplexed wireless data communication according to claim 1, wherein said continuous / burst signal conversion circuit replaces a bit string of an input continuous signal by an interleaving operation and converts the same into a burst signal. apparatus. 3. The multi-way time-division multiplex wireless data communication apparatus according to claim 1, wherein said burst / continuous signal conversion circuit converts an input burst signal into a continuous signal by a de-interleaving operation. 4. The continuous / burst signal conversion circuit stores the continuous signal based on a timing signal generated from a first timing signal generation circuit, and a timing signal generated from a second timing signal generation circuit. 2. The multi-way time-division multiplexed wireless data communication device according to claim 1, wherein the continuous signal stored based on the data is read out as a high-speed burst signal. 5. The continuous / burst signal conversion circuit according to claim 1, wherein
A timing output from the first timing signal generation circuit in accordance with a time series of a bit sequence of the continuous signal sequentially input from the smaller address value to the larger address value of the RAM. Performing an interleave operation by dispersing an input bit sequence in a time series by discretely circulating based on a timing signal output from the second timing signal generation circuit when writing by a signal and reading from a RAM. 2. The multi-directional time-division multiplexed wireless data communication device according to claim 1, wherein said burst signal is output by reading the data. 6. The error correction encoding circuit performs an error correction encoding operation on the continuous signal in units of the number of bits required for unit burst data by a timing signal output from the first timing signal generation circuit. Above the second
2. The multi-way time-division multiplex wireless data communication apparatus according to claim 1, wherein redundant bits for error correction are output by a timing signal output from said timing generation circuit. 7. The first timing generation circuit includes a timing signal necessary for synchronously inputting the continuous signal from the clock signal synchronized with the continuous signal to the continuous / burst signal conversion circuit. 7. The multi-directional time-division multiplexed wireless data according to claim 4, wherein the error correction encoding circuit generates a timing signal necessary for performing an error correction encoding operation. Communication device. 8. The second timing signal generation circuit,
The reading of data stored in the continuous / burst signal conversion circuit from the clock signal synchronized with the burst signal on the radio side output from the multiplexing circuit and the output of the error correction coding circuit from the error correction coding circuit to the error correction redundant bit output. The multi-directional time-division multiplexed wireless data communication device according to any one of claims 4 to 6, wherein a required timing signal is generated. 9. The burst / continuous signal conversion circuit stores based on a timing signal generated from a third timing signal generation circuit and operates at a low speed based on a timing signal generated from a fourth timing signal generation circuit. 2. The multi-way time-division multiplexed wireless data communication device according to claim 1, wherein the data is read out as a continuous signal. 10. The burst / continuous signal conversion circuit converts the burst signal from the clock signal synchronized with the burst signal input to the burst / continuous signal conversion circuit to the burst / continuous signal conversion circuit. 10. The multi-directional time-division multiplexed wireless data communication device according to claim 9, wherein a timing signal necessary for periodically inputting in units of the number of bits required is generated. 11. The burst / continuous signal conversion circuit,
The RAM is configured to write data from the smaller address value of the RAM to the larger address value in accordance with the time series of the input bit string of the burst signal based on the timing signal output from the third timing signal generation circuit. And when reading out from the RAM, the signal is read out by a de-interleaving operation by discretely circulating based on the timing signal output from the fourth timing signal generation circuit and converted into an original continuous signal. The multi-way time division multiplexed wireless data communication device according to claim 1. 12. The multiplication circuit according to claim 1, wherein the division circuit performs an operation based on a timing signal output from the fourth timing signal generation circuit when performing the operation with the polynomial. Directional time division multiplexed wireless data communication device. 13. The multi-directional circuit according to claim 1, wherein said error position detection circuit specifies a position where said bit error has occurred based on a timing signal output from said fourth timing signal generation circuit. Time division multiplex wireless data communication device. 14. The fourth timing signal generating circuit, when periodically reading data stored in the burst / continuous signal conversion circuit from a clock signal synchronized with the continuous signal output from the addition circuit, 10. A timing signal necessary for operation of the division circuit, and a timing signal necessary for outputting an error position detection signal from the error position detection circuit are output. 14. The multidirectional time-division multiplexed wireless data communication device according to any one of claims 11 to 13.