JPH0357349A - Line speed detection system - Google Patents

Abstract

PURPOSE:To discriminate a normal character data speed in succession to a speed detection character by allowing a line speed detection means to calculate the line speed when a detection means detects a prescribed number of rising or falling. CONSTITUTION:A rising or falling detection circuit 10 detects the rising or falling of a speed detection character sent from a reception signal line. A clock circuit 40 gives a clock signal of a prescribed period to the circuit 10 in this case to calculate the rising or falling time. The rising or falling and time information is stored in a rising or falling storage circuit 50 and used to reproduce the speed detection character as a normal character. When a speed calculation circuit 20 based on a prescribed logic designated by the line offer company detects a prescribed number such as 2 of rising or falling, the circuit 20 calculates immediately the line speed by using the time information from the circuit 40.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for detecting the terminal line speed in a start-stop line interface, by making it possible to detect the line speed at a point in the middle of the bit string of the speed detection character, The purpose is to enable continuous reception of data, and in the terminal line speed detection method in the start-stop line interface, there is a rising or falling detection means for detecting the rising or falling bit pattern of the bit pattern of the speed detection character. A line speed detection means detects the line speed by counting the time between two rising or falling edges of a predetermined bit of the bit pattern detected by the falling edge detection means, and a line speed detection means detects the line speed by counting the time between two rising or falling bits of the bit pattern detected by the falling edge detection means, and detects the data according to the speed determined by the line speed detection means. The apparatus is configured to include data receiving means for receiving the data.

[Industrial application field]

The present invention relates to a line speed detection method, particularly for start-stop lines, and especially for X. 2
This invention relates to a terminal line speed detection method in an 8 interface.

As a procedure for accommodating asynchronous terminals in a packet switching system, the X.
There is a method for automatically detecting line speed using 28 terminal control technology. This method uses the characteristics of the bit pattern of specific characters for line speed detection (hereinafter referred to as speed detection characters) that are input from the terminal to the Bakenohm display/decomposition unit (PAD) to calculate the number of bits and their The line speed is detected based on the relationship with the reception time j.

After detecting the line speed, normal data such as characters is received and decoded in synchronization with the detected speed, so the line speed must be detected in as short a time as possible.

(Prior art) FIG. 8 shows the X. FIG. 2 is an explanatory diagram of a conventional line speed detection method in the H.28 interface. As shown in FIG. 3A, a constant repeating pattern of "0° and 1°" representing the speed detection character between the start bit and the stop bit is received before the normal character is received. A mark is held before receiving this speed detection character pattern, and a mark is held between the stop bit and the normal character pattern that follows it.Therefore, it is possible to receive and decode normal characters. starts from the first falling edge after the mark hold after the speed detection character.

Conventionally, the pattern of speed detection characters is sampled at high speed by monitoring the reception line for a certain period of time T from the start of reception of speed detection characters, and the information string of ゜O゜ or ゜1゛ is later recorded. Through analysis, the reception time of one bit was calculated to calculate the data rate, that is, the line speed. for example,
As shown in (■) in the same figure, each bit of ゛0゛ or ゛1' is sampled at four points, and as shown in (C) of the same figure, the sampled values are analyzed later. Search for the number of sampling values at which the fall from 1° to 0° occurs, calculate the time until the second falling from the sampling number and the sampling period, and calculate the time until the second falling from the above. The line speed was calculated by dividing the number of bits until the falling edge by the above time.

[Problem to be solved by the invention]

Conventionally, normal characters other than speed detection characters are decoded in synchronization with the line speed after the line speed is detected.
The reception of normal characters is delayed by the time required to detect the line speed. In the above-mentioned conventional system, it is necessary to set the certain time T with a margin according to the lowest line speed among the line speeds of the lines that may receive the signal. For this reason, there was a problem in the past in that the reception and deciphering of normal characters was delayed. For example, in FIG. 8(a), the line speed is detected at time t.
If the process ends at , the time Tt is wasted because normal characters can be received and decoded after the time Tt.

In view of the problems in the prior art described above, an object of the present invention is to provide a rising/falling monitoring mode of the received signal in the line speed detection method, instead of devoting the fixed time T to speed detection, Regardless of the line speed, by detecting the line speed between predetermined bits and then immediately transitioning to character reception mode, it is possible to receive and decipher the normal characters that follow the speed detection character, thereby increasing the speed. The purpose is to shorten the time between the start of reception of detection characters and the start of reception and decoding of normal characters.

Still another object of the present invention is to reduce the time difference between the start point of receiving the speed detecting character and the start point of receiving and decoding the normal character to zero by using the normal character pattern as the speed detecting character. It's about doing.

Furthermore, another object of the present invention is to improve the reliability of preventing malfunctions even if a speed detection character is erroneously input.

(Means for Solving the Problems) Figure 1 is a block diagram of the principle of the present invention. In the figure, a terminal line speed detection method in the X.2 interface is shown, and l is a speed detection character. rising or falling detection means for detecting the rising or falling of the focus pattern; 2 is between predetermined bits of the bit pattern detected by the rising or falling detecting means 1; for example, between the first falling and the second rising; A line speed detecting means 3 detects the line speed by counting the time between two rising or falling edges, and 3 is a data receiving means 3 that receives data at the speed determined by the line speed detecting means 2.

Reference numeral 4 denotes timing means for calculating the time from the determination of the line speed by the line speed detecting means 2 to the stop bit of the speed detection character. The data receiving means 3 receives data from the character following the stop bit.

5 stores the rise or fall of the bit pattern detected by the rise or fall detection means 1 and the line speed detected by the line speed determination means 2, and reproduces the speed detection character as a character pattern. It is a memory reproducing means.

Furthermore, in the line speed detection means 2, the bit interval between two rising or falling bits for which the line speed should be calculated is set to 5.
Bit width to 7 bits width.

The significance of setting the width to 5 bits or 7 bits is as follows. If the bit width is n, and if n is an even number (2m>), then the speed will be twice as fast as when a m-bit width character is mistakenly used, resulting in a malfunction.

Also, if n = 3 bits, n = 6 bits width 1 If the character is used incorrectly, the speed 2 of It malfunctions frequently.

On the other hand, the usage speed distribution is usually 300bps and 600bps
, 1 1200 bps and 2400 bps, there are many cases in which the relationship is double or 2, and application of a 5 to 7 bit bin width is effective in preventing erroneous speed detection as described above.

[Effect]

The rise or fall detection means 1 detects the rise or fall of the input signal, and immediately upon detecting a predetermined number of rises or falls, the line speed detection means 2 calculates the line speed. When the speed calculation is completed, the data speed of the normal character following the speed detection character is known, so that characters can be received immediately after the bit pattern of the speed detection character.

More specifically, it is sufficient to start receiving and decoding normal characters in the speed calculation end storage/reproduction means and the time elapsed storage/reproduction means up to the stop bin of speed detection characters.

In addition, if normal characters are used as speed detection characters and the speed detection characters are memorized and reproduced, the speed detection characters can also be used as a normal character pattern.
It is no longer necessary to secure a line speed detection time T that matches the minimum speed of the line as in the past.

〔Example〕

Examples of the present invention will be described below.

FIG. 2 is a schematic illustration of the present invention. In the figure, in addition to the conventional signal line establishment mode and normal character reception mode, the following rising or falling modes are available as modes for controlling the signal vA (data receiving line) from the line. will be added. Then, in the rising or falling mode, the speed of the line is calculated as soon as the required number of risings or fallings are detected for speed calculation. This speed calculation is performed according to a predetermined logic predetermined by the line provider, and then the receiving circuit is initialized based on the speed information determined by the speed calculation and shifts to a normal character reception mode.

FIG. 3 is a functional block diagram showing an automatic line speed detection device according to an embodiment of the present invention as a means for realizing the system shown in FIG.

In the figure, a rising or falling detection circuit 10
detects the rising or falling edge of the speed detection character sent from the receiving signal line.

At this time, the clock circuit 40 supplies a clock signal with a predetermined period to the rise or fall detection circuit 10, thereby calculating the rise or fall time.

This rise or fall and its time information are stored in the rise or fall memory circuit 50, and are used to reproduce the speed detection characters as normal characters.

The speed calculation circuit 20 calculates times f! Based on a predetermined logic specified by the provider, when a certain number, for example two, of rising or falling edges are detected, the line speed is immediately calculated using time information from the clock circuit 40. The method for calculating this line speed will be explained using Figure 4. In Figure 4, the bit pattern of the speed detection character is
In this example, the time from the first falling edge to the next falling edge is 5.
It is a bit, and "1" in the bit pattern is a mark state, and "0" is a space state.

The mark in front of the speed detection character is in a mark hold state as shown by ■. The first falling edge after the mark hold state is the start bit of the speed detection character and tW.
m is done. When the second falling edge is detected, the speed calculation circuit 20 immediately calculates the line speed regardless of the subsequent bit pattern of the speed detection character.

At this time, since the counting time (2) from the first falling edge (2) to the next falling edge (2) can be known from the time information from the clock circuit 40, the line speed is calculated using the following formula.

Note that after the stop bit of the speed detection character, the mark is held again.

If the line speed is calculated in this manner, as shown in FIG. 5, the faster the provided line speed is, the shorter the time it takes to receive a 5-bit character, and therefore the shorter the line speed detection time. For example, if the provided line speed is 2400 bps, the detection time is 2.08ms, and if the provided line speed is 5Qbps, the detection time is ! ．． 00ms. Conventionally, the detection time was set according to the lowest line speed among the provided line speeds, so in the example in Figure 5, 40Ims was set as the line speed detection time even for lines faster than 50 bps. On the other hand, in the present invention, 10
50ms for 0bps line, 16.7ms for 300bps line, 4.17ms for 1200bps line
, with a 2400 bps line, it takes 2.08 network S time.

Returning to FIG. 3 again, when the line speed is detected as described above, the data receiving circuit 30 immediately enters the normal character receiving mode. As a result, the normal filler after the mark hold after the speed detection character can be immediately received and deciphered. The data received by the data receiving circuit 30 is stored in the received data buffer circuit 60 and used for printing out, etc. An example of switching between this character reception mode is shown in VI. In Figure 6, the line speed is detected as the speed detection character falls for the second time, and then the middle of the reception time of the stop bit is determined while taking the timing based on the bit pattern of the speed detection character up to the stop bit. and switch to reception mode at that time ■. Note that if this switching is performed before the focus pattern of the speed detection character falls, it will be mistaken as the start focus of the subsequent character, resulting in a malfunction.

On the other hand, in FIG. 3, changes in the rise or fall of the speed detection characters stored in the rise or fall storage circuit 50 are also sent to the received data basso circuit 60 and reproduced as normal characters. As a result, the speed detection characters are received as normal characters in parallel with the line speed detection operation, so the line speed detection time becomes substantially zero.

FIG. 7 is a more specific block circuit diagram of the apparatus of FIG. 3 according to an embodiment of the present invention. In this figure, parts that are the same as those in Figure 3 are given the same reference numbers. In FIG. 7, a receiver circuit 70 draws in the data reception line, and a rise or fall detection circuit 10 monitors the rise or fall operation of the data reception line, and upon detection, the operation is handed over to the speed calculation circuit 20. , the speed calculation circuit 20 counts the time between falling signals based on specified logic, and calculates the speed by calculating the number of bits received during that time.The clock circuit 4
0 counts time information for calculating the time between rising or falling edges, the timing circuit 80 counts the timing of switching from the line speed detection mode to the normal character reception mode, and the memory circuit 50 The circuit 60 stores changes in the rise or fall of the line along with time information and reproduces them as characters based on the detected speed information.The reception data buffer circuit 60 stores the reproduced speed detection characters and subsequent continuously received characters. It is something.

The operation of the device shown in FIG. 7 can be easily inferred from the description of FIG. 3, so a description thereof will be omitted.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, in the line speed automatic detection method, it becomes possible to receive and decode normal characters immediately after detecting the line speed using the speed detection characters, regardless of the problem with the provided line speed. Furthermore, since the speed detection characters can also be received as normal characters, the time between the time when receiving the speed detection characters starts and the time when receiving and decoding the normal characters starts is greatly shortened.

Furthermore, according to the present invention, when a normal character pattern is also used as a speed detection character, the time difference between the time when the speed detection character starts receiving and the time when the normal character starts receiving and decoding becomes substantially zero. Become.

When using error correction modems, which have recently become increasingly popular, the character time intervals of character strings transmitted from user terminals cannot be guaranteed on the receiving side. That is, since the error correction modem banfers a plurality of characters, blocks them, and transfers them all at once, the receiving side receives the characters in blocks continuously (without character intervals).

The line speed automatic detection method according to the present invention is characterized by continuous character reception, and will be extremely useful in the future in communications using error correction modems as described above.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of the present invention; FIG. 2 is a schematic explanatory diagram of the present invention; FIG. 3 is a functional block diagram showing means for realizing the system of FIG. 2 according to an embodiment of the present invention; An explanatory diagram of line speed calculation according to an embodiment of the present invention. Fig. 5 is a diagram showing the relationship between line speed detection time and provided line speed according to an embodiment of the present invention. Fig. 6 is a diagram showing speed detection according to an embodiment of the present invention. FIG. 7 is a more specific block circuit diagram of the device of FIG. 3 according to the embodiment of the present invention, and FIG. 8 is an explanatory diagram of the conventional line speed detection method. be. In the figure, 1...rise or fall detection means, 2...
Line speed detection means; 3. Data reception means; 4. Timing means; 5. Storage and reproduction means. Schematic explanatory diagram of the present invention $ 2 Figure + 1 Characters for speed detection 1 1 1 1 Means for realizing the method of Figure 2 Figure 3 ■ Embodiment of the present invention! Explanatory diagram of line speed calculation $4
! 21 Diagram showing the relationship with the provided line speed Characters for speed detection Subsequent characters ■ ■ ■ ~ -0 -- 0 ○ O

Claims (1)

[Claims] 1. In a terminal line speed detection method in a start-stop line interface, there is provided a rising or falling detection means (1) for detecting a rising or falling bit pattern of a speed detection character; A line speed detecting means (2) for detecting the line speed by counting the time between two rising or falling edges between predetermined bits of the bit pattern detected by the detecting means (1), and the line speed detecting means ( A line speed detection method characterized by comprising data receiving means (3) for receiving data at the speed determined in step 2). 2. The data receiving means (3) further comprises a timing means (4) for calculating the time until the stop bit of the speed detection character after the line speed is determined by the line speed detecting means (2), and the data receiving means (3) 2. The line speed detection method according to claim 1, wherein data is received from a character following a stop bit. 3. Memorize the rising or falling edge of the bit pattern detected by the rising or falling detection means (1) and the line speed detected by the line speed determining means (2), and write the speed detection character. 2. The line speed detection method according to claim 1, further comprising storage/reproduction means (5) for reproducing the character pattern. 4. A line speed detection method characterized in that, as a designation method for the bit pattern detected by the rise or fall detection means (1), the interval between two bits is set to a width of 5 bits or 7 bits.