JPH11205396A - Serial communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automate reception between different systems by switching input and output signal circuits on a receiver side based on the signal level of input signals so that the input and output signal circuits are matched with the signal level on a transmitter side. SOLUTION: An input signal switching circuit 2 of a receiver switches a circuit so that the circuit is matched with a balance or unbalance circuit based on a transmission signal level detected in an input level detection circuit 3 and matches the transmission signal level with the signal processing level of the receiver. Input signals received in the input signal switching circuit 2 of the receiver are matched with the communication system of the receiver and outputted to a start bit detection circuit 4, the start bit detection circuit 4 detects the rise of a start bit and then outputs input signals to a data bit detection circuit 5, clock synchronization is performed in a control circuit 6 and data are sampled and read to a shift register 9. That is, the input and output signal circuits on the receiver side are switched based on a detected signal level so as to be matched with the signal level on the transmitter side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial communication device which detects a signal level when a different signal level is input in serial communication of a start-stop synchronization system, and switches circuits to perform communication.

[0002]

2. Description of the Related Art A conventional serial communication device has a method of performing serial communication by unbalanced transmission (RS-232-C).
(Registered trademark)) and a method of performing serial communication by a balanced transmission method (RS-422 (registered trademark)). In these communication devices, the connection between the same communication systems is connected by a predetermined dedicated connector, and the communication between the different communication systems is manually switched and connected by a changeover switch.

[0003]

However, when a signal is transmitted from a transmitting device using a different communication method to a receiving device, the data signal level and the circuit method are different and communication cannot be performed. The receiving device determines whether the system for transmitting the signal level every time communication starts is a balanced transmission system or an unbalanced transmission system, and replaces or switches to a specified connector that matches the signal level and circuit system. The circuit had to be manually switched and connected using a switch.

Accordingly, it is an object of the present invention to detect a signal level of data transmitted from a transmitting device on the receiving device side and switch the receiving circuit and the transmitting circuit on the receiving device side based on the signal level of the transmitted data. It is an object of the present invention to provide a serial communication device capable of automatically performing communication by adjusting signal levels between transmission devices.

[0005]

SUMMARY OF THE INVENTION The present invention relates to a start-stop synchronous serial communication apparatus, comprising: level detection means for detecting a signal level of an input signal transmitted from a transmission apparatus;
A serial communication device comprising switching means for switching the input and output signal circuits on the receiving device side to match the signal level on the transmitting device side based on the signal level detected by the level detecting means.

Further, the present invention provides a start-stop synchronization type serial communication device, a means for detecting a start bit of an input signal transmitted from a transmitting device, a level detecting means for detecting a signal level of the start bit, and a receiving device. Switching means for switching the input and output circuits on the device side to a balanced circuit or an unbalanced circuit in accordance with the transmitting device side, and control means for controlling the switching means based on the level of the signal detected by the level detecting means. Serial communication device.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the serial communication device of the present invention. The serial communication device of the present embodiment can communicate at several types of signal levels,
The data transmitted from the transmitting device is received by the receiving device, the received signal level is detected, the input circuit of the receiving device is switched according to the signal level of the transmitted data according to the detected level, and the transmitting circuit is connected to the transmitting device. It is possible to communicate with each other in accordance with the above circuit system.

The output from the receiving device to the transmitting device is invalidated by a control signal from the control circuit 6 to prevent circuit destruction on both the transmitting device and the receiving device due to data signal mismatch. The input signal received by the receiving device is input from the receiving terminals 1 and 1 'when a signal is input by the balanced transmission method, and is input from the receiving terminal 1 when a signal is input by the unbalanced transmission method. Is entered. Receiving end 1, 1 '
Is input to the input signal switching circuit 2,
The signal is input from the receiving end 1 to the input signal level detection circuit 3.
In the case of performing communication by the balanced transmission method (such as RS-422), the received data input to the receiving end 1 ′ is a signal obtained by inverting the received data input to the receiving end 1 ′.

[0009] In the start bit, the received signal level is about 5 V or less in the communication by RS-422.
In communication by 232-C, the received signal level is about 8
It is transmitted at a high signal level of V to 12V. The input level detection circuit 3 detects the level of the input signal immediately after the start bit rises, and the control circuit 6 determines the input signal switching circuit 2 and the output signal switching circuit 21 as a balanced circuit based on the detected signal level. Alternatively, the control signal is switched to the unbalanced circuit, and a control signal is sent so as to enable the output of the output signal switching circuit 21 to be in a transmittable state.

The input signal switching circuit 2 of the receiving device switches the circuit based on the transmission signal level detected by the input level detection circuit 3 so as to match a balanced or unbalanced circuit, and receives the transmitted signal level. Match the signal processing level of the device. The input signal received by the input signal switching circuit 2 of the receiving device is matched to the communication system of the receiving device and output to the start bit detection circuit 4. After detecting the rise of the start bit, the start bit detection circuit 4 outputs an input signal to the data bit detection circuit 5, synchronizes the clock with the control circuit 6, and extracts and reads data into the shift register 9.

As a clock for extracting data, a clock obtained from a reference clock 7 is divided by a clock frequency dividing circuit 8.
, And the control circuit 6 generates a clock having a cycle corresponding to the clock on the transmitting device side. Data bit detection circuit 5
Is read into the shift register 9, and when the data shift is completed, the parity check circuit 10
Now check for data errors.

The parity bit is added for detecting an error in the data.
If it is set to 0 (binary number), in the case of even parity, 0 data is added so that the number of 1 becomes an even number.

In the receiving apparatus, if one bit of the received data is inverted due to disturbance or the like, and the number of 1s from the parity bit data is not an even number, the parity check circuit detects a data error and sends it to the reception buffer register 12. It outputs an error signal and performs processing such as data error. If there is no error as a result of checking by the parity check circuit 10, a control signal is sent to the reception data buffer register 12 if the data is normal. Next, the framing check circuit 11 detects a stop bit and sends a control signal to the reception data buffer register 12.

As a result of the parity and framing check, the data of the normally input signal is processed as normal reception data and output to the reception data buffer register 12. The reception data stored in the reception data buffer register 12 is sent to the central control unit (C
PU) 14, a character display or the like is displayed on a display device (not shown), and processing such as backup recording is performed on a recording device such as a hard disk.

On the other hand, a reception result is returned from the receiving device to the transmitting device. At this time, the reception data buffer register 1
The data that is stored in the parity check and the framing check to indicate normal or abnormal is stored in the internal bus 1.
3 to the transmission data buffer register 15. The return data stored in the transmission data buffer register 15 is read out to the shift register 16 by the control circuit 6, and the parity bit and the stop bit are generated by the parity generation circuit 17 and the stop bit generation circuit 18 and added to the return data. You.

The signal level returned from the output signal switching circuit 21 to which the output is permitted by the control circuit 6 to the transmitting apparatus is controlled so as to match the level of the signal transmitted from the transmitting apparatus to the receiving apparatus and the circuit system. The clock is controlled by the circuit 6, the start bit is added to the return data by the start bit generation circuit 19, and the clock is synchronized with the clock cycle transmitted from the transmission device side by the clock frequency dividing circuit 20.
The data is returned as return data from the transmitting ends 22, 22 '(when the transmitting device uses the balanced transmission method) or 22 (when the transmitting device uses the unbalanced transmission method).

The signal transmitted from the transmitting end 22 'is a signal obtained by inverting the data of the return signal output from the transmitting end 22 in the case where the transmission apparatus at the transmission destination uses the balanced transmission method (RS-422). Is output. The signal level output from the transmitting terminals 22 and 22 'based on RS-422 is normally + 5V
信号 0V signal level. Unbalanced transmission method (RS-2
32-C), the signal level of the transmission signal when transmitted from the transmission end 22 is +15 V to -15 V, and the signal level of the start bit when received on the receiving device side is about 8 V or more.

FIG. 2 is a block diagram showing an example of the input level detection circuit. The input level detection circuit 3 receives the received data a1 (in the case of RS-232-C) or a2 (RS-
422 (showing the positive signal wave) is input to the comparator 301 and the signal level conversion circuit 302. The comparison voltage A of the comparator 301 is RS-422 and RS-2.
The control circuit 6 is controlled by the ratio of the resistors R1 and R2 to about 6 to 8 V between the signal level of the start bit of the 32-C communication.
It is controlled and adjusted and set. Thereby, the comparator output b1 when the transmitting device side is RS-232-C
Is "H" level, and the comparator output b2 in the case of RS422 becomes "L" level. This comparator output b is input to the D terminal of the D flip-flop 304.

Also, the threshold level of the signal level input to the receiving apparatus is set by the ratio of the resistors R4 and R5, and the data of the signal is detected. Signal level conversion circuit 30
The output signal c output from the D flip-flop 3
The clock signal d of the normal transmission data is inputted from the control circuit 6 to the CK terminal which is delayed by the timing t from the output signal c of the signal level conversion circuit 302. D
The signal e delayed by the flip-flop 303 is input to the CK terminal of the D flip-flop 304, and the signal b is latched at the rising edge of the clock to obtain the output f. According to the latched signal f, the input signal switching circuit 2 and the output signal switching circuit 21 are not shown, but RS-232-C and RS-42.
In the case where the transmitting device side is different from the receiving device side in correspondence with the communication by the communication device 2, the circuit is automatically set to a circuit matching the transmitting device side.

FIG. 3 is a diagram for explaining signal waveforms at various parts of the input level detection circuit. a-1 and a-2 are signal waveforms of RS-232-C and RS-422, respectively. (Line A in a-1 and a-2 indicates the comparison voltage level of 6-7V). b-1 and b-2 are the comparators 3
01 shows the case where the output signal waveform of RS-232-C is 0 and the case of the output signal waveform of RS-422 is 0 when compared with each other. c is an output signal waveform of the signal level conversion circuit 302. d is a normal clock signal waveform. e is c
The signals b-1 and b-2 (the signals immediately after the rise of the start bit) are latched with the signal waveform delayed by f.sub.1 to switch between f-1 and f-2 (RS-232C, RS-422). Get. The switching output of f-1 and f-2 controls the switching selector for connection between the input switching circuit 2 and the output switching circuit 21 to switch the input and output circuits to balanced or unbalanced circuits.

In this embodiment, the signal level immediately after the rise of the start bit is detected, and the signal is transmitted from the transmitting apparatus in a different system from that of the receiving apparatus using balanced or unbalanced transmission, and the received signal level and the circuit system are different. Even in this case, the receiving apparatus controls switching so that the receiving input circuit and the transmitting output circuit are matched, so that automatic reception can be performed.

[0022]

According to the present invention, the signal level of the start bit is detected, and the receiving circuit and the transmitting circuit are controlled so as to match the transmitting apparatus based on the signal level of the transmitting side. Can be automatically received.

[Brief description of the drawings]

FIG. 1 is a block diagram of a serial communication device according to an embodiment of the present invention.

FIG. 2 is a block diagram of an input level detection circuit used in one embodiment of the present invention.

FIG. 3 is a diagram showing signal waveforms at various parts of an input level detection circuit used in one embodiment of the present invention.

[Explanation of symbols]

 1, 1 'receiving end 2 input signal conversion circuit 3 input level detection circuit 4 start bit detection circuit 5 data bit detection circuit 6 control circuit 7 reference clock 8 clock division circuit 9 shift register 10 parity check circuit 11 framing check circuit 12 received data Buffer register 13 Internal bus 14 CPU 15 Transmission data buffer register 16 Shift register 17 Parity bit generation circuit 18 Stop bit generation circuit 19 Start bit generation circuit 20 Clock division circuit 21 Output signal switching circuit 22, 22 'Transmission end

Claims (2)

[Claims] 1. A start-stop synchronization type serial communication apparatus, comprising: a level detecting means for detecting a signal level of an input signal transmitted from a transmitting apparatus; and a receiving apparatus based on the signal level detected by the level detecting means. A serial communication device, comprising: switching means for switching an input and output signal circuit so as to match a signal level of a transmission device. 2. An asynchronous communication serial communication apparatus, comprising: means for detecting a start bit of an input signal transmitted from a transmission device; level detection means for detecting a signal level of the start bit; And switching means for switching the output circuit to a balanced circuit or an unbalanced circuit in accordance with the transmitting device side, and control means for controlling the switching means based on the level of the signal detected by the level detecting means. Serial communication device.