JPH10285245A - Automatic data reception timing discriminating system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically discriminate the characteristic of a data terminal at a data communication equipment side by setting a mode to be an RT1 mode when an RT1 clock is included in a reception timing(RT) signal and to be an RT2 mode when it is not. SOLUTION: An RT1 clock detecting part 30 detects the RT1 clock included in the RT signal so as to latch it and gives it to a mode change-over part 31. When RT1 is detected, the mode change-over part 31 holds the RT1 mode by leaving a switch 32 as it is. Unless an oscillation source exists in the equipment, the RT1 clock detecting part 30 cannot latch the RT1 clock and the data terminal 1 reports an effect that the mode change-over part 31 cannot detect the RT1 clock. By receiving it, the mode change-over part 31 sets relay switches 32A and 32B to an a-contact so as to change-over the mode to the RT2 mode. Setting is executed to the RT1 mode when the RT1 clock is included in the RT signal and to the RT2 mode when it is not so that the characteristic of the data terminal 1 is automatically discriminated at the data communication equipment side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic data reception timing discriminating system, and more particularly to a data communication system which supplies a data reception timing clock to a data terminal or receives a data reception timing clock from the data terminal. Related to the device.

[0002] In data communication, demands for higher speed and higher reliability have been increasing in recent years. It is necessary to accurately select and switch the clock system in the data communication device, and to perform data communication without interruption.

[0003]

2. Description of the Related Art FIG. 5 is a conceptual diagram of a conventional data communication system. (A) shows the case of RT2 mode, (b) shows the case of R2 mode.
The case of the T1 mode is shown. In the figure, 1 is a data terminal (DTE), 2 is a data communication device (DCE) connected to the data terminal 1, and 3 is a line connected to the data communication device 2. In the example shown in the figure, a first data terminal 1 and a first data communication device 2 are connected, and the first data communication device 2 is connected to a second data communication device 2 via a line 3. . Then, the second data communication device 2
Is connected to the second data terminal 1.

When data transmission is performed in a synchronous manner,
The case where the data communication apparatus 2 performs data transmission by teaching the data transmission timing to the data terminal 1 as shown in FIG. 3A is called an RT2 mode, and as shown in FIG. The case where data transmission is performed by teaching the timing of data transmission to 2 is called the RT1 mode.

In the case of the RT2 mode, a data reception timing signal (RT) is given from the data communication device 2 to the data terminal 1 as shown in FIG. A clock for synchronization is generated, and data received from the data communication device 2 is set to R
Receive from D terminal.

In the case of the RT1 mode, a data reception timing signal (RT) is given from the data terminal 1 to the data communication device 2 as shown in (b), and the data communication device 2 generates a clock from the received timing signal, The received data is sent to the data terminal 1. The data terminal 1 receives data received from the data communication device 2 from an RD terminal.

When the conventional data reception timing clock is set, when the data terminal 1 receives data from the data communication device 2, the reception timing signal (RT) is
This is a timing signal (RT2) extracted from the carrier from the data communication device 2 on the other end, and transmits received data from the data communication device 2 to the data terminal 1 in synchronization with the timing signal (RT2).

However, when the data terminal 1 is connected to the data terminal 1 having an oscillation source (clock generator), data transmission is performed using the RT2 clock or data transmission is performed using the RT1 clock. This is set externally or mode switching data is stored in a register, and the mode is set according to the mode read from this register.

FIG. 6 is an explanatory diagram of a conventional data reception timing clock setting method. Here, the data terminal 1 is in accordance with ITU-T Recommendation V. A case with 35 interfaces is shown. In the data communication device 2, reference numeral 21 denotes a driver for transmitting received data and a data reception timing signal, and reference numeral 22 denotes a receiver for receiving a data reception timing signal.
Reference numeral 23 denotes a switch for switching a clock signal line. Switch 23 sets the RT mode to RT1 mode or R
Mode switching (RTM
ODSEL) signal is inputted, and it is determined whether the contact of the switch 23 is set to the a contact side (RT2 mode) or to the b contact side (RT1 mode). In addition,
When this mode switching is performed by a setting pin built in the data communication device 2, this mode switching signal is unnecessary.

In the RT2 mode, the switch 23 is connected to the contact a. In this case, since the clock is given from the data communication device 2 to the data terminal 1,
An RT2 timing signal is supplied from a driver 21 of the data communication device 2 to an RT terminal of a data terminal.

When a clock generator is built in the data terminal 1, the system shown in FIG.
It can operate in any of the T2 modes. When operating in the RT2 mode, the a contact of the switch is connected, and the data communication device 2 transmits the RT2 signal to the data terminal 1.
A timing signal is provided. In the case of the RT1 mode, the switch 23 switches to the contact b side. Then, an RT1 timing signal is provided from the data terminal 1 to the data communication device 2 and received by the receiver 22. When the clock is thus determined, the received data is transmitted from the driver 21 to the RD terminal of the data terminal in synchronization with the clock.

FIG. 7 is a time chart showing the operation of the conventional system. In the figure, (a) is the RT1 clock,
(B) is an RT2 clock, (c) is a reset signal for resetting the data communication device 2, (d) is a mode select signal (RTMODESEL) for setting an RT mode,
(E) is the data reception timing signal (RT), and (f) is the reception data (RD). Mode select signal (d)
Is configured to select RT1 with "L (low level, that is," 0 ")".

First, when a reset signal is output as shown in (c), the switch 23 in the data communication device 2 is reset, and its contact is set to the b-side.
The RT1 clock is sent to the data communication device 2 from the RT1 mode. As a result, the data communication device 2
The reception data RD is transmitted in synchronization with the RT1 clock, and the data terminal 1 side receives the reception timing signal R shown in FIG.
Data is taken in synchronization with T (clock synchronized with RT1). Specifically, the data is taken in synchronization with the fall of the data reception timing signal RT. The fetched data is "1", "1", "0" as shown in FIG.
Becomes

Here, when the mode select signal rises from "L" to "H" as shown in (d), the contact of the switch 23 in the data communication device 2 is switched from the side b to the side a, and the switch 23 is set to the RT2 mode. Become. In the RT2 mode, the clock generated on the data communication device 2 side is notified to the data terminal 1 via the switch 23. As a result, the reception timing signal RT changes from RT1 to RT2 as shown in FIG.
And the data terminal 1 fetches data in synchronization with the reception timing signal RT (clock synchronized with RT2) shown in (e). Specifically, the data is taken in synchronization with the fall of the data reception timing signal RT. The captured data, as shown in (f),
They are "0", "1", "0", and "1".

[0015]

In the conventional system described above, the data reception timing on the data terminal 1 side needs to be set differently depending on the characteristics of the connected terminal. Therefore, at the time of setting the reception timing clock, after understanding the characteristics of the data terminal 1, the mode select signal is set on the data communication device 2 side, or the mode is set using an external pin or the like, and the clock used is set to RT1. It is necessary to decide whether to use RT2.

That is, the data terminal 1 receives the timing of receiving the reception data RD from the data communication device 2 (that is, receives RT2) to take in the data, or outputs the timing (RT1) generated inside the data terminal 1. It is necessary for the data communication device 2 to set whether to perform data reception. For this reason, when the data reception timing clock is set, an erroneous setting may be performed, which may hinder data communication.

The present invention has been made in view of such a problem, and has been made in consideration of the characteristics of a data terminal (RT1 or RT2).
It is an object of the present invention to provide a data reception timing automatic discrimination system capable of automatically discriminating data reception timing on a data communication device side.

[0018]

[Means for Solving the Problems]

(1) FIG. 1 is a principle block diagram of the present invention. 6 are denoted by the same reference numerals. The system shown in the figure includes a data terminal (DTE) 1 and a data communication device (DC).
E) 2 is connected, and the data communication device 2
A system that receives data from the Internet. Further, here, the data terminal 1 complies with ITU-T Recommendation V.3. 3
The case where there are five interfaces is shown. If the data terminal 1 has V. RT for 35 interfaces
A and B lines are used as the signal lines for communication.

In the following description, the case where the data terminal 1 receives data from the data transmitting device 2 will be described. However, data can be transmitted from the data terminal 1 to the data communication device 2 side.

In the data terminal 1, RTA and RTB are terminals for transmitting and receiving RT signals, RD is a data receiving terminal,
ER is a data ready output terminal. When the ER signal is on (“1” level), the data terminal 1 can transmit and receive data. When the ER signal is off (“0” level), the data terminal 1 cannot transmit and receive data. Indicates a possible state.

In the data communication apparatus 2, reference numeral 21 denotes a driver (DV) for transmitting data and an RT mode signal, and reference numeral 22 denotes a receiver (RV) for receiving an RT mode signal. The driver 21 and the receiver 22 are in accordance with ITU-T Recommendation V. 35 specifications. Reference numeral 30 denotes an RT1 clock detecting unit for identifying whether or not an RT1 clock is included in a signal transmitted from the data terminal 1;
A mode switching unit that switches the mode between RT1 and RT2 according to the output of the clock detection unit 30;
A switch 32 switches between a clock signal line for an RT1 mode clock signal and a clock signal line for an RT2 mode according to the output of the mode switching unit 31, and a relay is used, for example. The output of the mode switching unit 31 is provided to a switch 32.

The mode switching section 31 takes an EOR (exclusive OR) with the RT1 clock detection section 30 and a data ready signal from the data terminal 1 to switch the mode. However, after the reset, the RT1 mode is set. RT2 clock from the driver 21;
This is to prevent the RT1 clock from the data terminal 1 from colliding on the signal line. The data ready signal ER is
It is provided to the RT1 clock detection unit 30c.

From the driver 21, received data is input to a received data terminal RD of the data terminal 1. The switch 32 is a relay switch 3 corresponding to the A line and the B line.
2A and 32B. The relay switch 32A is
The RTA line is switched, and the relay switch 32B switches the RTB line. The A line signal from the driver 21 is connected to the a contact of the relay switch 32A, and the A line signal of the receiver 22 is connected to the b contact of the relay switch 32A. The B line signal from the driver 21 is connected to the contact a of the relay switch 32B,
The line signal is connected to the contact b of the relay switch 32B.

An RT1 detection signal is output from the driver 22 and supplied to the RT1 clock detection unit 30. R
The output of the T1 clock detection unit 30 is
Given to one. A reset signal (XMRST) is given to the mode switching unit 31 (hereinafter, X added to the head of the signal name indicates negative logic).

According to the configuration of the present invention, the RT1 clock detecting section 30 detects whether the RT signal transmitted from the data terminal 1 includes the RT1 clock, and
When one clock is included, the mode is set to the RT1 mode, and when no RT1 clock is included, the mode is set to the RT2 mode, so that the characteristics (RT1 or RT2) of the data terminal 1 can be changed. This can be automatically determined on the side.

(2) In this case, a one-shot multivibrator for receiving a pulse RT1 and outputting a pulse is provided in the RT1 clock detecting section 30, and the output of the one-shot multivibrator is sent to the mode switching section 31. It is characterized by inputting and switching between the RT1 mode and the RT2 mode.

According to the configuration of the present invention, a pulse is generated from the one-shot multivibrator when the RT1 clock is included, and no clock is generated from the one-shot multivibrator when the RT1 clock is not included. By inputting the output of the one-shot multivibrator to the mode switching unit 31 as a control signal, switching between the RT1 mode and the RT2 mode can be automatically performed.

(3) The data communication system is I
TU-T Recommendation V. In the case of having a line interface conforming to R.35, if the data terminal 1 has an RT1, the data communication device 2 automatically determines that, and
It is characterized in that the T mode is set based on RT1 on the data terminal side.

According to the configuration of the present invention, the data terminal 1 is in accordance with ITU-T Recommendation V.3. In the case where the data terminal 1 has the RT1 in the case where the line interface conforms to 35, the data communication device 2 automatically recognizes the fact and automatically sets the RT mode to the RT1 of the data terminal 1. Can be.

(4) The data communication system is I
TU-T Recommendation X. In the case of having a line interface conforming to R.21, if the data terminal 1 has an RT1, the data communication device 2 automatically determines that the data terminal 1 has an RT1.
It is characterized in that the T mode is set based on RT1 on the data terminal side.

According to the configuration of the present invention, the data terminal 1 is in accordance with ITU-T Recommendation X. In the case where the data terminal 1 has the RT1 in the case of having the line interface conforming to the X.21, the data communication device 2 automatically recognizes the fact and automatically sets the RT mode to the RT1 of the data terminal 1. Can be.

(5) When the data communication device 2 supplies the data reception timing clock to the data terminal 1 or can receive the data reception timing clock from the data terminal 1,
Until the initial setting, the switch is controlled to control the RT2 clock from the data communication device and the RT1 clock from the data terminal.
The RT1 mode is set so that clocks do not collide.

According to the configuration of the present invention, until the initial setting mode (until the mode is set after the power-on reset).
By setting the RT mode to the RT1 mode,
RT1 clock from data terminal 1 and data communication device 2
From the output of the RT2 clock.

(6) When the data communication device 2 supplies the data reception timing clock to the data terminal 1 or can receive the data reception timing clock from the data terminal 1,
When the RT mode is set, it is triggered by a data ready signal from the data terminal 1 being turned on.

According to the configuration of the present invention, the data terminal 1 can reliably receive data by setting the RT mode when the data ready signal from the data terminal 1 is turned on. Becomes possible.

[0036]

Embodiments of the present invention will be described below in detail with reference to the drawings. Before describing the embodiment, the principle block diagram of FIG. 1 will be described in more detail. The ready signal from the data terminal 1 changes from "0" to "1", is output from the ER terminal, enters the RT1 clock detection unit 30, and the data terminal 1 is in a data transmission / reception ready state.

The RT1 clock detector 30 monitors whether the data terminal 1 sends out a reception timing signal (RT). On the other hand, the mode switching unit 31
Upon receiving a signal from the clock detection unit 30, the setting or switching of the reception mode is controlled based on the detection result of the RT1 clock detection unit 30.

The mode switching section 31 initially selects the relay switches 32A and 32B to the contact b (R
T1 mode). RT2 clock from the driver 21;
This is because the RT1 clock from the data terminal 1 does not collide.

Here, when the data terminal 1 has an oscillation source (clock generator) in the device and transmits an RT signal from the RTA and RTB and receives it on the data communication device 2 side, when the data communication device 2 side receives the RT signal, The signal enters the RT1 clock detector 30 as it is. The RT1 clock detection unit 30
If the RT signal includes the RT1 clock, it is detected and latched, and the latched RT signal is supplied to the mode switching unit 31.

When the mode switching unit 31 detects the presence of the RT1 signal input from the RT1 clock detection unit 30, the switch 32 keeps the RT1 mode.
Next, when the data terminal 1 has no oscillation source in the device, RT
The one-clock detector 30 cannot detect the RT1 clock and cannot latch. As a result, the mode switching unit 31
Is notified that the RT1 clock cannot be detected. Upon receiving this notification, the mode switching unit 31 sends a control signal to the switch 32, sets the relay switches 32A and 32B to the contact a side, and switches to the RT2 mode.

The data terminal 1 is connected to the data communication device 2
The RTA signal and the RTB signal generated by using the oscillation source on the side are received from the driver 21, and the RT2 clock is used as a timing clock. As a result, the data received from the driver 21 is input to the RD terminal of the data terminal 1,
The data terminal 1 takes in the received data in synchronization with the clock.

According to the configuration of the present invention, the RT1 clock detecting section 30 detects whether or not the RT1 clock transmitted from the data terminal 1 includes the RT1 clock.
When one clock is included, the mode is set to the RT1 mode, and when no RT1 clock is included, the mode is set to the RT2 mode, so that the characteristics (RT1 or RT2) of the data terminal 1 can be changed. This can be automatically determined on the side.

FIG. 2 is a block diagram showing an embodiment of the present invention. 1 are denoted by the same reference numerals. In this embodiment, the data terminal 1 has a 35
Indicates a case with an interface. 21 is V. 35 interface driver; 35 interface receiver. The RT1 clock detector 30 includes a one-shot multivibrator 30a and the one-shot multivibrator 30a.
It comprises a set / reset flip-flop 30b for receiving the Q output of the multivibrator 30a, and a selector 30c for receiving the XQ output (inverted output of Q) of the set / reset flip-flop 30b at one terminal. Here, the set / reset flip-flop 30b is used as a latch for holding data.

One-shot multivibrator 30a
, A resistor R and a capacitor C are connected as external additional elements, and a pulse width generated by the time constant of the resistor R and the capacitor C is determined. The A input of the one-shot multivibrator 30 a is connected to a common potential (zero potential), and the B input is connected to the receiver 22. Set / reset flip-flop 30b
The output of the one-shot multivibrator 30a is connected to the (latch) set terminal S, and the reset terminal R
Is connected to a common potential (0 V). Further, the common terminal is connected to the 0 terminal of the selector 30c, the output of the latch 30b is connected to the 1 terminal, and either the 1 terminal input or the 0 terminal input is selected by the data ready signal ER from the data terminal 1. It is supposed to be.

In the mode switching unit 31, reference numeral 31a denotes an inverter for inverting the output of the RT1 clock detecting unit 30, and 31b denotes a NAND gate receiving the output of the RT1 clock detecting unit 30 at one input and receiving the reset signal (XMRST) at the other input. , 31c have an inverter 3 as one input.
The output of 1a is a NAND gate that receives a reset signal at the other input. For example, a power-on reset is used as the reset signal (XMRST). The outputs of the NAND gates 31b and 31c are relay switches 3 respectively.
2A and 32B. When the output of the NAND gate 31b becomes "0", the relay switches 32A and 32B
When the output of the NAND gate 31c becomes "0", the contacts b of the relay switches 32A and 32B are connected. The operation of the system configured as described above will be described below.

(A) Operation when the data terminal 1 does not have an RT1 oscillation source FIG. 3 is a time chart showing an operation example when the data terminal 1 does not have an RT1 clock oscillation source. (A) is the RT1 signal, (b) is the RT2 signal, (c) is the data ready signal (ER), and (d) is the reset signal (XMRS).
T) and (e) are one-shot multivibrators 30
(f) is the XQ output of the latch 30b, (g) is the selector 30c output, (h) is the NAND gate 31b output, (i) is the NAND gate 31c output, and (j) is the data reception timing signal (RT). is there. (H) selects the RT2 mode with "0", and (i) selects the RT1 mode with "0".

First, an external reset signal (X
MRST) is “0” as shown in FIG.
In reset state. In this state, the NAND gate 31
The outputs of b and 31c are both "1". In this case, it is assumed that the relay switches 32A and 32B are set to the RT1 mode. In this case, both the relay switches 32A and 32B are connected to the contact b side, and are in the RT1 mode. As a result, by setting the RT mode to the RT1 mode before the initial setting mode, the RT2 clock from the driver 21 and the RT1 clock from the data terminal 1 are prevented from colliding with each other. The interface receiver 22 can be protected.

Thereafter, the reset signal changes from "0" to "1" as shown in (d), and the circuit is initialized. Next, when the data ready signal ER from the data terminal 1 is turned on ("1") at a certain timing as shown in (c), the data terminal 1 is in a transmission / reception ready state. Further, the selector 30c selects one terminal input from the zero terminal input up to that time. At this time, RT from the data terminal 1
A and RTB signals are input to the receiver 22. However, in this case, the RTA and RTB signals have RT1
Clock is not included.

That is, the RT1 signal is fixed at "0" or "1" indicating no output as shown in FIG. 7A (in the figure, the state is fixed at "0"). As a result, the one-shot multivibrator 30a does not generate a pulse. That is, the Q output is "0" as shown in (e).
Remains. Therefore, the latch 30b latches "0". When Q is "0", XQ is "1".

This XQ "1" enters the selector 30c,
One terminal input of the selector 30c is output, and the selector 30c
The output of c becomes "1". The output of the selector 30c is "1"
Then, the output of the NAND gate 31b changes from "1" to "0" as shown in (h). When the output of the NAND gate 31b becomes "0", the relay switch 32A
And 32B select the contact a side, and the RT mode becomes the RT2 mode as shown in (j).

Therefore, when the data terminal 1 does not have an oscillation source, RT2 output from the data communication device 2 side
When the signal is selected, the data terminal 1 receives the RT2 signal, uses it as a reception data timing clock, and takes in the reception data from the RD terminal.

(B) Operation when the data terminal has an RT1 oscillation source FIG. 4 is a time chart showing an operation example when the data terminal 1 has an RT1 clock oscillation source. (A) is RT
1 signal, (b) RT2 signal, (c) data ready signal (ER), (d) reset signal (XMRST),
(E) is the output of the one-shot multivibrator 30a, (f) is the XQ output of the latch 30b, (g) is the output of the selector 30c, (h) is the output of 31b, (i) is the output of 31c, and (j) is the timing. Signal (RT). (H) selects the RT2 mode with “0”, and (i) selects the RT2 mode with “0”.
Select 1 mode.

First, an external reset signal (X
MRST) is “0” as shown in FIG.
In reset state. In this state, the NAND gate 31
Since the outputs of b and 31c are both "1", the relay switches 32A and 32B are both connected to the contact b side, and are in the RT1 mode. As a result, by setting the RT mode to the RT1 mode before the initial setting mode, the RT2 clock from the driver 21 and the RT1 clock from the data terminal 1 are prevented from colliding with each other. The interface receiver 22 can be protected.

Thereafter, the reset signal changes from "0" to "1" as shown in (d), and the circuit is initialized. Next, as shown in (c), the data ready signal ER from the data terminal 1 is turned on ("1"), and at the same time, the RT1 clock is generated as shown in (a). When the data ready becomes “1”, the data terminal 1 enters a transmission / reception ready state. Further, the selector 30c selects one terminal input from the zero terminal input up to that time. At this time, the RTA and RTB signals from the data terminal 1 are being input to the receiver 22. In this case, the RTA and RTB signals have R
A T1 clock is included.

That is, the RT1 signal generates an RT1 clock that repeats changes from "0" to "1" from the data ready state as shown in FIG. This RT1 signal enters the B input of the one-shot multivibrator 30a via the receiver 22. Then, the one-shot multivibrator 30a captures the change of the RT1 clock from "0" to "1" and generates a pulse determined by the time constant of the resistor R and the capacitor C. Actually, the clock R
Since T1 is continuously input, the output of the one-shot multivibrator 30a does not have a pulse shape as shown in FIG.

One-shot multivibrator 30a
Is output to the latch 30b. The XQ output of the latch 30b changes from "1" to "0". The selector 30c outputs this "0", and this "0" is inverted by the inverter 31a to become "1". Therefore, the NAND gate 31c is inverted from "1" to "0" as shown in (i).

When the NAND gate 31c outputs "0", the relay switches 32A and 32B select the contact b, and the RT mode becomes the RT1 mode as shown in (j). Therefore, if the data terminal 1 has an oscillation source,
The RT1 signal output from the data terminal 1 is selected,
The data terminal 1 transmits the received data to the RD in synchronization with the RT1 signal.
Import from terminal.

As described above, according to this embodiment, when the RT1 clock is included, a pulse is generated from the one-shot multivibrator, and
When one clock is not included, no clock is generated from the one-shot multivibrator. By inputting the output of the one-shot multivibrator as a control signal to the mode switching unit 31, RT1
The mode and the RT2 mode can be automatically switched.

The data terminal 1 is in accordance with ITU-T Recommendation V.
In the case where the data terminal 1 has the RT1 in the case where the line interface conforms to 35, the data communication device 2 automatically recognizes the fact and automatically sets the RT mode to the RT1 of the data terminal 1. Can be.

Further, according to this embodiment, when the data communication device 2 supplies the data reception timing clock to the data terminal 1 or when the data communication device 2 can receive the data reception timing clock from the data terminal 1, the RT mode is set. When the data ready signal ER from the data terminal 1 is turned on, the RT mode is set when the data ready signal from the data terminal 1 is turned on. Then, the data terminal 1 can reliably receive the data.

In the above-described embodiment, the data terminal 1 uses the ITU-T Recommendation V. Taking an example of a case having an interface conforming to G.35. However, the present invention is not limited to this. 2
1 can be similarly applied.

Here, ITU-T Recommendation X. 21 means that the characteristics of the receiver are V.I. It is defined similarly to 35,
One of the input voltages V1 and V2 is kept at 0V, and the other is -1.
It is required that the current value when changed from 0 V to +10 V is within a predetermined region of the butterfly diagram, and when the difference between the input voltages V1 and V2 is -0.3 V or less, data "1" is output. When the difference is equal to or more than +0.3 V, the data is recognized as "0".

According to this embodiment, the data terminal 1
Is ITU-T Recommendation X. In the case where the data terminal 1 has the RT1 in the case of having the line interface conforming to the X.21, the data communication device 2 automatically recognizes the fact and automatically sets the RT mode to the RT1 of the data terminal 1. Can be.

In the above-described embodiment, a case where a relay switch is used as a switch is taken as an example. However, the present invention is not limited to this, and another switch, for example, a semiconductor switch can be used.

[0065]

As described above in detail, according to the present invention, (1) in a system in which a data terminal is connected to a data communication device and the data terminal receives data from the data communication device, In the data communication device, an RT1 clock detection unit for identifying whether or not the signal transmitted from the data terminal includes the RT1 clock, and the mode is set to either RT1 or RT2 according to the output of the RT1 clock detection unit. And a switch for switching between an RT1 mode clock signal line and an RT2 mode clock signal line according to the output of the mode switching unit. Detects whether the RT signal sent from the data terminal includes the RT1 clock,
When the clock is included, the mode is set to the RT1 mode.
By setting the mode to the T2 mode, the characteristics of the data terminal (RT1 or RT2) can be automatically determined on the data communication device side.

(2) In this case, a one-shot multivibrator for outputting a pulse in response to RT1 is provided in the RT1 clock detecting section, and an output of the one-shot multivibrator is input to the mode switching section. By switching between the RT1 mode and the RT2 mode, a pulse is generated from the one-shot multivibrator when the RT1 clock is included, and no clock is generated from the one-shot multivibrator when the RT1 clock is not included. By inputting the output of the one-shot multivibrator as a control signal to the mode switching unit,
Switching between the RT1 mode and the RT2 mode can be automatically performed.

(3) The data communication system is I
TU-T Recommendation V. In the case of having a line interface conforming to 35, if the data terminal has RT1, if the data communication device side automatically determines that, the RT mode is set based on the data terminal RT1. The data terminal is defined in ITU-T Recommendation V. In the case where the data terminal has the RT1 in the case where the line interface conforms to the standard 35, the data communication device automatically recognizes the fact and can automatically set the RT mode to the RT1 of the data terminal.

(4) The data communication system is I
TU-T Recommendation X. In the case of having a line interface conforming to X.21, if the data terminal has RT1, if the data communication device side automatically determines that, the RT mode is set based on the data terminal RT1. The data terminal is in accordance with ITU-T Recommendation X. In the case where the data terminal has RT1 in the case of having a line interface conforming to X.21, the data communication device can automatically recognize this and automatically set the RT mode to RT1 of the data terminal.

(5) Further, when the data communication device supplies a data reception timing clock to the data terminal or when the data communication device can receive the data reception clock from the data terminal 1, the data communication device controls the switch until the initial setting. By setting the RT2 clock from the data communication device and the RT1 clock from the data terminal so as not to collide with each other, the RT mode is changed to the RT1 mode until the initial setting mode (for example, until the mode is set after the power-on reset). , It is possible to prevent a collision between the output of the RT1 clock from the data terminal and the output of the RT2 clock from the data communication device.

(6) When the data communication device supplies the data receiving timing clock to the data terminal or when the data communication can be received from the data terminal, the RT terminal sets the RT mode. When the data ready signal is turned on, the RT mode is set when the data ready signal from the data terminal is turned on. It becomes possible to receive.

As described above, according to the present invention, it is possible to provide a data reception timing automatic discrimination system capable of automatically discriminating the characteristics (RT1 or RT2) of the data terminal on the data communication device side.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a time chart showing an operation example when the data terminal has no oscillation source.

FIG. 4 is a time chart showing an operation example when an oscillation source is provided on the data terminal side.

FIG. 5 is a conceptual diagram of a conventional data communication system.

FIG. 6 is an explanatory diagram of a conventional data reception timing clock setting method.

FIG. 7 is a time chart showing the operation of the conventional system.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 data terminal (DTE) 2 data communication device (DCE) 21 driver 22 receiver 30 RT1 clock detection unit 31 mode switching unit 32 switch 32A relay switch 32B relay switch

Claims (6)

[Claims] 1. A system in which a data terminal and a data communication device are connected and the data terminal receives data from the data communication device, wherein the data communication device includes an RT1 clock in a signal sent from the data terminal. And an RT1 clock detecting unit for identifying whether or not the RT1 clock is included. The mode is set to RT1 according to the output of the RT1 clock detecting unit.
Or a mode switching unit for switching between RT2 mode and RT2 mode, and a switch for switching between an RT1 mode clock signal line and an RT2 mode clock signal line by an output of the mode switching unit. Automatic identification system. 2. An RT1 clock detecting section, comprising:
2. A one-shot multivibrator for outputting a pulse in response to the input signal, wherein an output of the one-shot multivibrator is input to the mode switching unit to switch between the RT1 mode and the RT2 mode. Automatic data reception timing discrimination system. 3. The data communication system according to ITU-T Recommendation V.3. In the case of having a line interface conforming to S.35, if the data terminal has RT1 and the data communication device side automatically determines that, the RT mode is set based on the data terminal RT1. 2. The data reception timing automatic determination system according to claim 1, wherein: 4. The data communication system according to ITU-T Recommendation X.4. In the case of having a line interface conforming to X.21, if the data terminal has an RT1, the data communication device automatically determines that and sets the RT mode based on the RT1 of the data terminal. 2. The data reception timing automatic determination system according to claim 1, wherein: 5. When the data communication device supplies a data reception timing clock to the data terminal side or when the data communication device can receive the data terminal timing clock from the data terminal side, the data communication device controls the switch until the initial setting to control the switch. RT2 clock and RT1 from the data terminal
2. The data reception timing automatic determination system according to claim 1, wherein the RT1 mode is set so that clocks do not collide. 6. A data ready signal from the data terminal when setting the RT mode when the data communication device supplies a data reception timing clock to the data terminal or when the data communication device can receive the timing clock from the data terminal. 2. The data reception timing automatic determination system according to claim 1, wherein the data reception timing is turned on.