KR940006657Y1 - Selecting circuit of information i/o - Google Patents

Selecting circuit of information i/o Download PDF

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Publication number
KR940006657Y1
KR940006657Y1 KR2019880004431U KR880004431U KR940006657Y1 KR 940006657 Y1 KR940006657 Y1 KR 940006657Y1 KR 2019880004431 U KR2019880004431 U KR 2019880004431U KR 880004431 U KR880004431 U KR 880004431U KR 940006657 Y1 KR940006657 Y1 KR 940006657Y1
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South Korea
Prior art keywords
information
information transmission
reception
selection
communication device
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KR2019880004431U
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Korean (ko)
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KR890020180U (en
Inventor
신우식
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주식회사 금성사
최근선
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Priority to KR2019880004431U priority Critical patent/KR940006657Y1/en
Publication of KR890020180U publication Critical patent/KR890020180U/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/102Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/153Digital output to display device ; Cooperation and interconnection of the display device with other functional units using cathode-ray tubes

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Communication Control (AREA)

Abstract

내용 없음.No content.

Description

정보 송.수신 방법의 선택회로Selection circuit of information transmission and reception method

제1도는 본 고안에 따른 정보 송, 수신 방법 선택회로의 블록도.1 is a block diagram of an information transmission and reception method selection circuit according to the present invention.

제2도는 제1도의 요부 상세 회로도.2 is a detailed circuit diagram of the main part of FIG.

제3도는 제1도의 파형도.3 is a waveform diagram of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 정보 송, 수신 게이트 선택부 2 : 정보 송, 수신 게이트부1: information transmitting and receiving gate selecting unit 2: information transmitting and receiving gate selecting unit

3 : 송, 수신 콘트롤러 4 : RS232C 통신장치3: Transmit, Receive Controller 4: RS232C Communication Device

5 : RS422A 통신장치 6 : 정보 송, 수신 단자5: RS422A communication device 6: Information transmitting and receiving terminal

I1,I2 : 인버터 B1-B4 : 버퍼I1, I2: Inverter B1-B4: Buffer

본 고안은 정보 송, 수신 방법을 선택하는 회로에 관한 것으로 특히 키이보오드를 사용하여 사용자가 외부에서 편리하게 정보 송수신 방법을 선택할 수 있도록 하여 CRT(Cathode Ray Tube) 단말기에 적당하도록 한 정보송수신 방법 선택회로에 관한 것이다.The present invention relates to a circuit for selecting a method of transmitting and receiving information, and in particular, a method of selecting an information transmission / reception method suitable for a CRT (Cathode Ray Tube) terminal by allowing a user to conveniently select an information transmission / reception method from the outside using a key board. It is about a circuit.

종래의 정보 송, 수신 방법을 선택하는 기술은 컴퓨터용 CRT단말기의 메인보오드에서 점퍼(Jumper)를 사용하여 정보 송, 수신 방법(RS232C와 RS422A)을 선택하도록 되어 있으므로, 메인 보오드내의 스위칭 점퍼를 인위적으로 연결하여 정보 송, 수신 방법을 선택하도록 되어있다.The conventional technology for selecting information transmission and reception method is to select the information transmission and reception method (RS232C and RS422A) using a jumper on the main board of the computer CRT terminal. Therefore, the switching jumper in the main board is artificially selected. You can select the method of sending and receiving information by connecting

이러한 기존의 기술은 CRT터미날의 인터페이스(I/F) 방식을 바꾸고저할때 CRT를 해제하고 메인보오드를 꺼내어 그 안에서 RS232/422 인터페이스 회로를 찾아 인위적으로 그때그때 점퍼를 이용하여 연결해 주어야 하는 불편함이 있었으며 제품의 신뢰도가 저하되는 문제점이 있었고, 현재 단말기의 인터페이스 방법이 어떻게 세팅되었는지를 사용자가 알 수 없게 되어있다.This existing technology is inconvenient to change the interface (I / F) method of the CRT terminal, release the CRT, take out the main board, find the RS232 / 422 interface circuit in it, and then artificially connect the jumper at that time. There was a problem that the reliability of the product was deteriorated, and the user cannot know how the interface method of the current terminal is set.

이에 본 고안은 상기한 문제점을 개선시키기 위해 안출된 것으로써, 정보 송, 수신 방법의 선택을 사용자의 요구에 따라 키이보오드의 조작으로 선택하도록 한 것으로, 이하 그의 기술구성을 첨부된 도면에 따라 설명하면 다음과 같다.Accordingly, the present invention was devised to improve the above-mentioned problems, and to select the information transmission and reception method by the operation of the key board according to the user's request. Is as follows.

제1도는 본 고안에 따른 정보 송,수신 방법 선택회로의 블록도를 나타낸것으로 그의 연결구성을 살펴보면, 클럭펄스와 키이보오드 선택정보가 D-플립플롭의 정보송수신게이트 선택부(1)에 각각 인가되고, 정보 송, 수신 게이트 선택부(1)의 출력(θ,θ)은 버스버퍼게이트로된 정보 송, 수신 게이트부(2)에 각각 연결되어 정보 송,수신게이트부(2)가 일측으로 수신정보(R*D : Received Data)와 전송정보(T*D : Transmitted Data)에 의해 송, 수신 콘트롤러(3)에 연결되고, 정보 송.수신 게이트부(2)의 출력은 RS232C 통신장치(4)와 RS422A 통신장치(5)는 각각거쳐 정보 송, 수신 단자(6)에 접속되는 구성으로, 상기 회로구성중 정보 송.수신 게이트부(2)의 상세구성은 제2도에서 보는 바와 같이 2개의 인버터 게이트(I1,I2)와 4개의 버퍼 게이트(B1,B2,B3,B4)로 구성되어 있다.1 is a block diagram of an information transmission / reception method selection circuit according to the present invention. Looking at its connection configuration, clock pulses and key board selection information are applied to the information transmission / reception gate selection unit 1 of the D-Flip flop, respectively. The output (θ, θ) of the information transmission and reception gate selection section 1 is connected to the information transmission and reception gate section 2 as bus buffer gates so that the information transmission and reception gate section 2 is directed to one side. Received data (R * D: Received Data) and transmission information (T * D: Transmitted Data) are connected to the transmit / receive controller 3, and the output of the information transmit / receive gate unit 2 is RS232C communication device ( 4) and the RS422A communication device 5 are connected to the information transmission and reception terminals 6, respectively. The detailed configuration of the information transmission / reception gate section 2 in the circuit configuration is shown in FIG. It consists of two inverter gates I1 and I2 and four buffer gates B1, B2, B3 and B4.

상기 회로구성의 동작상태 및 작용효과를 첨부된 도면에 따라 설명하면 다음과 같다.The operation state and effect of the circuit configuration will be described with reference to the accompanying drawings.

제2도에서, 정보 송, 수신 게이트 선택부(1)로 인가되는 키이보오드 선택정보와 클럭펄스가 논리 하이(H)상태이면 정보 송, 수신 게이트 선택부(1)의 출력단(θ)으로는 하이(H)상태신호를, 출력단(θ)으로는 로우(L) 상태신호를 각각 출력하게 되는데, 이때 정보 송, 신게이트부(2)의 인버터(I1)출력은 로우(L)상태로 반전되어 버퍼(B2)의 제어단에 인가되어 버퍼(B2)를 인에이블(Enable)시키고, 버퍼(B4)의 제어단은 하이(H)상태가 되어 버퍼(B4)를 디스에이블(Disable)시키게 되며 버퍼(B1)의 제어단은 로우(L)상태로 되어 인에이블되고 버퍼(B3)는 인버터(12)의 하이(H)출력신호에 의해 디스에이블되게 된다.In FIG. 2, when the key board selection information and the clock pulse applied to the information transmission and reception gate selection unit 1 are at a logic high (H) state, the output transmission (θ) of the information transmission and reception gate selection unit 1 is used. The high (H) state signal is output and the low (L) state signal is output to the output terminal (θ). In this case, the information transmission and the inverter (I1) output of the new gate unit 2 are inverted to the low (L) state. Is applied to the control terminal of the buffer B2 to enable the buffer B2, and the control terminal of the buffer B4 becomes high (H) to disable the buffer B4. The control stage of the buffer B1 is set to the low L state and is enabled, and the buffer B3 is disabled by the high (H) output signal of the inverter 12.

그러므로, 상기 버퍼(B1)(B2)의 인에이블 동작에 따라 RS232C 통신장치(4)에 의해 정보가 송, 수신되게 된다.Therefore, information is transmitted and received by the RS232C communication device 4 in accordance with the enable operation of the buffers B1 and B2.

이때, RS422A 통신장치(5)는 오프된다.At this time, the RS422A communication device 5 is turned off.

그리고, 정보 송, 수신 게이트 선택부(1)로 인가되는 키이보오드 선택정보가 논리 로우(L)상태이면 정보 송, 수신 게이트 선택부(1)의 출력단(θ)으로는 로우(L)상태의 신호를 출력시키며 출력단(θ)으로는 하이(H)상태의 신호를 출력시켜 전술한 동작하는 반대로 동작하게 되는데, 이때에는 버퍼(B3)(B4)만이 인에이블되어 RS422A 통신장치(5)가 선택되게 되므로 R422A 통신장치(5)에 의해 정보가 송, 수신되게 된다.When the key board selection information applied to the information transmission / reception gate selection unit 1 is in a logic low L state, the output terminal θ of the information transmission / reception gate selection unit 1 is in a low L state. It outputs a signal and outputs a signal of a high (H) state to the output terminal (θ) to operate in the opposite manner as described above. In this case, only the buffers B3 and B4 are enabled and the RS422A communication device 5 is selected. Therefore, information is transmitted and received by the R422A communication device 5.

따라서, 본 고안에 따른 정보 송, 수신 방법의 선택회로는 이상의 설명에서와 같이, 사용자가 외부에서 키이보오드를 사용하여 키이보오드 선택 정보를 바꿔가면서 정보 송, 수신 방법을 선택하도록 되어 있으므로 제품의 신뢰도가 증진되는 효과를 갖게 된다.Therefore, the selection circuit of the information transmission and reception method according to the present invention, as described above, the user is to select the information transmission and reception method while changing the key board selection information using the key board from the outside, the reliability of the product Has the effect of being promoted.

Claims (1)

컴퓨터용 CRT 단말기에서 사용되는 정보 송, 수신 방법 선택회로에 있어서, 클럭펄스와 키이보오드 선택정보가 정보 송, 수신게이트 선택부(1)의 클럭단과 입력단에 각각 인가되고, 정보 송, 수신 게이트 선택부(1)의 출력단(θ,θ)은 송수신 콘트롤러(3)와 RS232C 통신장치(4) 및 RS422A 통신장치(5) 사이에서 인버터게이트(I1, I2)와 버퍼게이트(B1-B4)에 의해 구성된 정보 송, 수신 게이트부(2)에서 각각 연결되어 키이보오드로부터 인가되는 선택정보에 따라 통신방식(RS232C/RS422A)을 선택하도록 구성한 것을 특징으로 하는 정보 송, 수신 방법의 선택회로.In the information transmission and reception method selection circuit used in a computer CRT terminal, clock pulses and key board selection information are applied to the clock terminal and the input terminal of the information transmission and reception gate selection unit 1, respectively, and the information transmission and reception gate selection is performed. The output terminals θ and θ of the unit 1 are connected by the inverter gates I1 and I2 and the buffer gates B1 to B4 between the transmission and reception controller 3 and the RS232C communication device 4 and the RS422A communication device 5. And a communication circuit (RS232C / RS422A) selected according to selection information applied from a key board connected to each of the configured information transmission and reception gate units (2).
KR2019880004431U 1988-03-31 1988-03-31 Selecting circuit of information i/o KR940006657Y1 (en)

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KR2019880004431U KR940006657Y1 (en) 1988-03-31 1988-03-31 Selecting circuit of information i/o

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KR940006657Y1 true KR940006657Y1 (en) 1994-09-28

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KR20010083748A (en) * 2000-02-21 2001-09-01 박종섭 Output and input matching unit of communication system

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