JPH10200586A - Data signal transmission method and signal input circuit for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data signal transmission method and a signal input circuit for a semiconductor device in which a data signal is transmitted through one signal line with a simple configuration, and malfunctions due to noise hardly take place. SOLUTION: A transmission signal TD having a signal pattern where, when a data signal is at a low level 'L', a level of the signal TD becomes from '0' to '1/2VDD', when the data signal is at a high level 'H', the level of the signal TD goes from '0' to 'VDD' and at the and of data, the level of the signal TD goes from '0' to, 'VDD', to '1/2VDD' and to 'VDD', is compared with threshold voltages 'Va', 'Vb'. A clock signal CKD is generated, based on the comparison result between the voltage 'Vb' and the signal TD. A data signal DTD is generated based on the comparison result between the voltage 'Va' and the signal TD and on the clock signal. A strobe signal STB is generated by discriminating whether or not the signal TD exceeds the voltage 'Va', when the signal DTD is at a high level 'H'. The signal DTD is serial-parallel- converted to obtain a parallel data signal based on the signals CKD and STB.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data signal transmission method and a signal input circuit of a semiconductor device. More specifically, the signal level is switched between three levels to receive a transmission signal of a different signal pattern according to the logic level of the data signal and the end of the data of the data signal, and to generate the transmission signal and the threshold voltage generating means. The first and second threshold voltages are compared, and a signal pattern is determined based on the comparison result to generate a data signal, a clock signal, and a strobe signal. It can transmit and reduce malfunction due to noise.

[0002]

2. Description of the Related Art In conventional electronic equipment, for example, audio equipment and video equipment, a circuit for processing an audio signal, a circuit for processing a video signal, a circuit for driving a display element, and the like are integrated circuits. ing. In addition, a microcomputer (hereinafter, referred to as a “microcomputer”) is used to control the operation of these devices, and performs signal processing of audio and video signals integrated from the microcomputer or processing for driving display elements. Control data signals are supplied to the circuits to control the operation of these processing circuits.

Here, the supply of the control data signal from the microcomputer to the processing circuit is performed by a method as shown in FIG. FIG. 8 shows a case in which a control data signal is supplied from the microcomputer 10 to the processing circuit 20 using one signal line (hereinafter, referred to as a “one-wire interface”). In this case, the control data signal is converted into a modulation signal MD whose pulse width is switched according to the signal level of the control data signal, and is supplied to the processing circuit 20. When one word of the control data signal ends, the pulse width is set to be larger than the pulse width corresponding to the signal level of the control data signal to indicate the end of the signal.

The processing circuit 20 is supplied with a reference oscillation signal PS from an oscillation circuit 21 to be described later.
Based on S, the pulse width of modulation signal MD shown in FIG. 9 is detected, and a control data signal is generated from modulation signal MD. Note that the parentheses on the pulse of the modulation signal MD indicate the state of the control data signal.

[0005] The processing circuit 20 is provided with a serial-parallel converter (not shown) for converting serial data into parallel data using a shift register. The data is sequentially transferred to the shift register of the conversion unit.

Here, when it is detected that the pulse width of the modulation signal MD is larger than a predetermined value, the output signal of the shift register is output from the serial-parallel conversion unit as a one-word parallel control data signal.

[0007] FIG.
2 shows a case where a control data signal is supplied using two signal lines (hereinafter referred to as a “two-wire interface”). The control data signal DTA shown in FIG. 11A and the clock signal CKA shown in FIG. 11B are supplied from the microcomputer 12 to the processing circuit 22. Here, the clock signal CKA
When the control data signal DTA of one word is supplied from the microcomputer 12 to the processing circuit 22, the pulse width of the clock signal CKA is increased and the clock signal CKA is increased.
The control data signal DTA during the period when the pulse width of KA is large
Generates a pulse having a small pulse width.

The processing circuit 22 is provided with a serial-parallel converter (not shown) for converting serial data into parallel data using a shift register. While being supplied to the register and sequentially transferred based on the clock signal CKA, the processing circuit 22 compares the pulse width of the clock signal CKA with the pulse width of the control data signal DTA.

Here, when it is detected that the pulse width of the clock signal CKA is larger than the pulse width of the control data signal DTA, the output signal of the shift register is output from the serial-parallel conversion unit to a one-word parallel control data signal. Is output as

FIG. 12 also shows a two-wire interface in which the microcomputer 14 sends a control data signal DTB shown in FIG. 13A and a clock signal CK shown in FIG.
B is supplied. Here, the control data signal DTB is supplied from the output terminal 141 of the microcomputer 14 to the input terminal 241 of the processing circuit 24 via the resistor 142, for example. The output terminal 143 of the microcomputer 14 is connected to the input terminal 241 of the processing circuit 24 via the resistor 144.

Here, until the one-word control data signal DTB is supplied from the output terminal 141 of the microcomputer 14 to the processing circuit 24, the output terminal 143 of the microcomputer 14 is at the low level "L". Therefore, the voltage level of the control data signal DTB when the logic level of the control data signal DTB is the high level "H"
The voltage level when the output terminals 141 and 143 are at the high level “H” is “VDD”, and the voltage level when the output terminals 141 and 143 are the low level “L” is “0”, and the resistance values of the resistors 142 and 144 are equal. Then, when the logic level of the control data signal DTB is at the high level “H”, the voltage level becomes “(1/2)”.
VDD ”and“ 0 ”when the low level is“ L ”.

When the supply of the one-word control data signal DTB is completed, the output levels of the output terminals 141 and 143 are both set to the high level "H", and the voltage level of the control data signal DTB is set to "VDD".

The processing circuit 24 is provided with a serial-parallel converter (not shown) for converting serial data into parallel data using a shift register, and the control data signal DTB is supplied to the serial-parallel converter. The data is supplied to the register and sequentially transferred based on the clock signal CKB. In the processing circuit 24, when the voltage level of the pulse of the control data signal DTB is detected, and the pulse whose voltage level is “VDD” is detected, the output signal of the shift register is output from the serial-parallel conversion unit to the one-word parallel signal. Is output as a control data signal.

FIG. 14 shows a case where a control data signal is supplied from the microcomputer 16 to the processing circuit 36 using three signal lines (hereinafter referred to as a "3-wire interface"), and is shown in FIG. 15A. Control data signal DTC and FIG.
In addition to the clock signal CKC shown in FIG. 5B, a strobe signal STA shown in FIG.
Supplied to

The processing circuit 36 is also provided with a serial-to-parallel converter (not shown) for converting serial data into parallel data using a shift register. The data is supplied to the register and sequentially transferred based on the clock signal CKC. Also, based on the strobe signal STA, the output signal of the shift register is output from the serial-parallel converter as a one-word parallel control data signal.

[0016]

As described above, in the one-wire interface, the cost is increased because the oscillation circuit 21 is required.
Is determined to determine the end of the one-word control data signal by making the pulse width larger than a predetermined value, so that the transfer time of the control data signal becomes longer.

In the two-wire or three-wire interface, the number of signal lines increases, which increases the cost. Further, if noise is superimposed on the clock signals CKB, CKC and the strobe signal STA, a malfunction easily occurs. .

In view of the above, the present invention provides a data signal transmission method and a signal input circuit of a semiconductor device in which a data signal can be transmitted through one signal line with a simple configuration and a malfunction does not easily occur.

[0019]

According to a data signal transmission method according to the present invention, a signal level is set to a first level, a second level higher than the first level, and a second level higher than the second level. 3 to generate and transmit a transmission signal of a different signal pattern according to the logical level of the data signal to be transmitted and the end of the data of this data signal. And a first threshold voltage higher than the first level and lower than the second level, and a second threshold voltage higher than the second level and lower than the third level. Thus, the signal pattern is determined, and a data signal, a clock signal indicating the timing of the data signal, and a strobe signal indicating the end of the data of the data signal are generated.

In the signal input circuit of the semiconductor device according to the present invention, the signal level may be set to a first level, a second level higher than the first level, and a third level higher than the second level. In the semiconductor device that receives a transmission signal of a different signal pattern in accordance with the logical level of the data signal to be transmitted and the end of the data of the data signal by switching between the first level and the second level, Threshold voltage generating means for generating a small first threshold voltage and a second threshold voltage larger than the second level and smaller than the third level; and a threshold voltage generating means. Comparing the transmission signal with the first threshold voltage and the second threshold voltage, determining a signal pattern based on the comparison result, and indicating a data signal and a clock signal indicating the timing of the data signal; And it has a signal generating means for generating a strobe signal indicating the end of data of data signal.

In the present invention, for example, the transmission signal is
A first signal pattern indicating that the logic level of the data signal is low level “L”, a second signal pattern indicating that the logic level is high level “H”, and a third signal pattern indicating the end of the data signal The signal pattern is determined by comparing the transmission signal with the first threshold voltage and the second threshold voltage generated by the threshold voltage generating means, and the data pattern is determined. A signal, a clock signal, and a strobe signal are generated.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of an embodiment of the present invention, in which a transmission signal is generated by a microcomputer that controls the operation of an electronic device, for example, an audio device or a video device, and signal processing and display of the audio signal and the video signal are performed. A case is shown in which a processing circuit such as an element drive receives this transmission signal to control the operation of the processing circuit based on a control data signal from a microcomputer.

An address bus AB, a data bus DB, and a control bus CB are connected to a CPU section 32 of the microcomputer 30, and a ROM section 34 and a RAM
The unit 36 and the input / output control unit 38 are connected. A signal output unit 40 is connected to the input / output control unit 38, and a signal based on a control data signal for controlling the operation of the processing circuit 50 is sent from the signal output unit 40 to a signal input unit 52 of the processing circuit 50. A transmission signal TD having a ternary level is supplied.

The signal input section 52 of the processing circuit 50 converts the supplied transmission signal TD into a serial control data signal DT.
D, a clock signal CKD, and a strobe signal STB are generated and supplied to the serial-parallel converter 54. The serial-to-parallel converter 54 includes, for example, a shift register and a latch circuit. The control data signal DTD is captured and transferred to the shift register based on the clock signal CKD, and the output of the shift register is latched by the strobe signal. The output signal of the latch circuit is latched by the
, The serial control data signal DTD is converted into a parallel control data signal DTP. The parallel control data signal DTP is supplied to the processing unit 5
6 to perform various processes such as signal processing of audio signals and video signals and display element drive processing based on the control data signal DTP.

Next, the configuration of the signal output section 40 of the microcomputer 30 is shown in FIG. The signal output unit 40 is supplied with transmission signal generation data TA based on a control data signal for controlling the operation of the processing circuit 50 and an output control signal EN from the input / output control unit 38. This transmission signal generation data T
A is supplied to the inverter 41, the logic level of which is inverted, and the logic level of the input signal is inverted by the output control signal EN, and the output is output or the output is in a high impedance state (a so-called clocked inverter).
42. The output terminal of the clocked inverter 42 is connected to a power supply terminal 44 via a resistor 43 and grounded via a resistor 45, and a transmission signal TD is output from this output terminal.

The operation of the signal output unit 40 is shown in FIG.
When the output control signal EN is set to the low level “L”, the output of the clocked inverter 42 is set to the high impedance state. Therefore, the signal level of the transmission signal TD is a voltage level obtained by dividing the voltage supplied from the power supply terminal 44 by the resistors 43 and 45 regardless of the logical level of the transmission signal generation data TA. When the output control signal EN is set to the high level “H”, the clocked inverter 42 outputs a signal whose logic level is inverted. Therefore, when the transmission signal generation data TA is at the high level “H”, the output of the clocked inverter 42 is at the high level “H”, and when the transmission signal generation data TA is at the low level “L”, the clocked inverter 42 is at the low level. Is set to the low level “L”.

Here, it is assumed that the voltage supplied from the power supply terminal 44 is "VDD", the resistance values of the resistors 43 and 44 are equal, and the voltage level when the output of the clocked inverter 42 is at the high level "H". Is "VDD" and the voltage level when the low level is "L" is "0". When the output control signal EN is at the high level "H", the voltage level of the transmission signal TD is "(1/2) VDD". Is done. Also, when the output signal TA is at a high level “H” when the output control signal EN is at a low level “L”, the transmission signal T
The voltage level of D is set to “VDD”, and when the low level is set to “L”, the voltage level of the transmission signal TD is set to “0”.

As described above, a transmission signal having a ternary signal level is generated based on the transmission signal generation data TA and the output control signal EN, and supplied from the signal output unit 40 to the signal input unit 52 of the processing circuit 50. You. The signal output unit is shown in FIG.
The configuration shown in FIG.

A C-MOS (Complementary Met) shown in FIG.
al Oxide Semiconductor) buffer 401 is supplied with transmission signal generation data TBA from the input / output control unit 38, and the buffer 402 is provided with the input / output control unit 3
8 supplies the transmission signal generation data TBB. The outputs of the buffer 401 and the buffer 402 are resistors 403 and 4
04, the resistor 403 and the resistor 4
The transmission signal TD is output from the connection point 04.

FIG. 5 shows the operation of the signal output unit. When the transmission signal generation data TBA and TBB are both at the low level “L”, the outputs of the buffers 401 and 402 are both at the low level “L”, so that the signal level of the transmission signal TD is “0”. You. When any one of the transmission signal generation data is set to the high level “H”, the output of the buffer 401 or the buffer 402 on the side where the logical level of the transmission signal generation data is set to the high level “H” is set to the high level “H”. H ”. Here, the voltage level when the output of the buffer 402 is at the high level “H” is “VDD”,
Assuming that the resistance values of the resistors 403 and 404 are equal,
The signal level of the transmission signal is set to "(1/2) VDD". When the transmission signal generation data TBA and TBB are both at the high level “H”, the outputs of the buffers 401 and 402 are both at the high level “H”, so that the signal level of the transmission signal is “VDD”. . As described above, the signal level is 3 based on the two transmission signal generation data TBA and TBB.
A transmission signal TD having a value can be generated.

Next, the configuration of the signal input section 52 of the processing circuit 50 to which the ternary transmission signal TD is supplied is shown in FIG.
The transmission signal TD is supplied to inverting input terminals of the comparators 521 and 522. The output terminal of the comparator 521 is connected to the inverter 529 and to the non-inverting input terminal of the comparator 521 via the resistor 523. The non-inverting input terminal of the comparator 521 is connected to a power supply terminal 525 via a resistor 524.

An output terminal of the comparator 522 is connected to an R input terminal of an RS flip-flop 530, which will be described later, and is connected via a resistor 526 to the comparator 522.
Is connected to the non-inverting input terminal. The non-inverting input terminal of the comparator 522 is grounded via a resistor 527. Further, the non-inverting input terminal of the comparator 521 and the non-inverting input terminal of the comparator 522 are connected to a resistor 528.
Connected via

The output terminal of the inverter 529 is connected to the S input terminal of the RS flip-flop 530 and the clock (CLOCK) input terminal of the RS flip-flop 532.
The data (DATA) input terminal and the clock (CLOCK) input terminal of the RS flip-flop 530 are grounded. The Q output terminal of the RS flip-flop 530 is connected to the input terminal of the delay unit 534, and the output terminal of the delay unit 534 is connected to the data (DATA) input terminal of the RS flip-flop 532. The S input terminal of the RS flip-flop is grounded.

Next, the operation of the signal input unit 50 will be described with reference to FIGS. In FIG. 7, FIG. 7A shows a transmission signal TD, and the signal level of the transmission signal TD is one of three levels of "0", "(1/2) VDD", and "VDD".

Here, the resistors 524 and 52 shown in FIG.
The resistance value of 7,528 is the threshold voltage “Va” at which the voltage of the non-inverting input terminal of the comparator 521 is higher than the signal level “(1/2) VDD” and lower than the signal level “VDD”.
And the voltage at the non-inverting input terminal of the comparator 522 is set to be a threshold voltage “Vb” that is larger than “0” and smaller than the signal level “(1/2) VDD”.

For this reason, at the time point t1, the signal level of the transmission signal changes from "0" to "(1/1)" which is larger than the threshold voltage "Vb".
2) VDD ”, the output signal C of the comparator 521
MA is at high level “H” as shown in FIG. 7B, and output signal IVA of inverter 534 is at low level “L” as shown in FIG. 7C. The output signal of the comparator 522 is the clock signal CKD, and is at the low level “L” as shown in FIG. 7D. Further, the S input terminal of the RS flip-flop 530 has a low level “L”,
Since the input terminal is set to the low level “L”, the output signal RSA from the Q output terminal holds the state of the low level “L” before the time point t1. The output signal of the delay unit 534 is the control data signal DTD, and is at a low level “L” as shown in FIG. 7E. RS flip-flop 53
2 is a strobe signal S.
At time t1, the S input terminal is grounded and the R input terminal is set to high level "H", so that it is set to low level "L" as shown in FIG. 6F.

At time t2, when the signal level of the transmission signal TD is changed from "(1/2) VDD" to "0", the comparator 5
The clock signal CKD output from 22 changes from the low level “L” to the high level “H”, and the output signal CMA of the comparator 521 remains at the high level “H”. Since the S input terminal of the RS flip-flop 530 is at a low level “L” and the R input terminal is at a high level “H”, the output signal R from the Q output terminal is output.
SA keeps the state of the low level “L”, and the delay unit 5
The control data signal DTD output from 34 is kept at the low level “L”. RS flip-flop 5
At 32, since the R input terminal is at the high level “H”, the strobe signal STB output from the RS flip-flop 532 is kept at the low level “L”.

Next, when the signal level of the transmission signal TD is changed from "0" to "VDD" which is larger than "Va" at time t3, the output signal CMA of the comparator 521 is set to the low level "L". Output signal IVA of inverter 529 is at a high level “H”. Further, the comparator 522
Is set to a low level "L". In the RS flip-flop 530, since the S input terminal is at the high level “H” and the R input terminal is at the low level “L”, the output signal RSA from the Q output terminal is at the high level “H” and The output signal RSA is delayed by the delay unit 534, and the control data signal DTD from the delay circuit 534 is set to the high level “H” after a predetermined time τd has elapsed from the time point t3. RS flip-flop 53
In No. 2, since the R input terminal is changed from the high level “H” to the low level “L” and the output of the inverter 529 is changed from the low level “L” to the high level “H”,
Since the strobe signal STB output from the RS flip-flop 532 is in a state equal to the logic level of the data (DATA) input terminal at this time, that is, the logic level of the control data signal DTD from the delay unit 534, The state of level “L” is maintained.

When the signal level of the transmission signal TD is changed from "VDD" to "0" at the time point t4, the output signal CMA of the comparator 521 and the clock signal CKD from the comparator 522 are changed to the high level "H". Output signal IVA of inverter 529 is at low level “L”. In the RS flip-flop 530, the time t
2, the output signal RSA is set to the low level “L”, and the control data signal DTD from the delay unit 534 is changed to the time t.
After the elapse of the predetermined time τd from 4, the level is set to the low level “L”. The strobe signal STB from the RS flip-flop 532 is also kept at the low level "L" as at the time t2.

At time t5, when the signal level of the transmission signal TD is changed from "0" to "VDD", the output signal CMA of the comparator 521 and the
, The clock signal CKD is set to the low level “L”, and the output signal IVA of the inverter 529 is set to the high level “H”. Therefore, the RS flip-flop 5
30 is set to the high level “H”, and the control data signal DTD from the delay unit 534 is changed to the time t.
After the elapse of a predetermined time τd from 5, the high level is set to “H”. Further, the strobe signal STB from the RS flip-flop 532 is kept at a low level “L”.

Next, at time t6, when the signal level of the transmission signal TD is changed from "VDD" to "(1/2) VDD", the output signal CMA of the comparator 521 is changed to the high level "H" and the inverter is switched. The output signal IVA from 529 is at the low level “L”, but the clock signal CKD from the comparator 522 is kept at the low level “L”. Therefore, the output signal RSA from the RS flip-flop 530 becomes the output signal IV from the inverter 529.
Even if A is at low level “L”, the state of high level “H” is maintained. Also, the RS flip-flop 53
2 is at a high level “H”.
The strobe signal STB output from the −S flip-flop 532 is kept at the low level “L”.

At time t7, when the signal level of the transmission signal TD is changed from "(1/2) VDD" to "VDD", the output signal CMA of the comparator 521 is changed to the low level "L" and the signal from the inverter 529 is output. The output signal IVA is at the high level “H”, but the clock signal CKD from the comparator 522 is kept at the low level “L”.
Therefore, the output signal R of the RS flip-flop 530
SA keeps the high level “H” state, and the signal level of the control data signal DTD from the delay unit 534 also keeps the high level “H” state.

In the RS flip-flop 532, the R input terminal is changed from high level “H” to low level “L”, and the output signal I
Since VA is changed from low level “L” to high level “H”, strobe signal STB outputs data at this time.
Since the state is the same as the logical level of the (DATA) input terminal, that is, the logical level of the control data signal DTD output from the delay unit 534, it is set to the high level “H”.

When the signal level of the transmission signal TD is changed from "VDD" to "0" at the time point t8, the output signal CMA of the comparator 521 and the comparator
Is high, the output signal IVA of the inverter 529 is low and the control data signal D from the delay unit 534 is low.
TD is set to a low level "L" after a lapse of a predetermined time τd from time t8. Also, the RS flip-flop 532
In this case, since the R input terminal is at the high level “H”, the strobe signal STB is at the low level “L”.

As described above, when the signal level of the transmission signal TD falls below the threshold voltage "Vb", the clock signal CKD rises, and at the timing of this rise, the control data signal DTD changes to the serial-parallel converter. The control data signal DTD is set to a high level “H” when it is higher than the threshold voltage “Va”, and the signal level of the transmission signal TD is changed to the threshold voltage “Va”. The strobe signal STB is generated when the signal rises beyond this point, so that the output signal of the shift register of the serial-parallel converter 54 is output to the processor 56 as a one-word parallel control data signal DTP.

Therefore, the microcomputer 30 generates a signal pattern by changing the signal level of the transmission signal TD from "0" to "(1/2) VDD" when the logic level of the control data signal DT is low level "L". When the level is high, the signal level of the transmission signal TD is changed from "0" to "VDD" to generate a signal pattern. When the one-word control data signal DT is completed, the signal level of the transmission signal TD is set to "0".
Assuming that a signal pattern is generated as “VDD” → “(1/2) VDD” → “VDD”, the signal input unit 52 compares the transmission signal TD with the threshold voltages “Va” and “Vb”. Thus, the signal pattern is determined, and the control data signal DT
Since D, the clock signal CKD, and the strobe signal STB are generated, the control data signal can be easily transmitted from the microcomputer 30 to the processing circuit 50 through one signal line.

If the signal level of the transmission signal TD does not rise beyond the threshold voltage "Va" only, the strobe signal STB is not generated, so that noise is superimposed on the transmission signal TD and the signal level changes from "VDD". Even if it is set to “0”, the strobe signal STB is not generated, and it is possible to prevent an erroneous control data signal from being output from the serial-parallel converter 54.

As described above, according to the above-described embodiment,
The signal level of the ternary signal is determined based on the two threshold voltages “Va” and “Vb”, and a control data signal, a clock signal, and a strobe signal are generated based on the determination result.
For example, serial data can be transmitted by one signal line without using a reference oscillation signal for detecting a pulse width.

The above-described embodiment is merely an example. The rising of the clock signal CKD occurs when the signal level of the transmission signal TD falls below the threshold voltage "Vb" and the strobe signal STB Is generated by the transmission signal T
It is not limited to when the signal level of D rises above only the threshold voltage "Va", but may be implemented in other various ways without departing from the main features of the present application.

[0050]

According to the present invention, the transmission signal is compared with the first threshold voltage generated by the threshold voltage generating means and the second threshold voltage, thereby forming a signal pattern of the transmission signal. Once determined, a data signal, a clock signal, and a strobe signal can be generated. Therefore, for example, a serial data signal can be transmitted through one signal line without using a reference oscillation signal for detecting a pulse width.

When a parallel data signal is obtained using the data signal, the clock signal and the strobe signal,
Even if noise is superimposed on the transmission signal, incorrect parallel data can be prevented from being output.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a signal output unit.

FIG. 3 is a diagram illustrating an operation of a signal output unit.

FIG. 4 is a diagram illustrating a configuration of another signal output unit.

FIG. 5 is a diagram showing another signal output unit operation.

FIG. 6 is a diagram illustrating a configuration of a signal input unit.

FIG. 7 is a diagram illustrating an operation of a signal input unit.

FIG. 8 is a diagram showing a configuration of a one-wire interface.

FIG. 9 is a diagram for explaining the operation of the one-wire interface.

FIG. 10 is a diagram showing a configuration of a two-wire interface.

FIG. 11 is a diagram for explaining the operation of the two-wire interface.

FIG. 12 is a diagram showing a configuration of another two-wire interface.

FIG. 13 is a diagram for explaining the operation of another two-wire interface.

FIG. 14 is a diagram showing a configuration of a three-wire interface.

FIG. 15 is a diagram for explaining the operation of the three-wire interface.

[Explanation of symbols]

10, 12, 14, 16, 30 Microcomputer (microcomputer) 20, 22, 24, 26, 50 Processing circuit 21 Oscillation circuit 40 Signal output unit 52 Signal input unit 54 Serial-parallel conversion unit 56 Processing unit 521, 522 Comparator 529 Inverters 530, 532 RS flip-flop 534 Delay unit

Claims (2)

[Claims] The signal level is switched between a first level, a second level higher than the first level, and a third level higher than the second level, and a logic of a data signal to be transmitted is switched. A transmission signal having a different signal pattern according to the level and the end of the data of the data signal is generated and transmitted. The transmission signal is received, and the signal level of the transmission signal is higher than the first level. A signal pattern is determined by comparing a first threshold voltage that is larger than the second level and a second threshold voltage that is larger than the second level and smaller than the third level. Generating a data signal, a clock signal indicating the timing of the data signal, and a strobe signal indicating the end of the data of the data signal. Method. 2. The logic of a data signal to be transmitted by switching a signal level between a first level, a second level higher than the first level, and a third level higher than the second level. A semiconductor device for receiving a transmission signal having a different signal pattern according to the level and the end of the data of the data signal, wherein a first threshold voltage which is higher than the first level and lower than the second level; Threshold voltage generating means for generating a second threshold voltage higher than the second level and lower than the third level; a first threshold generated by the threshold voltage generating means A voltage and a second threshold voltage, and comparing the transmission signal, determining a signal pattern based on the comparison result, the data signal and a clock signal indicating the timing of the data signal,
A signal generating means for generating a strobe signal indicating the end of the data signal.