JP3246454B2 - Simultaneous bidirectional input / output circuit and signal transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a two-way
The present invention relates to a simultaneous bidirectional input / output circuit and a signal transfer method capable of transferring a value signal, and particularly to a simultaneous bidirectional input / output circuit and a signal transfer method capable of reducing power consumption.

[0002]

2. Description of the Related Art As a simultaneous bidirectional input / output circuit of this type, there is, for example, a binary signal transfer circuit disclosed in Japanese Patent Application Laid-Open No. 7-273748. This prevents a through current from flowing through the connection line by outputting a signal of a specific value at the time of the invalid signal when the logic levels of the signals output from the simultaneous bidirectional input / output circuits connected to each other are different. It is like that.

FIG. 7 is a circuit diagram showing the binary signal transfer circuit. That is, the binary signal transfer circuit includes the circuit 41,
42, and a transfer path 43 for connecting these circuits 41 and 42. The circuit 41 and the circuit 42 have the same configuration. The circuit 41 (42) includes an inverter 411 (421) and a complementary MOS circuit 4 of the power supply voltage VDD.
12 (422), comparators 413 and 414 (42
3, 424) and a selector 415 (425). The comparator 413 (423) generates an H signal when the input level is higher than the reference voltage VRH (VDD / 2 <VRH <VDD), and generates an L signal when the input level is lower than the reference voltage VRH. Comparator 414 (424) generates an H signal when the input level is higher than the reference voltage VRL (VDD / 2>VRL> 0), and generates an L signal when the input level is lower than the reference voltage VRL. The selector 415 (425) selects the output of the comparator 413 (423) when the output of the inverter 411 (421) is an L signal, and
When the output of (421) is an H signal, the comparator 41
4 (424) is selected.

The input terminals 410, 420 of the circuits 41, 42
Output terminals 416 for each combination of input signals at
The output signal 426 is as shown in the following (1) to (4). (1) When the input signals of the circuits 41 and 42 are both L signals The points A1 and A2 become H signals, whereby the selector 415 selects the output of the comparator 414, and the selector 425 selects the output of the comparator 424. select. The B1 point and the B2 point become L signals, whereby the comparator 4
14 and the comparator 424 output an L signal. Therefore, in this case, the output terminals 41 of both circuits 41 and 42 are used.
The L signal is output to 6,426.

(2) When both input signals to the circuit 41 and the circuit 42 are H signals The points A1 and A2 become L signals, whereby the selector 415 selects the output of the comparator 413, and the selector 425 selects the output of the comparator 423. Select the output of The B1 point and the B2 point become H signals, and the comparator 4
13 and the comparator 423 output an H signal. Therefore, in this case, the output terminals 41 of both circuits 41 and 42 are used.
H signal is output to 6,426.

(3) When the input signal of the circuit 41 is the H signal and the input signal of the circuit 42 is the L signal: The point A1 becomes the L signal, and the selector 415 selects the output of the comparator 413. The point A2 becomes the H signal, and the selector 425 selects the output of the comparator 424. Initially, the point B1 is an H signal and the point B2 is an L signal, but the potentials of the points B1 and B2 cannot be different from each other, and both converge to an intermediate level VDD / 2. Therefore, the selected comparator 413 outputs an L signal and outputs the output terminal 41 of the circuit 41.
The L signal is output to 6. Further, the selected comparator 424 outputs an H signal, and the output terminal 42 of the circuit 42
The H signal is output to 6.

(4) When the input signal of the circuit 41 is an L signal and the input signal of the circuit 42 is an H signal, the point A1 becomes an H signal, and the selector 415 selects the output of the comparator 414. The point A2 becomes the L signal, and the selector 425 selects the output of the comparator 423. Initially, the point B1 is an L signal and the point B2 is an H signal, but the potentials of the points B1 and B2 cannot be different from each other, and both converge to an intermediate level VDD / 2. Therefore, the selected comparator 414 outputs the H signal and outputs the output terminal 41 of the circuit 41.
The H signal is output to 6. Also, the selected comparator 423 outputs an L signal and outputs the output terminal 426 of the circuit 42.
Outputs an L signal.

When the above signal transfer modes are collectively expressed, regardless of the value of the input signal to the input terminal 420 of the circuit 42, the value of the input signal to the input terminal 410 of the circuit 41 It is transferred as the value of the output signal to the output terminal 426. Also, the input terminal 410 of the circuit 41
Regardless of the value of the input signal to the circuit 42, the value of the input signal to the input terminal 420 of the circuit 42 is transferred as it is to the value of the output signal to the output terminal 416 of the circuit 41.

FIG. 8 is a block diagram showing a simultaneous bidirectional input / output circuit when the binary signal transfer circuit of FIG. 7 is used.
The circuits 14 and 15 in FIG. 8 correspond to the circuits 41 and 42 in FIG. Further, the transfer path 16 in FIG. 8 corresponds to the transfer path 16 in FIG. Binary signal transfer circuit 1, first input terminals 8, 1
1, second input terminals 9, 12, AND circuits 2, 5, flip-flop circuits 3, 6, flip-flop circuits 4, 7
And output terminals 10 and 13. Binary input signals are supplied to the first input terminals 8 and 11. When the signals supplied to the first input terminals 8 and 11 are significant valid signals, the second input terminals 9 and 12 are set to H level.
When the input signal becomes an L signal, an identification signal for identifying whether the input signal is valid or invalid is supplied. The AND circuits 2 and 5 create a logical product of the input signal and its identification signal. Flip-flop circuits 3, 6
Holds the input signal to the binary signal transfer circuit 1. The flip-flop circuits 4 and 7 hold an output signal from the binary signal transfer circuit 1.

In such a configuration, the second input terminal 9,
When the identification signal supplied to 12 is an L signal indicating that it is invalid, the outputs of the AND circuits 2 and 5 become L, and the signal is held by the flip-flop circuits 3 and 6. The held signal is output to the transfer path 16 in the binary signal transfer circuit 1 as the same logic. At this time, no through current flows through the transfer path 16.

[0011]

By the way, in the binary signal transfer circuit described with reference to FIG. 7, in the above cases (3) and (4), the transfer path 43 has an intermediate level VDD / 2. For this reason, the comparators 413, 415, 423, and 424 are always in an operating state, and a through current flows through the transfer path 43, so that there is a problem that power consumption increases. By the way,
Generally, an analog type circuit is used for the comparator for performing the voltage comparison. This type of comparator consumes a large amount of power because a current is constantly flowing during operation, and it is necessary to flow a larger current to operate at high speed.

In the simultaneous bidirectional input / output circuit described with reference to FIG. 8, when the identification signal supplied to the first input terminals 8 and 11 is an L signal indicating that it is invalid, the transfer path 16
Is fixed to L, no through current flows. However, when the identification signal supplied to the first input terminals 8 and 11 is an H signal indicating that it is valid, a through current flows through the transfer path 16. That is, when the identification signal is an H signal indicating that the identification signal is valid, the above-mentioned states (1) to (4) are taken, and especially in the cases (3) and (4), the transfer path 16 is set to VDD / 2.
Therefore, there is a problem that power consumption increases because a through current flows. There is also a problem that a signal for determining whether the output data is valid or invalid is required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has the object of reducing power consumption and eliminating the need for a signal for determining whether output data is valid or invalid. And a signal transfer method.

[0014]

According to a first aspect of the present invention, there is provided a simultaneous bidirectional input / output circuit for transferring a binary signal through a transmission / reception shared transfer path, comprising: a data input comparator; A flip-flop circuit connected to the output of the comparator and holding the output of the comparator;
A first control signal input terminal for inputting a first control signal for controlling the operation of the comparator, wherein the comparator is activated when the first control signal is H,
When the control signal is low, the comparator is deactivated and the data input is applied to the input side of the comparator.
The output of the complementary MOS circuit for power is connected and
A second MOS signal is inputted to the complementary MOS circuit.
2 control signal input terminals are connected, and the second control signal
The signal becomes L in synchronization with the fall of the first control signal,
It characterized the this <br/> to a high impedance output of the complementary MOS circuit. Also, the first control signal causes the
And the complementary MOS
The output of the circuit is made high impedance by the second control signal.
It can be made to the nest. 4. The signal transfer method according to claim 3, wherein in the signal transfer method for transferring a binary signal through a shared transfer path, a first step of holding an output of the comparator, and the comparator when the first control signal is H. A second step of making the comparator inactive, a third step of making the comparator inactive when the first control signal is L, and a data output connected to the input side of the comparator.
The second control signal input terminal of the complementary MOS circuit for
1 goes low in synchronization with the fall of the control signal
Second control for setting the output of the MOS circuit to high impedance
And a fourth step of supplying a control signal . In the second to fourth steps, a first control signal is used.
To make the comparator inactive
The output of the MOS transistor is driven high by the second control signal.
It may be possible to include a step of making a piece of music . In the simultaneous bidirectional input / output circuit and the signal transfer method according to the present invention, the binary signal (transfer data) is sensed by the comparator, the data is held in the flip-flop circuit, and when the holding is completed, the comparator is switched to the first signal. By making it inactive by a control signal,
Limits the time during which the current flows when the comparator is active. Further, the complementary MOS circuit for data output is made inactive by the second control signal, and the output of the complementary MOS circuit is set to high impedance, so that the time required for the through current to flow in the transfer path is shortened.

[0015]

Embodiments of the present invention will be described below. (First Embodiment) FIG. 1 is a circuit diagram showing a binary signal transfer circuit according to a first embodiment of a simultaneous bidirectional input / output circuit of the present invention. The binary signal transfer circuit includes an inverter 51
1, a complementary MOS circuit 512 of a power supply voltage VDD, a comparator 513, a comparator 514, a selector 515, and a flip-flop circuit 516.

The comparator 513 receives the reference voltage VRH (V
When the input level is higher than DD / 2 <VRH <VDD), an H signal is generated, and when the input level is lower, an L signal is generated. The comparator 514 outputs the reference voltage VRL (VDD / 2>
When the input level is higher than VRL> 0), an H signal is generated, and when the input level is low, an L signal is generated. The selector 515 selects the output of the comparator 513 when the output of the inverter 511 is an L signal, and selects the output of the comparator 514 when the output of the inverter 511 is an H signal. The flip-flop circuit 516 holds the output signal of the selector 515.

FIG. 2 is a circuit diagram showing a simultaneous bidirectional input / output circuit according to a first embodiment of the present invention using the binary signal transfer circuit of FIG. That is, the above-described binary signal transfer circuit is incorporated in the input / output circuits 114 and 115. The simultaneous bidirectional input / output circuit includes a binary signal transfer circuit 101, input terminals 108 and 111, and flip-flop circuits 103 to 10.
6, clock input terminals 109 and 112, output terminal 11
0, 113 and signal input terminals 117, 118 as first control signal input terminals.

The input terminals 108 and 111 are supplied with binary input signals. Flip-flop circuits 103 and 10
5 holds an input signal to the binary signal transfer circuit 101. The flip-flop circuits 104 and 106 hold an output signal from the binary signal transfer circuit 101. The clock input terminals 109 and 112 are connected to the flip-flop circuit 103
To 106 are supplied. Signal input terminal 11
Reference numerals 7 and 118 denote flip-flop circuits 103 to 106 of input / output circuits 114 and 115 and comparators 513 and 5.
14, a clock signal C described later as a first control signal
Supply LK2.

Next, the operation of such a simultaneous bidirectional input / output circuit will be described with reference to the timing chart of FIG.
Output data signal D input to input terminals 108 and 111
OUT0 and DOUT1 are connected to the clock input terminal 109,
The flip-flop circuits 103 and 105 hold the clock signal CLK1 input to the 112 and output the data to a transfer path (BUS) 116 in the binary signal transfer circuit 101 as data. At the same time, the input / output circuits 114 and 1
15, the comparators 513 and 514 and the selector 51
5 (see FIG. 1), the data on the sending side is determined, and the result of the determination is held in the flip-flop circuit 516 as signals A0 and A1. The held signals A0 and A1
Are flip-flop circuits 103 for holding output data,
The flip-flop circuits 104 and 106 hold the same signal as the clock signal CLK1 input to 105.

Here, the clock signal CLK2 is input to the comparators 513 and 514 (see FIG. 1). When the clock signal CLK2 is H, the comparator 51
3,514 becomes active and current flows. On the other hand, when the clock signal CLK2 is L, the comparators 513 and 514 become inactive and the current stops. Further, the clock signal CLK2 is input to the clock terminal of the flip-flop circuit 516, and data is held at the falling edge. That is, the clock signal CLK2
Is high, comparators 513 and 514 sense input data, and when clock signal CLK2 is low, the sensed data is taken into flip-flop circuit 516.

Here, the clock signal CLK2 is generated from the clock signal CLK1. This clock signal CLK
2 indicates that the output data signals DOUT0 and DOUT1 are the flip-flop circuits 103 and 105 and the input / output circuit 11
4 and 115, when the signal is output to the transfer path 116, the necessary and sufficient delay time TD for stabilizing the signal waveform, the comparators 513 and 514 are activated, and the data is held in the flip-flop circuit 516 through the selector 515. And a necessary and sufficient pulse width TW.

Therefore, by such an operation, the time during which the comparators 513 and 514 are active and the current flows can be limited to the pulse width TW, so that the power consumption can be reduced. The comparators 513 and 51
4 can be controlled by the clock signal CLK2, thereby eliminating the need for a conventionally used signal for determining whether output data is valid or invalid.

(Second Embodiment) FIG. 4 is a circuit diagram showing a binary signal transfer circuit according to a second embodiment of the simultaneous bidirectional input / output circuit of the present invention. The binary signal transfer circuit includes an inverter 521, a two-input NAND 527, and a two-input NO
R528, a complementary MOS circuit 522 of the power supply voltage VDD, comparators 523 and 524, a selector 525, and a flip-flop circuit 526. The comparator 523 outputs the H signal when the input level is higher than the reference voltage VRH (VDD / 2 <VRH <VDD),
When it is low, an L signal is generated. Comparator 524
Generates an H signal when the input level is higher than the reference voltage VRL (VDD / 2>VRL> 0), and generates an L signal when the input level is lower. The selector 525 has a two-input NOR
When the output of 528 is an L signal, the output of the comparator 523 is selected, and when the output of 528 is an H signal, the output of the comparator 524 is selected. The flip-flop circuit 526 holds the output signal of the selector 525.

FIG. 5 is a circuit diagram showing a second embodiment of the simultaneous bidirectional input / output circuit of the present invention using the binary signal transfer circuit of FIG. That is, the simultaneous bidirectional input / output circuit
Binary signal transfer circuit 201, input terminals 208 and 211, flip-flop circuits 203 to 206, clock input terminals 209 and 212, output terminals 210 and 213, signal input terminals 217 and 218 as first control signal input terminals, and Control signal input terminal 21 as a control signal input terminal 2
9,220. Input terminals 208, 21
1 is supplied with a binary input signal. The flip-flop circuits 203 and 205 hold an input signal to the binary signal transfer circuit 201. Flip-flop circuits 204, 2
Reference numeral 06 holds an output signal from the binary signal transfer circuit 201. Clock input terminals 209 and 212 supply clock signals to flip-flop circuits 203 to 206.
The signal input terminals 217 and 218 are connected to the input / output circuits 214 and 2
The clock signal CLK2 as a first control signal is supplied to the flip-flop circuits 203 to 206 and the comparators 523 and 524 in FIG. Control signal input terminal 21
9 and 220 supply an output control signal OE to be described later as a second control signal to the input / output circuits 214 and 215.

Next, the operation of such a simultaneous bidirectional input / output circuit will be described with reference to the timing chart of FIG.
Output data signal D input to input terminals 208 and 211
OUT0 and DOUT1 are connected to a clock input terminal 209,
The flip-flop circuits 203 and 205 hold the clock signal CLK1 input to 212 and output the data to a transfer path (BUS) 216 in the binary signal transfer circuit 201 as data. At the same time, the comparators 523 and 524 in the input / output circuits 214 and 215 and the selector 5
25 (see FIG. 4), the data on the sending side is determined,
The signals are held as signals A0 and A1 in the flip-flop circuit 526 (see FIG. 4). The held signals A0 and A1
Are flip-flop circuits 203 for holding output data,
The flip-flop circuits 204 and 206 hold the same signal as the clock signal CLK <b> 1 input to 205.

Here, the clock signal CLK2 is input to the comparators 523 and 524. When the clock signal CLK2 is H, the comparators 523 and 524 become active and a current flows. The clock signal CL
When K2 is L, the comparators 523 and 524 become inactive and the current stops. Further, the clock signal CLK2 is input to the clock terminal of the flip-flop circuit 526, and data is held at the falling edge. That is, when CLK2 is H, the comparators 523, 5
At 24, the input data is sensed, and when CLK2 is L, the sensed data is taken into the flip-flop circuit 526. Next, the output control signal OE becomes L, and the output of the complementary MOS circuit 522 (see FIG. 4) becomes a high impedance state.

The clock signal CLK2 is the clock signal C
Generated from LK1. This clock signal CLK2 is
Output data signals DOUT0 and DOUT1 are supplied to flip-flop circuits 203 and 205 and input / output circuits 214 and 21.
5, when the signal is output to the transfer path 216, the necessary and sufficient delay time TD for stabilizing the signal waveform and the comparator 52
3, 524 become active and the data is transferred to the selector 52.
5 and a necessary and sufficient pulse width TW held in the flip-flop circuit.

Therefore, this allows the comparator 52
The power consumption can be reduced because the time during which 3,524 is active and the current flows can be limited to the pulse width TW. Also, in the transfer path 216, the complementary MOS
By setting the output of the circuit 522 to a high impedance state, the time required for the through current to flow can be shortened, so that power consumption can be further reduced.

[0029]

As described above, in the simultaneous bidirectional input / output circuit and the signal transfer method according to the present invention, the binary signal (transfer data) is sensed by the comparator, and the data is held in the flip-flop circuit. By making the comparator inactive at the end of the holding by the first control signal, the time during which the current flows when the comparator is active is limited. In addition, the complementary MOS circuit for data output is made inactive by the second control signal, and the output of the complementary MOS circuit is set to high impedance, so that the time required for the through current to flow in the transfer path is shortened. In addition, power consumption can be reduced, and a signal for determining whether output data is valid or invalid can be eliminated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a binary signal transfer circuit according to a first embodiment of a simultaneous bidirectional input / output circuit of the present invention.

FIG. 2 is a block diagram showing a first embodiment of a simultaneous bidirectional input / output circuit of the present invention using the binary signal transfer circuit of FIG. 1;

FIG. 3 is a timing chart for explaining the operation of the simultaneous bidirectional input / output circuit of FIG. 2;

FIG. 4 is a circuit diagram of a transfer circuit according to a second embodiment of the simultaneous bidirectional input / output circuit of the present invention.

FIG. 5 is a block diagram showing a second embodiment of the simultaneous bidirectional input / output circuit of the present invention using the binary signal transfer circuit of FIG. 4;

FIG. 6 is a timing chart for explaining the operation of the simultaneous bidirectional input / output circuit of FIG. 5;

FIG. 7 is a circuit diagram showing a conventional binary signal transfer circuit.

8 is a block diagram showing a conventional simultaneous bidirectional input / output circuit using the binary signal transfer circuit of FIG. 7;

[Description of Signs] 101, 201 Binary signal transfer circuit 103 to 106 Flip-flop circuit 108, 111 Input terminal 109, 112 Clock input terminal 110, 113 Output terminal 114, 115 Input / output circuit 116 Transfer path 117, 118 Signal input terminal 203 to 206 Flip-flop circuit 208, 211 Input terminal 209, 212 Clock input terminal 210, 213 Output terminal 214, 215 Input / output circuit 216 Transfer path 219, 220 Control signal input terminal 511, 521 Inverter 512, 522 Complementary MOS circuit 513 , 514 Comparator 515 Selector 516, 526 Flip-flop circuit 523, 524 Comparator 527 2-input NAND 528 2-input NOR

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 5/14 H03K 19/00

Claims (4)

(57) [Claims] 1. A simultaneous bidirectional input / output circuit for transferring a binary signal through a transfer path shared for transmission and reception, a comparator for data input, and a flip-flop circuit connected to an output of the comparator and holding an output of the comparator. And a first control signal input terminal for inputting a first control signal for controlling the operation of the comparator, wherein the comparator is activated when the first control signal is H, and When the control signal is L, the comparator is inactive, the input side of the comparator is connected to the output side of a complementary MOS circuit for data output, and the complementary MOS circuit is connected to the second side. A second control signal input terminal for inputting a control signal is connected, and the second control signal is a rising edge of the first control signal. L next in synchronization with the rising, simultaneous bidirectional input-output circuit, characterized in that the high impedance output of the complementary MOS circuit. 2. The method according to claim 1, wherein the first control signal causes the comparator to be inactive and the complementary M
2. The simultaneous bidirectional input / output circuit according to claim 1, wherein an output of the OS circuit is set to a high impedance by the second control signal. 3. A signal transfer method for transferring a binary signal through a shared transmission / reception transfer path, wherein: a first step of holding an output of the comparator; and when the first control signal is H, the comparator is activated. A second step of making the comparator inactive when the first control signal is L; and a second step of a data output complementary MOS circuit connected to the input side of the comparator. And supplying the second control signal to the control signal input terminal of the second control signal, which becomes L in synchronization with the fall of the first control signal and makes the output of the complementary MOS circuit a high impedance. A signal transfer method, comprising: 4. In the second to fourth steps, the comparator is made inactive by the first control signal, and the output of the complementary MOS circuit is made high impedance by the second control signal. 4. The signal transfer method according to claim 3, comprising a step.