JP2004198302A - Disconnection detecting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely detect disconnection by simple constitution. <P>SOLUTION: This circuit comprises a pulse generating part for impressing a checking pulse signal to a signal line to detect the disconnection via an impedance element, and a determination part for comparing a signal obtained from the signal line with the checking pulse signal to decide the disconnection of the signal line. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a disconnection detection circuit, and more particularly to a detection circuit for detecting a disconnection in a signal line from a signal source that generates a digital signal by a pull-up and pull-down method.
[0002]
[Prior art]
As a conventional technique related to the present invention, an inductance is connected in series to a low impedance load receiving power supply from a DC power supply, one end thereof is grounded, and a signal from an AC signal source is supplied to the inductance. A disconnection detection circuit is known which detects whether or not a low impedance load is disconnected based on the presence or absence of an AC signal generated in an inductance. (For example, see Patent Document 1).
[0003]
[Patent Document 1]
Japanese Patent Application Laid-Open No. Hei 5-94885
[Problems to be solved by the invention]
However, in such a conventional circuit, the electrical connection is a DC voltage source, a low-resistance load, a (detection point), a reactance, and ground. If the DC voltage source is regarded as a digital signal source, the digital signal obtained as the DC voltage will be short-circuited to the ground since there is no low-resistance load in series with the digital signal line. In addition, even when a low-resistance load is provided in series, the voltage level at the detection point in normal time (when there is no disconnection) is always constant at the ground level, and the voltage level of the digital signal source cannot be monitored. .
The present invention has been made in view of such circumstances, and provides a disconnection detection circuit capable of reliably detecting disconnection of a digital signal line with a simple configuration.
[0005]
[Means for Solving the Problems]
The present invention provides a pulse generation unit that applies a check pulse signal to a signal line to detect a disconnection via an impedance element, compares the signal obtained from the signal line with the check pulse signal, and disconnects the signal line. Is provided.
[0006]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram showing a basic configuration of a disconnection detection circuit according to the present invention. The disconnection detection circuit includes an impedance element Z on a signal line L connecting a signal source S for outputting a signal S1 and a signal receiving unit R. A pulse generation unit 100 for applying a check pulse signal S2 at a connection point P via a connection point P, and a determination unit 200 for comparing the signal Sx obtained from the signal line L with the check pulse signal S2 to determine disconnection of the signal line. Consists of
[0007]
Here, since the disconnection detecting circuit detects a disconnection between the signal source S and the connection point P, it is preferable that the contact point P is as close to the signal receiving unit R as possible.
In addition, the impedance element Z needs to have an impedance larger than the line impedance between the signal source S and the connection point P. Usually, a resistance element can be used for this.
Either a circuit that generates the check pulse signal S2 simultaneously with the disconnection or a circuit that constantly generates the check pulse signal S2 regardless of the disconnection can be used for the pulse generation unit 100.
Further, as the signal source S, a digital signal generation source using a pull-up and pull-down method is preferable.
[0008]
1, a check pulse signal S2 is applied to a signal line L from a pulse generation unit 100 via an impedance element Z. Therefore, when the signal line L is not disconnected, the signal Sx obtained from the signal line L is the signal S1 from the signal source S, and does not coincide with the check pulse signal S2. However, when the signal line L is disconnected, the signal Sx obtained from the signal line L becomes the check pulse signal S2. Therefore, the determination unit 200 can determine the presence / absence of disconnection of the signal line by comparing the signal Sx obtained from the signal line L with the check pulse signal S2.
In addition, the disconnection detecting circuit can be simply configured from the pulse generation unit 100 and the determination unit 200 as described above, and can reliably detect a disconnection.
[0009]
The determination unit 200 includes a comparison circuit that compares whether the signal Sx obtained from the signal line matches the check pulse signal S2, and a confirmation circuit that checks whether the match state of the comparison circuit continues for a predetermined period. It is preferable to determine that the signal line is disconnected when the signal Sx obtained from the signal line matches the check pulse signal S2 for a predetermined period. This prevents erroneous determination due to chattering, noise, or the like of the signal S1, and improves determination accuracy.
[0010]
The pulse generation unit 100 can be composed of a flip-flop that receives a signal Sx obtained from a signal line and outputs it based on a clock signal, and a NOT gate that inverts the output of the flip-flop.
[0011]
The comparison circuit includes a NOR gate and an AND gate that receive and calculate a signal obtained from the signal line and an output of the pulse generation unit, an OR gate that receives and receives an output of the NOR gate and the AND gate, and an output of the OR gate. And a flip-flop that outputs based on a clock signal.
[0012]
The confirmation circuit includes a plurality of cascade-connected flip-flops for sequentially reading the output of the comparison circuit based on a clock signal, an AND gate that receives and outputs the output of each flip-flop, and a clock that receives the output of the AND gate. It can be composed of a flip-flop that outputs based on a signal.
[0013]
Further, the pulse generation unit and the determination unit may be integrally configured using a PLD (Programmable Logic Device).
[0014]
Embodiments The present invention will be described below in detail based on embodiments shown in the drawings. This does not limit the present invention.
[0015]
FIG. 2 is a circuit diagram showing an embodiment embodying the circuit of FIG. As shown in the figure, the pulse generator 100 includes a flip-flop F1 and a NOT gate G1. The flip-flop F1 receives the signal Sx from the input terminal T1 connected to the signal line L of FIG. 1, and outputs the signal Sx to the NOT gate G1 based on the clock signal CLK input from the terminal T3. Is output to a terminal T2. Therefore, the impedance element (resistance element in this embodiment) Z shown in FIG. 1 is connected between the input terminal T1 and the output terminal T2.
Note that the flip-flop F1 is reset by receiving a reset signal RS input from the terminal T4.
[0016]
The determination unit 200 includes a comparison circuit 201 and a confirmation circuit 202. The comparison circuit 201 receives the signal Sx obtained from the signal line L via the input terminal T1 and the output signal S2 of the pulse generation unit 100 to calculate the NOR gate G2 and the AND gate G3, and the NOR gate G2 and the AND gate G3. , And an flip-flop F2 that receives the output of the OR gate G4 and outputs an output signal S3 to a terminal T5 based on the clock signal CLK.
[0017]
The confirmation circuit 202 includes six cascade-connected flip-flops F3 to F8 for sequentially reading the output signal S3 of the comparison circuit based on the clock signal CLK, and an AND gate that receives and operates each output of the flip-flops F3 to F8. G5 and a flip-flop F9 that reads the output of the AND gate G5 and outputs it as a signal S4. Note that the flip-flops F2 to F9 are also set by the reset signal RS input from the terminal T4.
[0018]
The disconnection detection operation in such a configuration will be described with reference to a time chart shown in FIG.
In the pulse generator 100, the NOT gate G1 outputs an inverted signal of the input signal Sx latched by the flip-flop F1 as the output signal S2. Assuming that the input signal Sx is constant at the high level, the output signal S2 is constant at the low level. Assuming that the input signal Sx is constant at the low level, the output signal S2 is constant at the high level. As described above, when the input signal Sx is constant, the output signal S2 does not match the input signal Sx. Now, it is assumed that the signal source S outputs the high-level signal S1 before the disconnection occurs, and the input signal Sx is constant at the high level. At this time, the output signal S2 is constant at the Low level.
[0019]
When the disconnection occurs at the time shown in FIG. 3, the output signal S2 is input as the input signal Sx via the passive element Z. Therefore, the input signal Sx immediately matches the output signal S2. Since the output signal S2 is constant at the Low level, at this moment, the input signal Sx changes from the High level to the Low level. At this moment, the output signal S2 remains unchanged at the Low level.
[0020]
Only after the clock signal CLK immediately after this, the input Sx is latched by the flip-flop F1, and the output of the flip-flop F1 changes to the low level. Therefore, at this timing, the output signal S2 changes from the Low level to the High level. At this time, the input signal Sx immediately changes from the low level to the high level. At this moment, the output signal S2 remains unchanged at the High level. At this time, the output signal S2 matches the input signal Sx (state A).
[0021]
The input signal Sx is latched by the flip-flop F1 in response to the clock signal following the clock signal CLK that has caused the state A, and the output of the flip-flop F1 changes to the high level. Therefore, at this timing, the output signal S2 changes from the High level to the Low level. At this time, the input signal Sx immediately changes from the high level to the low level. At this moment, the output signal S2 remains unchanged at the Low level. At this time, the output signal S2 matches the input signal Sx (state B).
[0022]
The input signal Sx is latched by the flip-flop F1 in response to the clock signal following the clock signal CLK that has generated the state B, and the output of the flip-flop F1 changes to low level. This is the same phenomenon as state A, and states A and B cycle.
[0023]
As described above, the pulse generator 100 operates so as to repeat the operations in the state A and the state B when the disconnection occurs. That is, only when a disconnection occurs, the output signal S2 starts oscillating a pulse at a constant period, and accordingly, the input signal Sx also becomes a pulse signal. When a disconnection occurs, the pulse signal S2 and the input signal Sx continue to match in the repetition of the state A and the state B.
[0024]
In the comparison circuit 201, the output of the NOR gate G2 becomes High when both the output signal S2 and the input signal Sx are at Low level. The output of the AND gate G3 becomes High when both the output signal S2 and the input signal Sx are at High level. The signal S3 is given by the logical sum of the NOR gate output and the AND gate output.
[0025]
Therefore, the signal S3 outputs a high-level signal when both the output signal S2 and the input signal Sx are at the low level, or when both the output signal S2 and the input signal Sx are at the high level. That is, the signal S3 becomes High level when the output signal S2 and the input signal Sx are compared and matched. At the stage before disconnection occurs, as described above, since the output signal S2 does not match the input signal Sx, the signal S3 is kept at a low level.
[0026]
If the output signal S1 of the signal source S changes from the high level to the low level in a state where no disconnection has occurred, the input signal Sx immediately changes from the high level to the low level. The output signal S2 does not change immediately due to the action of the flip-flop F1. Therefore, at this moment, the input signal Sx and the pulse signal S2 match at the Low level. However, the pulse signal S2 changes to the high level by the next clock signal CLK. Therefore, the pulse signal S2 and the input signal Sx do not match here.
[0027]
Similarly, when the disconnection does not occur and the output signal S1 changes from the low level to the high level, similarly, the input signal Sx immediately changes from the low level to the high level. The output signal S2 does not change immediately. Therefore, at this moment, the input signal Sx and the output signal S2 match at the High level. However, the output signal S2 changes to the low level by the next clock signal CLK. Therefore, the output signal S2 and the input signal Sx no longer match.
[0028]
In the state where the disconnection has not occurred, the pulse signal S2 and the input signal Sx do not continuously coincide with the synchronous clock for a period of two or more clocks.
[0029]
When the disconnection occurs, in the repetition of the state A and the state B, the output signal S2 and the input signal Sx continue to match. Therefore, the signal S3 is constant at the High level. When the signal S3 becomes High level, it is latched by the first flip-flop F3 of the check circuit 202 by the next clock signal CLK. Further, the output of the first flip-flop F3 is latched by the second flip-flop F4 by the next clock signal CLK. Further, the output of the second flip-flop F4 is latched by the third flip-flop F5 by the next clock signal CLK.
[0030]
As described above, the flip-flops F6 to F8 are sequentially latched, and when six clocks elapse with respect to the clock signal CLK, the high-level signals are latched in all the flip-flops F3 to F8.
[0031]
At this timing, all the gate inputs of the AND gate G5 which takes the logical product of the seven signals become High level, and the output turns to High level. With the next clock signal CLK, the disconnection determination signal S4 output from the flip-flop F9 changes to the high level.
[0032]
In this way, the confirmation circuit 202 sets the disconnection determination signal S4 to the high level when the signal S3 is at the high level continuously for seven clock periods with respect to the clock signal CLK. If the signal S3 is not at the high level continuously for seven clocks with respect to the synchronous clock, the disconnection determination signal S4 is at the low level. In other words, when the pulse-like output signal S2 and the input signal Sx continue to match for seven clock periods with respect to the clock signal CLK, it is determined that a disconnection state has occurred.
[0033]
In addition, the disconnection determination condition is determined by determining that the disconnection state is established when the output signal S2 and the input signal Sx continuously match for a predetermined period (here, a period of 7 clocks to the clock signal CLK). , The effect of chattering in the signal source S can be effectively removed. In addition, by configuring a synchronization circuit that latches the output of various signals using a clock signal CLK using a flip-flop, noise resistance is improved.
[0034]
By adopting the pulse generation unit 100 as in this embodiment instead of the pulse generation unit that continuously oscillates, a pulse signal is not oscillated in a non-disconnection state, and a pulse signal is oscillated only when a disconnection occurs. Therefore, the effect of reducing the influence of electromagnetic radiation on other circuits can be expected.
[0035]
【The invention's effect】
According to the present invention, there is provided a disconnection detection circuit capable of reliably detecting a disconnection with a simple configuration.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the principle of a disconnection detection circuit according to the present invention.
FIG. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a time chart showing the operation of the embodiment shown in FIG. 2;
[Explanation of symbols]
F1 flip-flop F2 flip-flop F3 flip-flop F4 flip-flop F5 flip-flop F6 flip-flop F7 flip-flop F8 flip-flop F9 flip-flop G1 NOT gate G2 NOR gate G3 AND gate G4 OR gate G5 AND gate T1 terminal T2 terminal T3 terminal T4 terminal T5 terminal T6 terminal Z Impedance element

Claims (5)

A pulse generation unit that applies a check pulse signal to a signal line to detect a disconnection via an impedance element, and compares a signal obtained from the signal line with the check pulse signal to determine a disconnection of the signal line Disconnection detection circuit consisting of a part. The determination unit includes a comparison circuit that compares whether a signal obtained from the signal line matches the check pulse signal, and a confirmation circuit that confirms whether a match state by the comparison circuit continues for a predetermined period, 2. The disconnection detecting circuit according to claim 1, wherein when the signal obtained from the signal line matches the check pulse signal for a predetermined period, it is determined that the signal line is disconnected. 3. The disconnection detection circuit according to claim 1, wherein the pulse generation unit includes a flip-flop that receives a signal obtained from the signal line and outputs the signal based on a clock signal, and a NOT gate that inverts an output of the flip-flop. The comparison circuit receives a signal obtained from the signal line and an output of the pulse generator, and performs an operation on the NOR gate and the AND gate; an OR gate operating on the output of the NOR gate and the AND gate; 4. The disconnection detection circuit according to claim 2, wherein the circuit comprises a flip-flop that outputs the signal based on a clock signal. The checking circuit includes a plurality of cascaded flip-flops for sequentially reading the output of the comparing circuit based on the clock signal, an AND gate that receives and outputs the output of each flip-flop, and a clock that receives the output of the AND gate. 3. The disconnection detection circuit according to claim 2, comprising a flip-flop that outputs based on a signal.

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