CN110138377B

CN110138377B - Latch device

Info

Publication number: CN110138377B
Application number: CN201910476094.2A
Authority: CN
Inventors: 虞蓓蕾; 高唯欢; 胡晓明
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2019-06-03
Filing date: 2019-06-03
Publication date: 2023-06-13
Anticipated expiration: 2039-06-03
Also published as: CN110138377A

Abstract

The invention discloses a latch, which comprises a first inverter input end connected with a clock signal, a second inverter input end connected with a first inverter output end, a first clock control inverter input end connected with a latch input signal D, a first inverter output end connected with a second clock control inverter output end connected with a fourth clock control inverter output end, an output end serving as an output end of the latch, a fifth inverter input end connected with the first, second and third clock control inverter output ends, and a third inverter input end connected with a fifth inverter output end; the input end of the sixth inverter is connected with the output ends of the second clocked inverter and the third inverter; the input end of the third clock control inverter is connected with the output ends of the first, second and sixth inverters; the fourth clocked inverter input is connected to the first, second, fifth and sixth inverter outputs. Compared with the prior art, the latch has better signal interference resistance and higher reliability.

Description

Latch device

Technical Field

The present invention relates to the field of integrated circuits, and more particularly to a latch.

Background

A Latch (Latch) is a logic element with a memory function of a product in a digital circuit. The latch is to temporarily store the signal to maintain a certain level state, and binary digital signals "0" and "1" can be recorded in the digital circuit. Only the state of the input is saved to the output when there is a latch signal until the next latch signal. Typically there are only two values of 0 and 1. Latches (latches) are pulse level sensitive memory cell circuits that change state under the action of a particular input pulse level.

As shown in fig. 1, a conventional latch includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a first clock control inverter ck_inv1, and a second clock control inverter ck_inv2. The first inverter INV1 inverts the clock signal CK to CKb. The first clock control inverter ck_inv1 is turned on by the clock signal control, inverts the input signal D to be a D non-signal, inverts the input signal D to be a D signal by the third inverter INV3, and outputs the D signal. Meanwhile, the D non-signal is inverted by the second inverter INV2 to be a D signal, which is latched between the second inverter INV2 and the second clocked inverter ck_inv2. When the first clock control inverter ck_inv1 is turned off under the control of the clock signal, the second clock control inverter ck_inv2 is turned on, the latched D signal is inverted to a D non-signal through the second clock control inverter ck_inv2, and is inverted to a D signal through the third inverter INV3 to be output. Such a latch may change the logic state of the latch if the latch circuit (N1 node) is disturbed by a signal such as noise when the latch signal is outputted, so that the logic state of the output is erroneously inverted.

Disclosure of Invention

The invention aims to provide a latch with better signal interference resistance and higher reliability compared with the prior art.

In order to solve the technical problems, the latch provided by the invention comprises first to fourth clock control inverters CK_INV1 to CK_INV4 and first to sixth inverters INV1 to INV6;

a first inverter INV1 having an input terminal connected to a clock signal (CK) and outputting a first clock signal CKb;

the input end of the second inverter INV2 is connected with the output end of the first inverter INV1, and the second inverter INV2 outputs a second clock signal CK1;

the input end of the first clock control inverter CK_INV1 is connected with the input signal D of the latch, the output end of the first inverter INV1 and the output end of the second inverter INV 2;

the input end of the second clock control inverter CK_INV2 is connected with the latch input signal D, the output end of the first inverter INV1 and the output end of the second inverter INV 2;

the input end of the fourth inverter INV4 is connected with the output end of the second clock control inverter CK_INV2 and the output end of the fourth clock control inverter CK_INV4, and the output end of the fourth inverter INV is used as the output end of the latch;

the input end of the fifth inverter INV5 is connected with the output end of the first clock control inverter ck_inv1, the output end of the second clock control inverter ck_inv2 and the output end of the third clock control inverter ck_inv3;

the input end of the third inverter INV3 is connected with the output end of the fifth inverter INV 5;

the input end of the sixth inverter INV6 is connected with the output end of the second clocked inverter ck_inv2 and the output end of the third inverter INV 3;

the input end of the third clock control inverter CK_INV3 is connected with the output end of the sixth inverter INV6, the output end of the first inverter INV1 and the output end of the second inverter INV 2;

the fourth clock control inverter ck_inv4 has an input terminal connected to the output terminal of the fifth inverter INV5, the output terminal of the sixth inverter INV6, the output terminal of the first inverter INV1, and the output terminal of the second inverter INV2.

The first inverter INV1 includes a first PMOS transistor and a first NMOS transistor;

the source electrode of the first PMOS transistor is connected with a power supply, the grid electrode of the first PMOS transistor is connected with the grid electrode of the first NMOS transistor to form the input end of the first inverter, the drain electrode of the first NMOS transistor is connected with the first PMOS transistor to form the output end of the first inverter INV1, and the source electrode of the first NMOS transistor is connected with the ground.

The first inverter INV1 has an output signal logic value of 1 when the clock input signal logic value is 0, and has an output signal logic value of 0 when the clock input signal logic value is 1.

The second inverter INV2 includes a second PMOS transistor and a second NMOS transistor;

the source electrode of the second PMOS transistor is connected with a power supply, the grid electrode of the second PMOS transistor is connected with the grid electrode of the second NMOS transistor to form the input end of the second inverter, the drain electrode of the second NMOS transistor is connected with the second PMOS transistor to form the output end of the second inverter INV2, and the source electrode of the second NMOS transistor is connected with the ground.

The second inverter INV2 has an output signal logic value of 1 when the clock input signal logic value is 0, and has an output signal logic value of 0 when the clock input signal logic value is 1.

The third inverter INV3 includes a third PMOS transistor and a third NMOS transistor;

the source electrode of the third PMOS transistor is connected with a power supply, the grid electrode of the third PMOS transistor is connected with the grid electrode of the third NMOS transistor to form the input end of the third inverter INV3, the drain electrode of the third PMOS transistor is connected with the drain electrode of the third NMOS transistor to form the output end of the third inverter INV3, and the source electrode of the third NMOS transistor is connected with the ground.

The third inverter INV3 has an output signal logic value of 1 when the input signal logic value is 0, and has an output signal logic value of 0 when the input signal logic value is 1.

The fourth inverter INV4 includes a fourth PMOS transistor and a fourth NMOS transistor;

the source electrode of the fourth PMOS transistor is connected with a power supply, the grid electrode of the fourth PMOS transistor is connected with the grid electrode of the fourth NMOS transistor to form the input end of the fourth inverter INV4, the drain electrode of the fourth PMOS transistor is connected with the drain electrode of the fourth NMOS transistor to form the output end of the fourth inverter INV4, and the source electrode of the fourth NMOS transistor is connected with the ground.

The fourth inverter INV4 has an output signal logic value of 1 when the input signal logic value is 0, and has an output signal logic value of 0 when the input signal logic value is 1.

The fifth inverter INV5 includes a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;

the source electrode of the fifth PMOS is connected with the source electrode of the sixth PMOS, the grid electrode of the fifth PMOS is connected with the output end of the first clock control inverter CK_INV1 and the output end of the third clock control inverter CK_INV3, the grid electrode of the sixth PMOS is connected with the output end of the second clock control inverter CK_INV2, the drain electrode of the sixth PMOS is connected with the drain electrode of the fifth NMOS to form the output end of the fifth inverter INV5, the grid electrode of the fifth NMOS is connected with the output end of the first clock control inverter CK_INV1 and the output end of the third clock control inverter CK_INV3, the source electrode of the fifth NMOS is connected with the drain electrode of the sixth NMOS, the grid electrode of the sixth NMOS is connected with the output end of the second clock control inverter CK_INV2, and the source electrode of the sixth NMOS is connected with the ground.

When the clock signal CK is 1, the first and second clocked inverters ck_inv1 and ck_inv2 are turned on and the D signal is transmitted, when the first and second clocked inverters ck_inv1 and ck_inv2 output are the same as 0, the fifth inverter INV5 inverter output is 1, and when the first and second clocked inverters ck_inv1 and ck_inv2 output are the same as 1, the fifth inverter INV5 inverter output is 0. The third clocked inverter ck_inv3 is turned off, and the D input signal is simultaneously held between the sixth inverter INV6 and the third clocked inverter ck_inv3.

The sixth inverter INV6 includes a seventh PMOS transistor, an eighth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor;

the source electrode of the seventh PMOS is connected with a power supply, the drain electrode of the seventh PMOS is connected with the source electrode of the eighth PMOS, the grid electrode of the seventh PMOS is connected with the grid electrode of the seventh NMOS to form a sixth inverter INV6, the first input end of the seventh PMOS is connected with the output end of the second clocked inverter CK_INV2, the grid electrode of the eighth PMOS is connected with the grid electrode of the eighth NMOS to form a sixth inverter INV6, the second input end of the eighth PMOS is connected with the output end of the third inverter INV3, the drain electrode of the eighth PMOS is connected with the drain electrode of the seventh NMOS to form an output end of the sixth inverter INV6, the source electrode of the seventh NMOS is connected with the drain electrode of the eighth NMOS, and the source electrode of the eighth NMOS is grounded.

When the second clocked inverter ck_inv2 and the third inverter INV3 output the same 0, the sixth inverter INV6 inverter output is 1, and when the second clocked inverter ck_inv2 and the third inverter INV3 output the same 1, the sixth inverter INV6 inverter output is 0.

Wherein the first clock control inverter ck_inv1 includes a ninth PMOS transistor, a tenth PMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor;

a source electrode of the ninth PMOS transistor is connected with a power supply, a drain electrode of the ninth PMOS transistor is connected with a source electrode of the tenth PMOS transistor, and a grid electrode of the ninth PMOS transistor is connected with an input signal D;

the grid electrode of the tenth PMOS transistor is connected with the output end of the first inverter INV1, the drain electrode of the tenth PMOS transistor is connected with the drain electrode of the ninth NMOS transistor to form the output end of the first clock control inverter CK_INV1, the source electrode of the ninth NMOS transistor is connected with the drain electrode of the tenth NMOS transistor, the grid electrode of the ninth NMOS transistor is connected with the output end of the second inverter INV2, the grid electrode of the tenth NMOS transistor is input with a signal D, and the source electrode of the tenth NMOS transistor is connected with the ground.

The first clock control inverter ck_inv1 inputs the first clock signal CKb as 0, and when the second clock signal CK1 is 1, the first clock control inverter ck_inv1 is turned on; the first clock control inverter ck_inv1 inputs the first clock signal CKb as 1, and when the second clock signal CK1 is 0, the first clock control inverter ck_inv1 is turned off;

when the logic value of the input signal D is 0, the logic value of the output signal is 1, and when the logic value of the input signal D is 1, the logic value of the output signal is 0.

Wherein the second clocked inverter ck_inv2 includes an eleventh PMOS transistor, a twelfth PMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor;

the source electrode of the eleventh PMOS transistor is connected with the power supply, the drain electrode of the eleventh PMOS transistor is connected with the source electrode of the twelfth PMOS transistor, and the grid electrode of the eleventh PMOS transistor is connected with the input signal D;

the grid electrode of the twelfth PMOS transistor is connected with the output end of the first inverter INV1, the drain electrode of the twelfth PMOS transistor is connected with the drain electrode of the eleventh NMOS transistor to form the output end of the second clock control inverter CK_INV2, the source electrode of the eleventh NMOS transistor is connected with the drain electrode of the twelfth NMOS transistor, the grid electrode of the eleventh NMOS transistor is connected with the output end of the second inverter INV2, the grid electrode of the twelfth NMOS transistor is input with a signal D, and the source electrode of the twelfth NMOS transistor is connected with the ground.

The second clocked inverter ck_inv2 inputs the first clock signal CKb as 0, and when the second clock signal CK1 is 1, the second clocked inverter ck_inv2 is turned on; the second clocked inverter ck_inv2 inputs the first clock signal CKb as 1, and when the second clock signal CK1 is 0, the second clocked inverter ck_inv2 is turned off;

Wherein the third clocked inverter ck_inv3 includes a thirteenth PMOS transistor, a fourteenth PMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor;

the grid electrode of the thirteenth PMOS is connected with the grid electrode of the fourteenth NMOS to form the input end of the third clock control inverter CK_INV3 and is connected with the output end of the sixth inverter INV6, the grid electrode of the fourteenth PMOS is connected with the output end of the second inverter INV2, the grid electrode of the thirteenth NMOS is connected with the output end of the first inverter INV1, and the drain electrode of the fourteenth PMOS is connected with the drain electrode of the thirteenth NMOS to form the output end of the third clock control inverter CK_INV3.

The third clocked inverter ck_inv3 inputs the first clock signal CKb as 0, and turns off when the second clock signal CK1 is 1; the third clocked inverter ck_inv3 inputs the first clock signal CKb as 1, and when the second clock signal CK1 is 0, the third clocked inverter ck_inv3 is turned on;

when the third clocked inverter ck_inv3 is turned on, the first clocked inverter ck_inv1 and the second clocked inverter ck_inv2 are turned off, the third clocked inverter ck_inv3 transmits the D signal (i.e., the latch signal) transmitted when the first clocked inverter ck_inv1 and the second clocked inverter ck_inv2 are turned on before the latch signal is 0, the logic value of the output signal is 1, and when the latch signal is 1, the logic value of the output signal is 0.

Wherein the fourth clock control inverter ck_inv4 includes a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, and a seventeenth NMOS transistor;

the source electrode of the fifteenth PMOS is connected with a power supply, the grid electrode of the fifteenth PMOS is connected with the grid electrode of the sixteenth NMOS to form a first input end of a fourth clock control inverter CK_INV4 and is connected with the output end of a fifth inverter INV5, the drain electrode of the fifteenth PMOS is connected with the source electrode of the sixteenth PMOS, the grid electrode of the sixteenth PMOS is connected with the grid electrode of the seventeenth NMOS to form a second input end of the fourth clock control inverter CK_INV4 and is connected with the output end of a sixth inverter INV6, the drain electrode of the sixteenth PMOS is connected with the source electrode of the seventeenth PMOS, the drain electrode of the seventeenth PMOS is connected with the drain electrode of the seventeenth NMOS to form an output end of the fourth clock control inverter CK_INV4 and is connected with the output end of the second clock control unit CK_INV2 and the input end of the fourth inverter INV4, the grid electrode of the fifteenth PMOS is connected with the output end of the first inverter INV1, the source electrode of the fifteenth NMOS is connected with the drain electrode of the sixteenth NMOS, and the drain electrode of the seventeenth NMOS is connected with the seventeenth source electrode of the seventeenth NMOS is connected with the ground.

The clock signal CK of the present invention is inverted to CKb by the first inverter and then to CK1 by the second inverter. The clocks inside the circuit are controlled by the signals of CKB and CK1. The input signal D is transmitted through two identical sets of clocked inverters, respectively. When the first and second clocked inverters are clocked on, the input signal D is inverted to D not by the second clocked inverter and then inverted to D by the fourth clocked inverter to the output. While the input signal D sequentially passes through the latch loops of the first clocked inverter, the fifth inverter, the third inverter, and the sixth inverter, locking the signal D between the third clocked inverter and the sixth inverter. When the clock signal is turned over, the first clock control inverter, the second clock control inverter and the third clock control inverter are turned on, the D signal passes through the latch loop, the fourth clock control inverter and the fourth inverter is transmitted to the output end. Internal nodes are added in the latch loop, the internal nodes are mutually influenced, when any internal node is subjected to signal interference errors, the latch can be adjusted and recovered through other nodes, and meanwhile, the output result of the latch is not influenced. As shown in fig. two, the loop internal nodes S1 to S4 are latched. When latching the output, S1 is connected to one of the inputs, since the fifth inverter has two different sets of input controls. Therefore, when the S1 node is interfered with and is in error, the fifth inverter is turned off, the S2 node is not affected, and meanwhile, the logic state of the S1 node is recovered by the S4 node through the third clock control inverter. Similarly, when the S2 node is disturbed, the S3 node is affected, but at the same time, the logic state of the S2 node is recovered by the S1, S5 node through the fifth inverter, and then the S3 node is recovered through the third inverter. When the S3 node is disturbed, it is recovered by the S2 node through a third inverter. When the S4 node is disturbed, the S1 node is affected, but at the same time the logic function of the S4 is recovered by the S3, S5 node through the sixth inverter. Thus, the anti-signal interference capability of the latch is effectively improved, and the reliability of the circuit is improved.

Drawings

The invention is described in further detail below with reference to the attached drawings and detailed description:

fig. 1 is a circuit configuration of a conventional latch.

FIG. 2 is a schematic diagram of a latch structure provided by the present invention.

FIG. 3 is a schematic diagram of simulated waveforms of internal nodes of a latch loop of the conventional latch of FIG. 1 subject to signal interference.

Fig. 4 to 7 are schematic diagrams of simulated waveforms of the internal nodes S1 to S4 of the latch circuit of the latch according to the present invention, respectively, which are subject to signal interference.

Description of the reference numerals

Ck_inv1 to ck_inv4 represent first to fourth clock-controlled inverters

INV1 to INV6 represent first to sixth inverters

N1, S1-S4 represent different electrical nodes

D represents the D input signal

CK represents clock signal

CKB represents the first clock signal, i.e. CK after processing by the first inverter

CK1 represents a second clock signal, i.e. CKB processed by a second inverter

Q is the latch output signal.

Detailed Description

Other advantages and technical effects of the present invention will become more fully apparent to those skilled in the art from the following disclosure, which is a detailed description of the present invention given by way of specific examples. The invention may be practiced or carried out in different embodiments, and details in this description may be applied from different points of view, without departing from the general inventive concept. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.

Referring to fig. 2, a possible embodiment of the latch provided by the present invention includes first to fourth clock control inverters ck_inv1 to ck_inv4 and first to sixth inverters INV1 to INV6;

The present invention provides a possible embodiment of the first inverter INV1, including: a first PMOS transistor and a first NMOS transistor;

The present invention provides a possible embodiment of the second inverter INV2 comprising: a second PMOS transistor and a second NMOS transistor;

The present invention provides a possible embodiment of the third inverter INV3 comprising: a third PMOS transistor and a third NMOS transistor;

The present invention provides a possible embodiment of the fourth inverter INV4 comprising: a fourth PMOS transistor and a fourth NMOS transistor;

The present invention provides a possible embodiment of the fifth inverter INV5 comprising: a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;

The present invention provides a possible embodiment of the sixth inverter INV6 comprising: a seventh PMOS transistor, an eighth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor;

the grid electrode of the seventh PMOS is connected with the grid electrode of the seventh NMOS to form a sixth inverter INV6, the first input end of the sixth inverter INV6 is connected with the output end of the second clock control inverter CK_INV2, the grid electrode of the eighth PMOS is connected with the grid electrode of the eighth NMOS to form a sixth inverter INV6, the second input end of the eighth PMOS is connected with the output end of the third inverter INV3, and the drain electrode of the eighth PMOS is connected with the drain electrode of the seventh NMOS to form the output end of the sixth inverter INV 6.

When the first and second clocked inverters ck_inv1 and ck_inv2 output are the same as 0, the sixth inverter INV6 inverter output is 1, and when the first and second clocked inverters ck_inv1 and ck_inv2 output are the same as 1, the sixth inverter INV6 inverter output is 0.

The present invention provides a possible embodiment of the first clock-controlled inverter ck_inv1 comprising: a ninth PMOS transistor, a tenth PMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor;

A possible embodiment of the second clocked inverter CK_INV2 includes an eleventh PMOS transistor, a twelfth PMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor;

A possible embodiment of the third clocked inverter CK_INV3 includes a thirteenth PMOS transistor, a fourteenth PMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor;

The present invention provides a fourth clock-controlled inverter ck_inv4, which comprises: a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, and a seventeenth NMOS transistor;

The present invention has been described in detail by way of specific embodiments and examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims

1. A latch, comprising: first to fourth clock control inverters (ck_inv1 to ck_inv4) and first to sixth inverters (inv1 to INV 6);

a first inverter (INV 1) having an input terminal connected to the clock signal (CK) and outputting a first clock signal (CKb);

a second inverter (INV 2) whose input end is connected to the output end of the first inverter (INV 1) and which outputs a second clock signal (CK 1);

a first clock control inverter (CK_INV1), the input end of which is connected with the input signal D of the latch, the first control end of which is connected with the output end of the first inverter (INV 1), and the second control end of which is connected with the output end of the second inverter (INV 2);

a second clocked inverter (ck_inv2) having an input connected to the latch input signal D, a first control connected to the output of the first inverter (INV 1), and a second control connected to the output of the second inverter (INV 2);

a fourth inverter (INV 4) having an input connected to the output of the second clocked inverter (ck_inv2) and the output of the fourth clocked inverter (ck_inv4), and an output serving as the output of the latch;

a fifth inverter (INV 5) having a first input connected to the output of the first clocked inverter (ck_inv1) and the output of the third clocked inverter (ck_inv3) and a second input connected to the output of the second clocked inverter (ck_inv2);

the input end of the third inverter (INV 3) is connected with the output end of the fifth inverter (INV 5);

a sixth inverter (INV 6) having a first input connected to the output of the second clocked inverter (ck_inv2) and a second input connected to the output of the third inverter (INV 3);

a second control end of the third clock control inverter (CK_INV3) is connected with the output end of the first inverter (INV1), the first control end of the third clock control inverter is connected with the output end of the second inverter (INV 2), and the input end of the third clock control inverter is connected with the output end of the sixth inverter (INV 6);

and a fourth clock control inverter (ck_inv4) having a second control terminal connected to the output terminal of the first inverter (INV 1), a first control terminal connected to the output terminal of the second inverter (INV 2), a first input terminal connected to the output terminal of the fifth inverter (INV 5), and a second input terminal connected to the output terminal of the sixth inverter (INV 6).

2. The latch according to claim 1, wherein: the first inverter (INV 1) includes a first PMOS transistor and a first NMOS transistor;

the source electrode of the first PMOS transistor is connected with a power supply, the grid electrode of the first PMOS transistor is connected with the grid electrode of the first NMOS transistor to form the input end of the first inverter, the drain electrode of the first NMOS transistor is connected with the first PMOS transistor to form the output end of the first inverter (INV 1), and the source electrode of the first NMOS transistor is connected with the ground.

3. The latch according to claim 2, wherein: the first inverter (INV 1) has an output signal logic value of 1 when the clock input signal logic value is 0, and has an output signal logic value of 0 when the clock input signal logic value is 1.

4. The latch according to claim 1, wherein: the second inverter (INV 2) includes a second PMOS transistor and a second NMOS transistor;

the source electrode of the second PMOS transistor is connected with a power supply, the grid electrode of the second PMOS transistor is connected with the grid electrode of the second NMOS transistor to form the input end of the second inverter, the drain electrode of the second NMOS transistor is connected with the second PMOS transistor to form the output end of the second inverter (INV 2), and the source electrode of the second NMOS transistor is connected with the ground.

5. The latch according to claim 4, wherein: the second inverter (INV 2) has an output signal logic value of 1 when the clock input signal logic value is 0, and has an output signal logic value of 0 when the clock input signal logic value is 1.

6. The latch according to claim 1, wherein: the third inverter (INV 3) includes a third PMOS transistor and a third NMOS transistor;

the source electrode of the third PMOS transistor is connected with a power supply, the grid electrode of the third PMOS transistor and the grid electrode of the third NMOS transistor are connected to form the input end of the third inverter (INV 3), the drain electrode of the third PMOS transistor and the drain electrode of the third NMOS transistor are connected to form the output end of the third inverter (INV 3), and the source electrode of the third NMOS transistor is connected to the ground.

7. The latch according to claim 6, wherein: the third inverter (INV 3) has an output signal logic value of 1 when the input signal logic value is 0, and has an output signal logic value of 0 when the input signal logic value is 1.

8. The latch according to claim 1, wherein: the fourth inverter (INV 4) includes a fourth PMOS transistor and a fourth NMOS transistor;

the source electrode of the fourth PMOS transistor is connected with a power supply, the grid electrode of the fourth PMOS transistor and the grid electrode of the fourth NMOS transistor are connected to form the input end of the fourth inverter (INV 4), the drain electrode of the fourth PMOS transistor and the drain electrode of the fourth NMOS transistor are connected to form the output end of the fourth inverter (INV 4), and the source electrode of the fourth NMOS transistor is connected to the ground.

9. The latch according to claim 8, wherein: the fourth inverter (INV 4) has an output signal logic value of 1 when the input signal logic value is 0, and has an output signal logic value of 0 when the input signal logic value is 1.

10. The latch according to claim 1, wherein: the fifth inverter (INV 5) includes a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;

the source electrode of the fifth PMOS is connected with the source electrode of the sixth PMOS, the grid electrode of the fifth PMOS is connected with the output end of the first clock control inverter (CK_INV1) and the output end of the third clock control inverter (CK_INV3), the grid electrode of the sixth PMOS is connected with the output end of the second clock control inverter (CK_INV2), the drain electrode of the sixth PMOS is connected with the drain electrode of the fifth NMOS to form the output end of the fifth inverter (INV 5), the grid electrode of the fifth NMOS is connected with the output end of the first clock control inverter (CK_INV1) and the output end of the third clock control inverter (CK_INV3), the source electrode of the fifth NMOS is connected with the drain electrode of the sixth NMOS, the grid electrode of the sixth NMOS is connected with the output end of the second clock control inverter (CK_INV2), and the source electrode of the sixth NMOS is connected with the ground.

11. The latch according to claim 10, wherein: when the clock signal CK is 1, the first clocked inverter (ck_inv1) and the second clocked inverter (ck_inv2) are turned on and the D signal is transmitted, when the first clocked inverter (ck_inv1) and the second clocked inverter (ck_inv2) output are the same as 0, the fifth inverter (INV 5) inverter output is 1, when the first clocked inverter (ck_inv1) and the second clocked inverter (ck_inv2) output are the same as 1, the fifth inverter (INV 5) inverter output is 0, the third clocked inverter (ck_inv3) is turned off, and the D input signal is simultaneously held between the sixth inverter (INV 6) and the third clocked inverter (ck_inv3).

12. The latch according to claim 1, wherein: the sixth inverter (INV 6) includes a seventh PMOS transistor, an eighth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor;

the source electrode of the seventh PMOS is connected with a power supply, the drain electrode of the seventh PMOS is connected with the source electrode of the eighth PMOS, the grid electrode of the seventh PMOS is connected with the grid electrode of the seventh NMOS to form the output end of the sixth inverter (INV 6), the first input end of the eighth PMOS is connected with the output end of the second clocked inverter (CK_INV2), the grid electrode of the eighth PMOS is connected with the grid electrode of the eighth NMOS to form the second input end of the sixth inverter (INV 6) and the output end of the third inverter (INV 3), the drain electrode of the eighth PMOS is connected with the drain electrode of the seventh NMOS to form the output end of the sixth inverter (INV 6), the source electrode of the seventh NMOS is connected with the drain electrode of the eighth NMOS, and the source electrode of the eighth NMOS is grounded.

13. The latch according to claim 12, wherein: when the outputs of the second clocked inverter (ck_inv2) and the third inverter (INV 3) are the same as 0, the inverter output of the sixth inverter (INV 6) is 1, and when the outputs of the second clocked inverter (ck_inv2) and the third inverter (INV 3) are the same as 1, the inverter output of the sixth inverter (INV 6) is 0.

14. The latch according to claim 1, wherein: a first clock control inverter (ck_inv1) including a ninth PMOS transistor, a tenth PMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor;

the grid electrode of the tenth PMOS transistor is connected with the output end of the first inverter (INV 1), the drain electrode of the tenth PMOS transistor is connected with the drain electrode of the ninth NMOS transistor to form the output end of the first clock control inverter (CK_INV1), the source electrode of the ninth NMOS transistor is connected with the drain electrode of the tenth NMOS transistor, the grid electrode of the ninth NMOS transistor is connected with the output end of the second inverter (INV 2), the grid electrode of the tenth NMOS transistor is input with a signal D, and the source electrode of the tenth NMOS transistor is connected with the ground.

15. The latch according to claim 14, wherein: when the first clock signal (CKB) is input into the first clock control inverter (CK_INV1) to be 0 and the second clock signal (CK 1) is input into the second clock control inverter (CK_INV1), the first clock control inverter (CK_INV1) is turned on; the first clock control inverter (ck_inv1) inputs a first clock signal (CKb) of 1, and when the second clock signal (CK 1) is 0, the first clock control inverter (ck_inv1) is turned off;

16. The latch according to claim 1, wherein: a second clocked inverter (ck_inv2) including an eleventh PMOS transistor, a twelfth PMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor;

the grid electrode of the twelfth PMOS transistor is connected with the output end of the first inverter (INV 1), the drain electrode of the twelfth PMOS transistor is connected with the drain electrode of the eleventh NMOS transistor to form the output end of the second clocked inverter (CK_INV2), the source electrode of the eleventh NMOS transistor is connected with the drain electrode of the twelfth NMOS transistor, the grid electrode of the eleventh NMOS transistor is connected with the output end of the second inverter (INV 2), the grid electrode of the twelfth NMOS transistor is input with a signal D, and the source electrode of the twelfth NMOS transistor is connected with the ground.

17. The latch according to claim 16, wherein: the second clocked inverter (ck_inv2) is turned on when the first clock signal (CKb) is 0 and the second clock signal (CK 1) is 1; the second clocked inverter (ck_inv2) inputs the first clock signal (CKb) as 1, and when the second clock signal (CK 1) is 0, the second clocked inverter (ck_inv2) is turned off;

18. The latch according to claim 1, wherein: a third clocked inverter (ck_inv3) including a thirteenth PMOS transistor, a fourteenth PMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor;

the grid electrode of the thirteenth PMOS is connected with the grid electrode of the fourteenth NMOS to form the input end of a third clock control inverter (CK_INV3) and is connected with the output end of a sixth inverter (INV 6), the grid electrode of the fourteenth PMOS is connected with the output end of the second inverter (INV 2), the grid electrode of the thirteenth NMOS is connected with the output end of the first inverter (INV 1), and the drain electrode of the fourteenth PMOS is connected with the drain electrode of the thirteenth NMOS to form the output end of the third clock control inverter (CK_INV3).

19. The latch according to claim 18, wherein: the third clocked inverter (ck_inv3) is turned off when the first clock signal (CKb) is 0 and the second clock signal (CK 1) is 1; the third clocked inverter (ck_inv3) is turned on when the first clock signal (CKb) is 1 and the second clock signal (CK 1) is 0;

when the third clocked inverter (ck_inv3) is turned on, the first clocked inverter (ck_inv1) and the second clocked inverter (ck_inv2) are turned off, the D signal (i.e., the latch signal) transmitted when the first clocked inverter (ck_inv1) and the second clocked inverter (ck_inv2) are turned on before the third clocked inverter (ck_inv3) is transmitted, the logic value of the output signal is 1 when the latch signal is 0, and the logic value of the output signal is 0 when the latch signal is 1.

20. The latch according to claim 1, wherein: a fourth clock control inverter (ck_inv4) including a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, and a seventeenth NMOS transistor;

the source electrode of the fifteenth PMOS is connected with a power supply, the grid electrode of the fifteenth PMOS is connected with the grid electrode of the sixteenth NMOS to form a first input end of a fourth clock control inverter (CK_INV4) and is connected with the output end of a fifth inverter (INV 5), the drain electrode of the fifteenth PMOS is connected with the source electrode of the sixteenth PMOS, the grid electrode of the sixteenth PMOS is connected with the grid electrode of the seventeenth NMOS to form a second input end of the fourth clock control inverter (CK_INV4) and is connected with the output end of a sixth inverter (INV 6), the drain electrode of the sixteenth PMOS is connected with the source electrode of the seventeenth PMOS, the grid electrode of the seventeenth PMOS is connected with the drain electrode of the seventeenth NMOS to form the output end of the fourth clock control inverter (CK_INV4) and is connected with the output end of the fourth clock control unit (CK_INV2), the grid electrode of the fifteenth NMOS is connected with the output end of the first inverter (INV 1), the drain electrode of the sixteenth NMOS is connected with the drain electrode of the seventeenth NMOS, and the drain electrode of the seventeenth NMOS is connected with the ground.