CN105897223A - D trigger resistant to single event upset - Google Patents
D trigger resistant to single event upset Download PDFInfo
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- CN105897223A CN105897223A CN201610196541.5A CN201610196541A CN105897223A CN 105897223 A CN105897223 A CN 105897223A CN 201610196541 A CN201610196541 A CN 201610196541A CN 105897223 A CN105897223 A CN 105897223A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
Abstract
The invention discloses a D trigger resistant to single event upset. The D trigger is formed by master and slave latches connected in series. The master latch and the slave latch have completely same structure. The core of a latch is no longer composed of two end-to-end inverters, but six PMOS transistors P1 to P6 and six NMOS transistors N1 to N6. The master latch or the slave latch of the invention can be formed by adding a clock-controlled transistor to the core of the latch. Compared with triplication redundancy in the prior art, the D trigger not only save the area of an election circuit, but also eliminate single event sensitivity due to the election circuit. Further, the D trigger is lower in single event sensitivity and better in single event upset resistance when storing a numerical value 0. Since many triggers are required to hold the same numerical value for a long time in practical application, the invention is significant to enhance the single event upset resistance of the kind of the triggers.
Description
Technical field
The present invention relates to trigger in integrated circuit fields, especially primary particle inversion resistant d type flip flop under radiation environment.
Background technology
Cosmic space exists a large amount of high energy particle (proton, heavy ion etc.) and high-energy ray.Timing unit in integrated circuit,
Such as trigger, after the bombardment by these high energy particles and ray, (Single Event Upset is called for short to produce single-particle inversion
SEU).The generation of single-particle inversion can produce soft error, so that integrated circuit operational is made mistakes.Along with holding of process
Continuous reduction, integrated circuit transistor density continues to increase, and the probability that multiple transistors are bombarded by single-particle simultaneously is greatly promoted,
And the reduction of the size of transistor own makes the critical charge representing device state persistently reduce, and this is to trigger under nanoscale
Design brings challenge greatly.On the one hand, the multinode charge-trapping that multiple transistors are caused by bombardment simultaneously can bring single-particle
Multiple-bit upsets (Multiple Cell Upset is called for short MCU)；On the other hand, multinode charge-trapping makes a lot of tradition simultaneously
Trigger reinforcement design technology (such as double interlocking unitDualInterlockedCeLl (being called for short DICE) etc.) consolidation effect is significantly
Weaken.Thus under nanoscale, design novel highly reliable anti-single particle T-flip flop circuit and seem necessary.
Common d type flip flop, as it is shown in figure 1, be in series by principal and subordinate's two stage latch (Latch), is designated as main Latch and from Latch,
Main Latch is the same with the logical construction from Latch, all as shown in Fig. 2 (a), by the input inverter Inv1 of 2 band clock controls
Constitute with feedback inverter Inv2 and 1 phase inverter without clock control (being designated as the 3rd phase inverter Inv3).Input is anti-
Receiving data-signal D to the input of device, output is connected with node M N, separately has two input end of clock to receive clock respectively
Signal CLK andFrom the perspective of function, as shown in Fig. 2 (b), feedback inverter Inv2 and the 3rd phase inverter Inv3
Join end to end and constitute storage organization or the kernel of Lacth, the input of the 3rd phase inverter Inv3 of Latch in common d type flip flop
End connects node MN, and node M N is connected with the output of input inverter Inv1, and the output of the 3rd phase inverter Inv3 connects
Node M and the input of feedback inverter Inv2, node M is actually directly connected to the output Q of Latch；Feed back anti-phase
The input of device Inv2 is connected with node M, and output is connected with node M N, when separately having two input end of clock to receive respectively
Clock signal CLK and
Shown in realization such as Fig. 3 (a) of 3rd phase inverter, by PMOS transistor P0With a nmos pass transistor N0Composition,
Wherein PMOS transistor be connected with the drain electrode of nmos pass transistor constitute phase inverter output Y, and PMOS transistor and
The grid of nmos pass transistor is connected and constitutes the input A of phase inverter；The source electrode of PMOS transistor is connected on power vd D,
And the source electrode of nmos pass transistor is connected on ground VSS.As shown in Fig. 3 (b)-(d), the input inverter or anti-of band clock control
Feedback phase inverter is then by 2 PMOS transistor P1And P2And 2 nmos pass transistor N1And N2Composition, has 3 kinds of realizations
Mode.Making a general survey of this 3 kinds of ways of realization, they are all (by PMOS transistor P at the 3rd phase inverter shown in Fig. 3 (a)1With
Nmos pass transistor N1Constitute) on the basis of add a clock control PMOS transistor P2With a clock control
Nmos pass transistor N2；And its transistor increased or be connected in series as shown in Fig. 3 (b)-(c), or such as Fig. 3 (d)
The shown output being connected to phase inverter with the form of transmission gate (Transmission Gate, TG).Transmission gate is by a PMOS
Transistor and a nmos pass transistor composition, wherein PMOS transistor is connected with each other with the source electrode of nmos pass transistor, leaks
Pole is also connected with each other, and respective grid is controlled the source electrode break-make to drain electrode by external control signal.It should be noted that band
In the input inverter of clock control, clock signal is 180 degree with clock signal phase difference in the feedback inverter of band clock control.
It is to say, when in the input inverter of band clock control, the grid of PMOS transistor P2 is connected to certain external signal CLK,
With PMOS transistor P in the feedback inverter of clock control2Grid be connected to by CLK signal through one phase inverter produce CLK
Non-signalOn.
T.Calin et al. delivers on IEEE Transaction on Nuclear Science (IEEE atomic energy science journal)
" Upset hardened memory design for submicro CMOS Technology " (anti-upset in sub-micron CMOS technology
The memory cell design reinforced) (phase December the 6th in 1996 volume 43, the 2874-2878 page) propose DICE first
Structure, this structure uses the form of double interlocking, can effectively suppress single-particle inversion under micron and submicrometer processing, thus to mesh
DICE structure extensive application triggers Design of Reinforcement till before.But under nanometer technology, N.Gaspard et al. is at IEEE
" the Technology scaling com-delivered on Transaction on Nuclear Science (IEEE atomic energy science journal)
Parison of flip-flop heavy-ion single event upset cross sections " (trigger single-particle under heavy ion radiation environment
Upset cross section is affected by process reduction factor to be compared) (phase December the 6th in 2013 volume 60, the 4368-4373 page) refer to
Go out DICE trigger drastically to decline relative to the consolidation effect of d type flip flop, DICE trigger and the single-particle inversion of d type flip flop
Cross section becomes and differs only by 1.2～5 times by originally differing 1～2 order of magnitude.Under nanometer CMOS process, extensively adopted at present
Flip-flop design scheme also have the d type flip flop that triplication redundancy reinforces, if Y.He et al. is at Science China Information
" the Comparison ofheavy-ion induced SEU for D-and delivered on Sciences (Chinese science information science)
TMR-flip-flop designs in 65nm bulk CMOS technology " (under 65 nanometer CMOS process d type flip flop and
The heavy ion single-particle inversion of triplication redundancy design compares) (phase October the 10th in 2014 volume 57, the 102405:1-7 page)
Point out that triplication redundancy technology is highly effective to suppression single-particle inversion, however triplication redundancy under 65 nanometer technologies, upset cross section is the most only
Only reduce about an order of magnitude, and the election circuit itself that triplication redundancy technology introduces also is that single-particle is sensitive.
Process tapers in 65nm and following technique thereof, and in integrated circuit, electric charge shares the single-particle multinode electric charge receipts of induction
Collection has become as a kind of universal phenomenon.On the one hand, current reinforcing d type flip flop is increasingly difficult to avoid that single-particle multinode electric charge
Collect the single-particle inversion brought, so that primary particle inversion resistant demand under radiation environment can not be met；On the other hand, pass
Although the d type flip flop triplication redundancy reinforcement technique of system can suppress single-particle inversion well, but needed for triplication redundancy cannot being avoided
The election single-particle inversion that brought of circuit and need the area overhead of more than 4 times (containing area of election circuit).How to subtract
Reinforce the SEU cross section of d type flip flop less, and then lifting d type flip flop anti-single particle upset ability is those skilled in the art
The technical problem extremely paid close attention to.
Summary of the invention
The technical problem to be solved in the present invention is: can not meet anti-single particle upset under radiation environment for existing reinforcing d type flip flop
Demand, traditional d type flip flop triplication redundancy reinforcement technique cannot avoid electing the single-particle inversion that brought of circuit and area to open
Selling big problem, it is provided that a kind of primary particle inversion resistant d type flip flop, anti-single particle upset ability is higher, and effectively reduces by three moulds
The area overhead of redundancy reinforcement technique, eliminates the single-particle sensitive question that election circuit brings.
The technical scheme is that in the present invention, d type flip flop is in series by principal and subordinate's two stage latch (Latch), Zhu Congsuo
The structure of storage is identical, but this Latch is incomplete same with the Latch in common d type flip flop, and wherein Latch's is interior
Core is no longer end to end two phase inverters, but as shown in Figure 4, by 6 PMOS transistor P1～P6 and 6 NMOS
Transistor N1～N6 is constituted.As shown in Figure 4, the drain electrode of N1 is connected with drain electrode, node M N1 of P1, and is connected to P2
With on the grid of N4, the grid of N1 is connected with the drain electrode of N2；The drain electrode of N2 is connected with drain electrode, the node M 1 of P2, and
Being connected on the grid of P3 Yu N1, the grid of N2 is connected with the drain electrode of N5；Drain electrode and the drain electrode of P3, node M N2 of N3
Being connected, and be connected on the grid of P4 and N6, the grid of N3 is connected with the drain electrode of N4；The drain electrode of N4 and the drain electrode of P4,
Node M 2 is connected, and is connected on the grid of P5 and N3, and the grid of N4 is connected with the drain electrode of N1；The drain electrode of N5 and P5
Drain electrode, node M N3 be connected, and be connected on the grid of P6 Yu N2, the grid of N5 is connected with the drain electrode of N6；N6
Drain electrode be connected with drain electrode, the node M 3 of P6, and be connected on the grid of P1 and N5, the grid of N6 and the drain electrode of N3
It is connected.The grid of P1 is connected with the drain electrode of N6, and the drain electrode of P1 is connected with the drain electrode of N1；The drain electrode phase of the grid of P2 and N1
Even, the drain electrode of P2 is connected with the drain electrode of N2；The grid of P3 is connected with the drain electrode of N2, and the drain electrode of P3 is connected with the drain electrode of N3；
The grid of P4 is connected with the drain electrode of N3, and the drain electrode of P4 is connected with the drain electrode of N4；The grid of P5 is connected with the drain electrode of N4, P5
Drain electrode be connected with the drain electrode of N5；The grid of P6 is connected with the drain electrode of N5, and the drain electrode of P6 is connected with the drain electrode of N6.6
The source electrode of PMOS transistor P1～P6 all meets power vd D；The source grounding VSS of 6 nmos pass transistor N1～N6.
On the basis of kernel shown in Fig. 4, i.e. may make up the main Latch of the present invention by increasing the transistor etc. of band clock control
Or from Latch.In d type flip flop of the present invention, main Latch is still identical with from Latch.As it is shown in figure 5, the number of main Latch
According to input D by the input inverter of 3 band clock controls be connected respectively to node M N1 in Latch kernel, MN2 and
MN3, and at Latch core nodes M1, M2 and M3 only need to according to the phase inverter of band clock control in prior art like that (as
Series system shown in Fig. 3 (b)-(c), or transmission gate mode shown in Fig. 3 (d)) respectively increase one by the PMOS of clock control and
Nmos pass transistor, any one node in M1 or M2 or the M3 node of final main Latch is connected to from Latch
Data input D, and any one node from M1 or M2 or the M3 node of Latch is d type flip flop of the present invention
Data output Q.
Fig. 5-Fig. 7 is 3 kinds of main in d type flip flop of the present invention (or from) Latch and implements form.
Latch shown in Fig. 5 have employed implementation shown in Fig. 3 (b), PMOS transistor P2, P4 and P6 source electrode each via
One PMOS transistor controlled by clock signal (i.e. P7, P8 and P9) is connected to power vd D, and NMOS crystal
The source electrode of pipe N2, N4 and N6 is each via a nmos pass transistor controlled by clock signal (i.e. N7, N8 and N9)
It is connected to ground VSS.The data input D of Latch is connected respectively to by input inverter Inv1～Inv3 of three band clock controls
Node M N1, MN2 and MN3, and node M 3 is chosen as output signal Q.Two such Latch press the mode of Fig. 1
It is together in series and i.e. may make up the d type flip flop of the present invention, any one node in M1 or M2 or the M3 node of main Latch
It is connected to input D from the data of Latch, and in this example, is chosen as output signal Q from the node M 3 of Latch.
Latch shown in Fig. 6 have employed implementation shown in Fig. 3 (c), the drain electrode of PMOS transistor P2 and nmos pass transistor
PMOS transistor P10 controlled by clock signal and one it has been sequentially inserted into by clock signal control between the drain electrode of N2
Nmos pass transistor N10, be sequentially inserted between drain electrode and the drain electrode of nmos pass transistor N4 of PMOS transistor P4
One PMOS transistor P11 controlled by clock signal and a nmos pass transistor N11, PMOS controlled by clock signal
It has been sequentially inserted into a PMOS controlled by clock signal between drain electrode and the drain electrode of nmos pass transistor N6 of transistor P6
A transistor P12 and nmos pass transistor N12 controlled by clock signal.Equally, the data input D of Latch is by three
Input inverter Inv1～Inv3 of individual band clock control is connected respectively to node M N1, MN2 and MN3, and node M 3 quilt
Elect output signal Q as.Two such Latch are together in series by the mode of Fig. 1 and i.e. may make up the d type flip flop of the present invention, main
Any one node in M1 or M2 or the M3 node of Latch is connected to input D from the data of Latch, and in this example,
It is chosen as output signal Q from the node M 3 of Latch.
Latch shown in Fig. 7 have employed the transmission gate mode shown in Fig. 3 (d), is i.e. realized by transmission gate TG1, TG2 and TG3
The clock signal control to data path.PMOS transistor P13 and NMOS tube N13 constitute transmission gate TG1, PMOS
Transistor P14 and NMOS tube N14 constitute transmission gate TG2, PMOS transistor P15 and NMOS tube N15 and constitute transmission
Door TG3.One end of transmission gate TG1 is connected to M1 node, and the other end is connected to nmos pass transistor N1 and PMOS crystal
The grid of pipe P3；One end of transmission gate TG2 is connected to M2 node, and the other end is connected to nmos pass transistor N3 and PMOS
The grid of transistor P5；One end of transmission gate TG3 is connected to M3 node, the other end be connected to nmos pass transistor N5 and
The grid of PMOS transistor P1.Similarly, the data input D of the Latch input inverter by three band clock controls
Inv1～Inv3 is connected respectively to node M N1, MN2 and MN3, and node M 3 is chosen as output signal Q.Two such
Latch is together in series by the mode of Fig. 1 and i.e. may make up the d type flip flop of the present invention, M1 or M2 or the M3 node of main Latch
In any one node be connected to input D from the data of Latch, and in this example, be chosen as defeated from the node M 3 of Latch
Go out signal Q.
The primary particle inversion resistant course of work of the present invention is:
When Latch main during the high energy particle in space or ray bombard d type flip flop of the present invention or the somewhere from Latch, as
PMOS transistor P2 in Fig. 4 and P3, P3 is upper can produce single-ion transient state, and node M N2 can produce the full pendulum of 0 → 1
Width voltage jump, opens nmos pass transistor N6, so that the voltage in node M 3 becomes an intermediate level value；With
This simultaneously, PMOS transistor P2 is made by particle bombardment the voltage in node M 1 be strengthened, and maintains high level state,
It acts on N1 transistor so that node M N1 is not affected by N6 transistor driving P1 and remains logic low,
Thus the storage organization of this Latch will not occur numerical value to overturn.Certainly, from the perspective of circuit, with kernel structure shown in Fig. 4
Become Latch and non-fully will not produce single-particle inversion, such as transistor to (P1, P3) simultaneously by particle bombardment time, save
Point MN1 and MN2 can produce the full amplitude of oscillation voltage jump of 0 → 1；So that produce the full amplitude of oscillation of 1 → 0 in node M 2
Voltage jump, node M 3 produces half amplitude of oscillation voltage jump of 1 → 1/2；At this moment MN3 node is driven higher by P5, MN3
Slowly there is the full amplitude of oscillation saltus step of 0 → 1 in node, and drives the full amplitude of oscillation saltus step of generation 1 → 0 on M3；There is number in final Lacth
Value upset.In the Latch that kernel shown in Fig. 4 is constituted, for storage 0 and 1 two kinds of data patterns of storage, particle bombards simultaneously
The transistor of upset can be caused 9 right to having, and these transistors to all only under storage 1 this data pattern sensitive；But
Transistor is nearest to (P1, P3) and (P3, P5) spacing distance in domain realizes, and realizes all by minimum layout design rules
1.79 μm are reached；Thus these transistors to be actually difficult to simultaneously by the Latch in particle bombardment, the i.e. present invention and
The d type flip flop of the present invention has the highest anti-single particle upset ability.
Use the present invention can reach techniques below effect:
1, it is made up of 6 PMOS transistor and 6 nmos pass transistors due to the kernel of Latch each in the present invention,
This has not only saved the area overhead of an election circuit compared with traditional triplication redundancy technology, also eliminates election circuit and brings
Single-particle sensitive question；
2, in the present invention, in d type flip flop, the numerical value of storage has significant impact to the single-particle sensitiveness of this unit.For storage 0 this
Planting data pattern, in d type flip flop, any two transistor is bombarded by particle all without occurring numerical value to overturn simultaneously, and this makes this
D type flip flop in invention single-particle sensitiveness when storing numerical value 0 is lower, anti-single particle upset ability is higher.Owing to reality should
In with, a lot of triggers need to keep same numerical value for a long time, thus the anti-single particle that the present invention is to improving this kind of trigger further
Upset ability is significant.
Accompanying drawing explanation
Fig. 1 is the building-block of logic of the d type flip flop using principal and subordinate's two-stage Latch structure；
Fig. 2 is principal and subordinate's two-stage Latch and the building-block of logic of Latch kernel in common d type flip flop in background technology；
Fig. 3 (a) is the logical construction of the 3rd phase inverter in common d type flip flop in background technology, and Fig. 3 (b)-(d) is band clock control
The logical construction of 3 kinds of ways of realization of input inverter or feedback inverter；
Fig. 4 is the building-block of logic of Latch kernel in the present invention；
Fig. 5 is the Latch core logic structure chart using mode shown in Fig. 3 (b) to realize in the present invention；
Fig. 6 is the Latch core logic structure chart using mode shown in Fig. 3 (c) to realize in the present invention；
Fig. 7 is the Latch core logic structure chart using mode shown in Fig. 3 (d) to realize in the present invention.
Detailed description of the invention
Fig. 1 is the building-block of logic of the d type flip flop using principal and subordinate's two-stage Latch structure.
Common d type flip flop and d type flip flop of the present invention by main latch (Latch) and form from Latch tandem, main Latch
Identical with the structure from Latch.
Fig. 2 is principal and subordinate's two-stage Latch and the building-block of logic of Latch kernel in common d type flip flop in background technology.
The main Latch of common d type flip flop or from Latch by the input inverter of 1 band clock control, 1 band clock control
Feedback inverter and phase inverter constitute.And the kernel of Latch is made up of two end to end phase inverters.
Fig. 3 (a) is the 3rd phase inverter, and it is made up of 1 PMOS transistor and 1 nmos pass transistor, and wherein PMOS is brilliant
Body pipe is connected with the drain electrode of nmos pass transistor and constitutes the output of phase inverter, and PMOS transistor and nmos pass transistor
Grid is connected and constitutes the input of phase inverter；The source electrode of PMOS transistor is connected on power supply, and the source electrode of nmos pass transistor
It is connected on the ground.Fig. 3 (b)-(d) is input inverter or 3 kinds of ways of realization of feedback inverter of band clock control.Make a general survey of this 3
Planting way of realization, they are all (by PMOS transistor P1 and nmos pass transistor N1 at the 3rd phase inverter shown in Fig. 3 (a)
Constitute) on the basis of add PMOS transistor P2 of a clock control and the nmos pass transistor N2 of a clock control；
And its transistor increased or be connected in series as shown in Fig. 3 (b)-(c), or with the shape of transmission gate as shown in Fig. 3 (d)
Formula is connected to the output of phase inverter.Clock when it should be noted that clock signal and band in the input inverter of band clock control
In the feedback inverter of system, clock signal phase difference is 180 degree.It is to say, as PMOS in the input inverter of band clock control
When the grid of transistor P2 is connected to certain external signal CLK, PMOS transistor P in the feedback inverter of band clock control2
Grid be connected to by CLK signal through one phase inverter produce CLK non-signalOn.
Fig. 4 is the kernel of Latch in the present invention.
It no longer has two end to end phase inverters to constitute as the kernel (shown in Fig. 2) of Latch in common d type flip flop,
But be made up of 6 PMOS transistor P1～P6 and 6 nmos pass transistor N1～N6.The drain electrode of N1 and the leakage of P1
Pole, node M N1 are connected, and are connected on the grid of P2 and N4, and the grid of N1 is connected with the drain electrode of N2；The drain electrode of N2
Drain electrode, node M 1 with P2 are connected, and are connected on the grid of P3 Yu N1, and the grid of N2 is connected with the drain electrode of N5；
The drain electrode of N3 is connected with drain electrode, node M N2 of P3, and is connected on the grid of P4 and N6, and the grid of N3 is with N4's
Drain electrode is connected；The drain electrode of N4 is connected with drain electrode, the node M 2 of P4, and is connected on the grid of P5 and N3, the grid of N4
Pole is connected with the drain electrode of N1；The drain electrode of N5 is connected with drain electrode, node M N3 of P5, and is connected on the grid of P6 Yu N2,
The grid of N5 is connected with the drain electrode of N6；The drain electrode of N6 is connected with drain electrode, the node M 3 of P6, and is connected to P1's and N5
On grid, the grid of N6 is connected with the drain electrode of N3.The grid of P1 is connected with the drain electrode of N6, the drain electrode of P1 and the drain electrode of N1
It is connected；The grid of P2 is connected with the drain electrode of N1, and the drain electrode of P2 is connected with the drain electrode of N2；The drain electrode phase of the grid of P3 and N2
Even, the drain electrode of P3 is connected with the drain electrode of N3；The grid of P4 is connected with the drain electrode of N3, and the drain electrode of P4 is connected with the drain electrode of N4；
The grid of P5 is connected with the drain electrode of N4, and the drain electrode of P5 is connected with the drain electrode of N5；The grid of P6 is connected with the drain electrode of N5, P6
Drain electrode be connected with the drain electrode of N6.The source electrode of 6 PMOS transistor P1～P6 all meets power vd D；6 NMOS crystal
The source grounding VSS of pipe N1～N6.
Fig. 5-Fig. 7 is 3 kinds of main in d type flip flop of the present invention (or from) Latch and implements form.
Latch shown in Fig. 5 have employed implementation shown in Fig. 3 (b), PMOS transistor P2, P4 and P6 source electrode each via
One PMOS transistor controlled by clock signal (i.e. P7, P8 and P9) is connected to power vd D, and NMOS crystal
The source electrode of pipe N2, N4 and N6 is each via a nmos pass transistor controlled by clock signal (i.e. N7, N8 and N9)
It is connected to ground VSS.The data input D of Latch is connected respectively to by input inverter Inv1～Inv3 of three band clock controls
Node M N1, MN2 and MN3, and node M 3 is chosen as output signal Q.Two such Latch press the mode of Fig. 1
It is together in series and i.e. may make up the d type flip flop of the present invention, any one node in M1 or M2 or the M3 node of main Latch
It is connected to input D from the data of Latch, and in this example, is chosen as output signal Q from the node M 3 of Latch.
Latch shown in Fig. 6 have employed implementation shown in Fig. 3 (c), the drain electrode of PMOS transistor P2 and nmos pass transistor
PMOS transistor P10 controlled by clock signal and one it has been sequentially inserted into by clock signal control between the drain electrode of N2
Nmos pass transistor N10, be sequentially inserted between drain electrode and the drain electrode of nmos pass transistor N4 of PMOS transistor P4
One PMOS transistor P11 controlled by clock signal and a nmos pass transistor N11, PMOS controlled by clock signal
It has been sequentially inserted into a PMOS controlled by clock signal between drain electrode and the drain electrode of nmos pass transistor N6 of transistor P6
A transistor P12 and nmos pass transistor N12 controlled by clock signal.Equally, the data input D of Latch is by three
Input inverter Inv1～Inv3 of individual band clock control is connected respectively to node M N1, MN2 and MN3, and node M 3 quilt
Elect output signal Q as.Two such Latch are together in series by the mode of Fig. 1 and i.e. may make up the d type flip flop of the present invention, main
Any one node in M1 or M2 or the M3 node of Latch is connected to input D from the data of Latch, and in this example,
It is chosen as output signal Q from the node M 3 of Latch.
Latch shown in Fig. 7 have employed the transmission gate mode shown in Fig. 3 (d), is i.e. realized by transmission gate TG1, TG2 and TG3
The clock signal control to data path.PMOS transistor P13 and NMOS tube N13 constitute transmission gate TG1, PMOS
Transistor P14 and NMOS tube N14 constitute transmission gate TG2, PMOS transistor P15 and NMOS tube N15 and constitute transmission
Door TG3.One end of transmission gate TG1 is connected to M1 node, and the other end is connected to nmos pass transistor N1 and PMOS crystal
The grid of pipe P3；One end of transmission gate TG2 is connected to M2 node, and the other end is connected to nmos pass transistor N3 and PMOS
The grid of transistor P5；One end of transmission gate TG3 is connected to M3 node, the other end be connected to nmos pass transistor N5 and
The grid of PMOS transistor P1.Similarly, the data input D of the Latch input inverter by three band clock controls
Inv1～Inv3 is connected respectively to node M N1, MN2 and MN3, and node M 3 is chosen as output signal Q.Two such
Latch is together in series by the mode of Fig. 1 and i.e. may make up the d type flip flop of the present invention, M1 or M2 or the M3 node of main Latch
In any one node be connected to input D from the data of Latch, and in this example, be chosen as defeated from the node M 3 of Latch
Go out signal Q.
Claims (4)
1. a primary particle inversion resistant d type flip flop, is in series by principal and subordinate's two stage latch Latch, be designated as main Latch and
From Latch, the structure of master-slave latch is identical, it is characterised in that the Latch kernel of principal and subordinate's two stage latch is by 6
PMOS transistor P1～P6 and 6 nmos pass transistor N1～N6 are constituted；Drain electrode and the drain electrode of P1, node M N1 of N1
Being connected, and be connected on the grid of P2 and N4, the grid of N1 is connected with the drain electrode of N2；The drain electrode of N2 and the drain electrode of P2,
Node M 1 is connected, and is connected on the grid of P3 Yu N1, and the grid of N2 is connected with the drain electrode of N5；The drain electrode of N3 and P3
Drain electrode, node M N2 be connected, and be connected on the grid of P4 and N6, the grid of N3 is connected with the drain electrode of N4；N4
Drain electrode be connected with drain electrode, the node M 2 of P4, and be connected on the grid of P5 and N3, the grid of N4 and the drain electrode of N1
It is connected；The drain electrode of N5 is connected with drain electrode, node M N3 of P5, and is connected on the grid of P6 Yu N2, the grid of N5 with
The drain electrode of N6 is connected；The drain electrode of N6 is connected with drain electrode, the node M 3 of P6, and is connected on the grid of P1 and N5, N6
Grid be connected with the drain electrode of N3；The grid of P1 is connected with the drain electrode of N6, and the drain electrode of P1 is connected with the drain electrode of N1；P2's
Grid is connected with the drain electrode of N1, and the drain electrode of P2 is connected with the drain electrode of N2；The grid of P3 is connected with the drain electrode of N2, the leakage of P3
Pole is connected with the drain electrode of N3；The grid of P4 is connected with the drain electrode of N3, and the drain electrode of P4 is connected with the drain electrode of N4；The grid of P5
Being connected with the drain electrode of N4, the drain electrode of P5 is connected with the drain electrode of N5；The grid of P6 is connected with the drain electrode of N5, the drain electrode of P6 with
The drain electrode of N6 is connected；The source electrode of 6 PMOS transistor P1～P6 all meets power vd D；6 nmos pass transistor N1～N6
Source grounding VSS；
Main Latch or input D from the data of Latch and be connected respectively in Latch by the input inverter of 3 band clock controls
Node M N1 in core, MN2 and MN3, and according in prior art during band at Latch core nodes M1, M2 and M3
The phase inverter of clock respectively increases one by the PMOS of clock control and nmos pass transistor, the M1 of final main Latch
Or any one node in M2 or M3 node is connected to input D from the data of Latch, and from M1 or M2 of Latch
Or any one node in M3 node is the data output Q of d type flip flop of the present invention.
Primary particle inversion resistant d type flip flop the most as claimed in claim 1, it is characterised in that described Latch core nodes
One is respectively increased by PMOS transistor P7 of clock control, P8 and P9, and nmos pass transistor at M1, M2 and M3
N7, N8 and N9；PMOS transistor P2, P4 and P6 source electrode brilliant each via the PMOS that controlled by clock signal
Body pipe i.e. P7, P8 and P9, is connected to power vd D, and the source electrode of nmos pass transistor N2, N4 and N6 is each via one
The individual nmos pass transistor controlled by clock signal i.e. N7, N8 and N9, be connected to ground VSS；The data input D of Latch leads to
Input inverter Inv1～Inv3 crossing three band clock controls is connected respectively to node M N1, MN2 and MN3.
Primary particle inversion resistant d type flip flop the most as claimed in claim 1, it is characterised in that described Latch core nodes
Respectively increase at M1, M2 and M3 one by PMOS transistor P10 of clock control, P11 and P12, and NMOS crystal
Pipe N10, N11 and N12；It has been sequentially inserted into one between drain electrode and the drain electrode of nmos pass transistor N2 of PMOS transistor P2
Individual PMOS transistor P10 controlled by clock signal and a nmos pass transistor N10, PMOS controlled by clock signal
It has been sequentially inserted into a PMOS controlled by clock signal between drain electrode and the drain electrode of nmos pass transistor N4 of transistor P4
Transistor P11 and a nmos pass transistor N11 controlled by clock signal, the drain electrode of PMOS transistor P6 and NMOS
Be sequentially inserted into PMOS transistor P12 controlled by clock signal between the drain electrode of transistor N6 and one believed by clock
The data input D of number the nmos pass transistor N12, Latch that control is by the input inverter of three band clock controls
Inv1～Inv3 is connected respectively to node M N1, MN2 and MN3.
Primary particle inversion resistant d type flip flop the most as claimed in claim 1, it is characterised in that described Latch core nodes
Respectively increase at M1, M2 and M3 one by PMOS transistor P13 of clock control, P14 and P15, and NMOS crystal
Pipe N13, N14 and N15；PMOS transistor P13 and NMOS tube N13 constitute transmission gate TG1, PMOS transistor
P14 and NMOS tube N14 constitute transmission gate TG2, PMOS transistor P15 and NMOS tube N15 and constitute transmission gate TG3；
One end of transmission gate TG1 is connected to M1 node, and the other end is connected to nmos pass transistor N1 and PMOS transistor P3
Grid；One end of transmission gate TG2 is connected to M2 node, and the other end is connected to nmos pass transistor N3 and PMOS transistor
The grid of P5；One end of transmission gate TG3 is connected to M3 node, and the other end is connected to nmos pass transistor N5 and PMOS
The grid of transistor P1；Similarly, the data input D of Latch input inverter Inv1～Inv3 by three band clock controls
It is connected respectively to node M N1, MN2 and MN3.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788341A (en) * | 2017-01-12 | 2017-05-31 | 深圳大学 | A kind of primary particle inversion resistant asynchronous reset d type flip flop |
| CN106788380A (en) * | 2017-01-12 | 2017-05-31 | 深圳大学 | A kind of primary particle inversion resistant asynchronous set d type flip flop |
| CN108199698A (en) * | 2017-12-13 | 2018-06-22 | 北京时代民芯科技有限公司 | A kind of doubleclocking anti-single particle latch |
| CN110138377A (en) * | 2019-06-03 | 2019-08-16 | 上海华力微电子有限公司 | Latch |
| CN110311655A (en) * | 2019-06-27 | 2019-10-08 | 北京嘉楠捷思信息技术有限公司 | Hold-free dynamic D trigger, data processing unit, chip, force calculation board and computing equipment |
| CN110838834A (en) * | 2019-11-11 | 2020-02-25 | 西安电子科技大学 | Reinforced improved QUATRO D trigger of anti single event upset |
| CN111241770A (en) * | 2020-01-08 | 2020-06-05 | 中国人民武装警察部队海警学院 | Low-power consumption SET suppression circuit for trigger under radiation environment |
| CN111223503B (en) * | 2020-03-11 | 2021-10-01 | 河海大学常州校区 | Double-node single-particle upset immune memory cell and latch |
| WO2024060469A1 (en) * | 2022-09-19 | 2024-03-28 | 长鑫存储技术有限公司 | Flip-flop circuit and electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040027184A1 (en) * | 2002-08-06 | 2004-02-12 | Mitsubishi Denki Kabushiki Kaisha | Master slave flip-flop circuit functioning as edge trigger flip-flop |
| CN103021456A (en) * | 2012-12-19 | 2013-04-03 | 电子科技大学 | Non-volatile highly-resistant-single-particle configuration memory unit |
| CN103903645A (en) * | 2012-12-28 | 2014-07-02 | 中国科学院微电子研究所 | Static random storage unit employing radiation hardening design |
-
2016
- 2016-03-31 CN CN201610196541.5A patent/CN105897223B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040027184A1 (en) * | 2002-08-06 | 2004-02-12 | Mitsubishi Denki Kabushiki Kaisha | Master slave flip-flop circuit functioning as edge trigger flip-flop |
| CN103021456A (en) * | 2012-12-19 | 2013-04-03 | 电子科技大学 | Non-volatile highly-resistant-single-particle configuration memory unit |
| CN103903645A (en) * | 2012-12-28 | 2014-07-02 | 中国科学院微电子研究所 | Static random storage unit employing radiation hardening design |
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|---|---|---|---|---|
| CN106788380B (en) * | 2017-01-12 | 2020-03-24 | 深圳大学 | Asynchronous set D trigger resistant to single event upset |
| CN106788380A (en) * | 2017-01-12 | 2017-05-31 | 深圳大学 | A kind of primary particle inversion resistant asynchronous set d type flip flop |
| CN106788341A (en) * | 2017-01-12 | 2017-05-31 | 深圳大学 | A kind of primary particle inversion resistant asynchronous reset d type flip flop |
| CN106788341B (en) * | 2017-01-12 | 2020-07-10 | 深圳大学 | Asynchronous reset D trigger resisting single event upset |
| CN108199698A (en) * | 2017-12-13 | 2018-06-22 | 北京时代民芯科技有限公司 | A kind of doubleclocking anti-single particle latch |
| CN110138377A (en) * | 2019-06-03 | 2019-08-16 | 上海华力微电子有限公司 | Latch |
| CN110138377B (en) * | 2019-06-03 | 2023-06-13 | 上海华力微电子有限公司 | Latch device |
| CN110311655A (en) * | 2019-06-27 | 2019-10-08 | 北京嘉楠捷思信息技术有限公司 | Hold-free dynamic D trigger, data processing unit, chip, force calculation board and computing equipment |
| CN110838834A (en) * | 2019-11-11 | 2020-02-25 | 西安电子科技大学 | Reinforced improved QUATRO D trigger of anti single event upset |
| CN111241770A (en) * | 2020-01-08 | 2020-06-05 | 中国人民武装警察部队海警学院 | Low-power consumption SET suppression circuit for trigger under radiation environment |
| CN111241770B (en) * | 2020-01-08 | 2023-11-24 | 中国人民武装警察部队海警学院 | Low-power-consumption SET suppression circuit for trigger under radiation environment |
| CN111223503B (en) * | 2020-03-11 | 2021-10-01 | 河海大学常州校区 | Double-node single-particle upset immune memory cell and latch |
| WO2024060469A1 (en) * | 2022-09-19 | 2024-03-28 | 长鑫存储技术有限公司 | Flip-flop circuit and electronic device |
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