CN111241770B - Low-power-consumption SET suppression circuit for trigger under radiation environment - Google Patents
Low-power-consumption SET suppression circuit for trigger under radiation environment Download PDFInfo
- Publication number
- CN111241770B CN111241770B CN202010016917.6A CN202010016917A CN111241770B CN 111241770 B CN111241770 B CN 111241770B CN 202010016917 A CN202010016917 A CN 202010016917A CN 111241770 B CN111241770 B CN 111241770B
- Authority
- CN
- China
- Prior art keywords
- input
- inverter
- input end
- pmos tube
- tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001629 suppression Effects 0.000 title claims abstract description 38
- 230000005855 radiation Effects 0.000 title abstract description 13
- 238000005070 sampling Methods 0.000 claims description 8
- 239000013256 coordination polymer Substances 0.000 claims description 6
- 230000000694 effects Effects 0.000 claims description 5
- 230000000630 rising effect Effects 0.000 claims description 4
- 230000003471 anti-radiation Effects 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract 2
- 150000004706 metal oxides Chemical class 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 239000002245 particle Substances 0.000 description 5
- 230000001052 transient effect Effects 0.000 description 4
- 230000005764 inhibitory process Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 241000282414 Homo sapiens Species 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Abstract
The invention discloses a SET (SET) suppression circuit for a radiation-resistant trigger, which comprises a two-input exclusive-OR gate, a two-input NOR gate, a single-input delay inverter, a double-input delay inverter and a three-input delay inverter, wherein the single-input delay inverter comprises a delay chain, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube, the double-input delay inverter comprises a first inverter, a third PMOS tube, a fourth PMOS tube, a third NMOS tube and a fourth NMOS tube, and the three-input delay inverter comprises a second inverter, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube; the integrated circuit has the advantages that the suppression is realized by adopting a simple circuit structure, the occupied area is small, the time sequence expenditure is small (only about 10 percent), and the power consumption, the area expenditure and the total output delay of the integrated circuit can be reduced.
Description
Technical Field
The present invention relates to a SET suppression circuit with low power consumption, and more particularly, to a SET suppression circuit for a radiation-resistant trigger.
Background
The existing space exploration and aerospace technology is an important support for national security, and is one of core technologies for promoting national technological development. However, the aerospace activity of human beings is not supported by an important scientific technology, namely the microelectronic technology. Microelectronics is a high-new electronics technology with large-scale integrated circuits as cores, and is one of the most important and basic scientific technologies in the information society at present.
Large scale integrated circuits used in the aerospace field are quite different from those used in other fields. The environment where the aerospace equipment works is filled with a large amount of radiation rays and high-energy particles, and when the high-energy particles are injected into a large-scale integrated circuit in the aerospace field, various electronic components in the large-scale integrated circuit are inevitably affected by the radiation of the high-energy particles, various failures are generated, the whole electronic components cannot work normally, even the electronic components are damaged, and the reliable operation of the aerospace equipment is seriously affected.
Single event upset (Single Event Upset, SEU) is the dominant failure mode of current large scale integrated circuits exposed to radiation effects. It is a soft error that manifests itself as a flip of the logic state of the circuit and a random change of the stored data without damage to the electronic components themselves, which is random, non-recurring and recoverable. The energy threshold required for soft errors is low and is continually decreasing with the continued reduction in the feature size of large scale integrated circuits. Particularly, under the 65nm process, the node capacitance of the storage node is smaller and smaller, the working voltage is lower and lower, and the stored charge is smaller and smaller, so that the SEU phenomenon is easier to occur in the large-scale integrated circuit.
One manifestation of SEU occurs in combinational logic circuits. When the high-energy particles collide with the combinational logic circuit, if charges generated by Single-Event Transient (SET) are collected by the internal nodes of the combinational logic circuit, an instantaneous SET pulse is formed at the output end, and the SET pulse propagates in the combinational logic circuit, and when the SET pulse propagates to the input end of the memory circuit and is captured by the memory circuit, the SET is directly converted into SEU. The data trigger is used as a storage circuit and mainly comprises a main latch and a slave latch, wherein the main latch and the slave latch are respectively provided with a data input end, an output end and a clock end, the output end of the main latch is connected with the data input end of the slave latch, the data input end of the main latch is used as the data input end of the trigger to be accessed and input, the output end of the slave latch is used as the output end of the trigger to output and output data, and the clock end of the main latch and the clock end of the slave latch are connected with each other to be used as the clock end of the trigger.
Currently, in order to solve this problem of flip-flop and improve the radiation resistance of integrated circuit chips, designers have proposed various reinforcement techniques. For example, in 2015, author C.Ramamurthy et al, journal "IEEE Trans.Nuclear Science" published "High Performance Low Power Pulse-Clocked TMR Circuits for Soft-Error Hardness," a TMR pulse latch was presented that latches SET via a pulse generating circuit and gives TMR to eliminate SEU. With the 90nm process, the latch is applied to an AES processor with 128-bit data and 256-bit keys, and the test results show that when the processor is impacted by particles, no state inversion occurs at all, i.e., SEU is eliminated. Although TMR pulse latches SEU inhibit well, the circuit structure is complex and the area is twice larger than standard static latches, resulting in a much larger integrated circuit area increase. Secondly, the largest defect of the triple-modular redundancy mechanism is very dependent on a voter, and once the voter has errors, the errors of the system are covered, thereby threatening the correct operation of the whole system and leading to failure of the fault-tolerant mechanism. Meanwhile, an author R.Naseer published "DF-DICE: A scalable solution for soft error tolerant circuit design" in a meeting "Proc.Int.Symp.circuits and Systems" proposes a method for reducing the influence of SET on a storage circuit by adopting a delay unit so as to reduce the probability of SEU generation; although the scheme has simple circuit structure and small area, the SEU inhibition effect is poor, the time sequence cost is large, and the time sequence cost accounts for about 30% of the whole time sequence cost, so that the total output delay of the integrated circuit is increased more. Author q.zhou, published in conference "proc.13th European Test Conf" as "Tunable transient filters for soft error rate reduction in combinational circuits", proposes a method of eliminating SET glitches using a transient filtering unit, thereby preventing SEU generation; author J.Teifel, journal "IEEE Trans. Nuclear Science" published "Self-acting dual-module-redundancy circuits for single event transient mitigation," also proposes a method of using voters to suppress SEU caused by SET. Although the SEU suppression effect of the scheme is good, the circuit structure is complex, and the area of the integrated circuit is increased more.
Disclosure of Invention
The invention aims to solve the technical problem of providing the SET suppression circuit aiming at the anti-radiation trigger, which has the advantages of simple structure, small occupied area, small time sequence expenditure and capability of reducing the power consumption, the area expenditure and the total output delay of an integrated circuit.
The technical scheme adopted for solving the technical problems is as follows: the SET suppression circuit for the radiation-resistant trigger comprises a two-input exclusive-OR gate, a two-input NOR gate, a single-input delay inverter, a double-input delay inverter and a three-input delay inverter, wherein the two-input exclusive-OR gate is provided with a first input end, a second input end and an output end, the two-input NOR gate is provided with the first input end, the second input end and the output end, the single-input delay inverter is provided with the input end and the output end, the double-input delay inverter is provided with the first input end, the second input end and the output end, and the three-input delay inverter is provided with the first input end, the second input end, the third input end and the output end. The first input end of the two-input exclusive-OR gate is the first input end of the SET suppression circuit, the second input end of the two-input exclusive-OR gate, the input end of the single-input delay inverter and the second input end of the two-input nor gate are connected, the output end of the two-input exclusive-OR gate is connected with the first input end of the three-input delay inverter, the second input end of the three-input delay inverter is the third input end of the SET suppression circuit, the third input end of the three-input delay inverter, the output end of the two-input nor gate and the second input end of the two-input delay inverter are connected, the output end of the three-input delay inverter is the output end of the SET suppression circuit, and the output end of the single-input delay inverter is connected with the first input end of the two-input exclusive-OR gate; the single-input delay inverter comprises a delay chain, a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, wherein the delay chain comprises 2k+1 inverters, k is an integer greater than or equal to 0, when k=0, the input end of the 1 st inverter is the input end of the delay chain, the output end of the 1 st inverter is the output end of the delay chain, when k > 0, the input end of the 1 st inverter is the input end of the delay chain, the output end of the j-th inverter is connected with the input end of the j+1th inverter, j=1, 2, …,2k, and the output end of the 2k+1th inverter is the output end of the delay chain; the input end of the delay chain, the grid electrode of the first PMOS tube and the grid electrode of the second NMOS tube are connected, the connection end of the delay chain is the input end of the single-input delay inverter, the output end of the delay chain, the grid electrode of the second PMOS tube and the grid electrode of the first NMOS tube are connected, the source electrode of the first PMOS tube is connected with a power supply, the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube, the connection end of the second PMOS tube is the output end of the single-input delay inverter, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded; the double-input delay inverter comprises a first inverter, a third PMOS tube, a fourth PMOS tube, a third NMOS tube and a fourth NMOS tube, wherein the first inverter is provided with an input end and an output end, the input end of the first inverter is connected with the grid electrode of the third NMOS tube, the connection end of the first inverter is the first input end of the double-input delay inverter, the output end of the first inverter is connected with the grid electrode of the fourth PMOS tube, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth NMOS tube, the connection end of the third NMOS tube is the second input end of the double-input delay inverter, the source electrode of the third PMOS tube is connected with a power supply, the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube, the source electrode of the fourth PMOS tube is connected with the drain electrode of the third NMOS tube, the connection end of the third NMOS tube is the output end of the double-input delay inverter, and the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube; the third input delay inverter comprises a second inverter, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube, wherein the second inverter is provided with an input end and an output end, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the seventh NMOS tube, the connection end of the grid electrode of the fifth PMOS tube is the third input end of the third input delay inverter, the source electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube, the grid electrode of the sixth PMOS tube is connected with the grid electrode of the sixth NMOS tube, the connection end of the grid electrode of the sixth PMOS tube is the first input end of the third input delay inverter, the drain electrode of the fifth PMOS tube, the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube, the grid electrode of the seventh PMOS tube is connected with the output end of the seventh NMOS tube, and the drain electrode of the seventh NMOS tube is connected with the drain electrode of the seventh NMOS tube; a first input end of the SET suppression circuit is connected with a storage node N1 in a main latch of the trigger, a second input end of the SET suppression circuit is connected with a data input end of the trigger, a third input end of the SET suppression circuit is connected with a clock signal CLK, and an output end of the SET suppression circuit is connected with a clock end of the trigger; when the global clock CLK jumps from '1' to '0', the trigger enters a transparent state, when the global clock CLK jumps from '0' to '1', the trigger enters a sampling state, at this time, the trigger performs data sampling only when the input data accessed by the data input end of the trigger is different from the data stored by the trigger, when the data of the trigger storage node N1 is '0', the data input end of the trigger generates a positive SET pulse, CLK is low, the trigger is in the transparent state, at this time, due to the delay effect of the single-input delay inverter, a negative short pulse is generated after the NOR gate, thus a positive short pulse CP is generated at the output end of the three-input delay inverter, the transparent state of the trigger is turned off, the SEU error generated by the SET is prevented from being sampled when the clock rising edge arrives, and the SEU error generated by the SET is restrained.
Compared with the prior art, the invention has the advantages that the SET inhibition circuit single-input delay inverter for the anti-radiation trigger comprises a delay chain, a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, wherein the delay chain comprises 2k+1 inverters, k is an integer greater than or equal to 0, when k=0, the input end of the first inverter is the input end of the delay chain, the output end of the first inverter is the output end of the delay chain, when k > 0, the input end of the first inverter is the input end of the delay chain, the output end of the j inverter is connected with the input end of the j+1 inverter, j=1, 2, …,2k, the output end of the 2k+1 inverter is the output end of the delay chain, the double-input delay inverter comprises the first inverter, the NMOS, the third PMOS tube, the fourth PMOS tube, the third NMOS tube is connected with the output end of the second NMOS tube, the second inverter is connected with the input end of the first trigger, the second trigger is connected with the output end of the second trigger, the first trigger is connected with the output end of the first trigger, and the second trigger is connected with the output end of the second trigger; when the global clock CLK jumps from '1' to '0', the trigger enters a transparent state, when the global clock CLK jumps from '0' to '1', the trigger enters a sampling state, at this time, the trigger performs data sampling only when the input data accessed by the data input end of the trigger is different from the data stored by the trigger, when the data of the trigger storage node N1 is '0', the data input end of the trigger generates a positive SET pulse, and CLK is low, the trigger is in the transparent state, at this time, due to the delay effect of the single-input delay inverter, a negative short pulse is generated after the NOR gate, thus a positive short pulse CP is generated at the output end of the three-input delay inverter, the transparent state of the trigger is turned off, the SEU error generated by the SET is prevented from being sampled when the clock rising edge arrives, therefore, the SEU error generated by the SEU is inhibited.
Drawings
FIG. 1 is a circuit diagram of a low power SET suppression circuit for flip-flops in a radiating environment according to the present invention;
FIG. 2 is a circuit diagram of a single input delay inverter in a low power SET suppression circuit for flip-flops in a radiating environment according to the present invention;
FIG. 3 is a circuit diagram of a dual input delay inverter in a low power SET suppression circuit for flip-flops in a radiating environment according to the present invention;
FIG. 4 is a circuit diagram of a three-input delay inverter in a low power SET suppression circuit for flip-flops in a radiating environment according to the present invention;
FIG. 5 is a schematic diagram of a low power SET suppression circuit for flip-flops in a radiating environment of the present invention when used in conjunction with a flip-flop;
FIG. 6 (a) is a diagram of the CLK waveform of the low power SET suppression circuit for flip-flop in radiation environment of the present invention when the flip-flop is SET;
fig. 6 (b) is a schematic waveform diagram of an input signal to which a low power consumption SET suppression circuit for a trigger in a radiation environment of the present invention is connected when the trigger generates a SET;
FIG. 6 (c) is a schematic diagram showing waveforms of the output signal NDR of the NOR gate output terminal of the low power consumption SET suppression circuit for flip-flop in radiation environment according to the present invention when the flip-flop generates SET;
fig. 6 (d) is a schematic waveform diagram of the output signal CP of the three-input delay inverter output of the low power consumption SET suppression circuit for flip-flop in radiation environment according to the present invention when the flip-flop generates SET.
Detailed Description
The invention is described in further detail below with reference to the embodiments of the drawings.
Examples: as shown in fig. 1, a SET suppression circuit for a radiation-resistant flip-flop includes a two-input exclusive-or gate XOR, a two-input NOR gate NOR, a single-input delay inverter C1, a two-input delay inverter C2, and a three-input delay inverter C3, the two-input exclusive-or gate XOR having a first input terminal, a second input terminal, and an output terminal, the two-input NOR gate NOR having a first input terminal, a second input terminal, and an output terminal, the single-input delay inverter C1 having an input terminal and an output terminal, the two-input delay inverter C2 having a first input terminal, a second input terminal, and an output terminal, the three-input delay inverter C3 having a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input end of the two-input exclusive-OR gate XOR is the first input end of a SET suppression circuit, the second input end of the two-input exclusive-OR gate XOR, the input end of the single-input delay inverter C1 and the second input end of the two-input NOR gate NOR are connected, the output end of the two-input exclusive-OR gate XOR is connected with the first input end of the three-input delay inverter C3, the second input end of the three-input delay inverter C3 is the third input end of the SET suppression circuit, the third input end of the three-input delay inverter C3, the output end of the two-input NOR gate NOR and the second input end of the double-input delay inverter C2 are connected, the output end of the double-input delay inverter C2 is the output end of the SET suppression circuit, and the output end of the single-input delay inverter C1 and the first input end of the two-input exclusive-OR gate XOR are connected;
as shown in fig. 2, the single-input delay inverter C1 includes a delay chain, a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube N1 and a second NMOS tube N2, where the delay chain includes 2k+1 inverters, k is an integer greater than or equal to 0, when k=0, the input end of the 1 st inverter is the input end of the delay chain, the output end of the 1 st inverter is the output end of the delay chain, when k > 0, the input end of the 1 st inverter is the input end of the delay chain, the output end of the j-th inverter is connected with the input end of the j+1th inverter, j=1, 2, …,2k, and the output end of the 2k+1th inverter is the output end of the delay chain; the input end of the delay chain, the grid electrode of the first PMOS tube P1 and the grid electrode of the second NMOS tube N2 are connected, the connection end of the delay chain is the input end of the single-input delay inverter C1, the output end of the delay chain, the grid electrode of the second PMOS tube P2 and the grid electrode of the first NMOS tube N1 are connected, the source electrode of the first PMOS tube P1 is connected with a power supply, the drain electrode of the first PMOS tube P1 is connected with the source electrode of the second PMOS tube P2, the drain electrode of the second PMOS tube P2 is connected with the drain electrode of the first NMOS tube N1, the connection end of the second PMOS tube P2 is the output end of the single-input delay inverter C1, the source electrode of the first NMOS tube N1 is connected with the drain electrode of the second NMOS tube N2, and the source electrode of the second NMOS tube N2 is grounded;
as shown in fig. 3, the dual-input delay inverter C2 includes a first inverter F1, a third PMOS tube P3, a fourth PMOS tube P4, a third NMOS tube N3 and a fourth NMOS tube N4, where the first inverter F1 has an input end and an output end, the input end of the first inverter F1 is connected to the gate of the third NMOS tube N3 and the connection end is the first input end of the dual-input delay inverter C2, the output end of the first inverter F1 is connected to the gate of the fourth PMOS tube P4, the gate of the third PMOS tube P3 is connected to the gate of the fourth NMOS tube N4 and the connection end is the second input end of the dual-input delay inverter C2, the source of the third PMOS tube P3 is connected to the power supply, the drain of the third PMOS tube P3 is connected to the source of the fourth PMOS tube P4, the source of the fourth PMOS tube P4 is connected to the drain of the third NMOS tube N3 and the connection end is the output end of the dual-input delay inverter C2, the source of the third NMOS tube N3 is connected to the drain of the fourth NMOS tube N4, and the source of the fourth NMOS tube N4 is connected to the ground;
as shown in fig. 4, the three-input delay inverter C3 includes a second inverter F2, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a seventh NMOS transistor N7, where the second inverter F2 has an input end and an output end, the gate of the fifth PMOS transistor P5 is connected to the gate of the seventh NMOS transistor N7 and the connection end thereof is the third input end of the three-input delay inverter C3, the source of the fifth PMOS transistor P5 and the source of the sixth PMOS transistor P6 are both connected to a power supply, the gate of the sixth PMOS transistor P6 and the gate of the sixth NMOS transistor N6 are connected to the first input end of the three-input delay inverter C3, the drain of the fifth PMOS transistor P5, the drain of the sixth PMOS transistor P6 and the source of the seventh PMOS transistor P7 are connected, the gate of the seventh PMOS transistor P7 and the output end of the seventh NMOS transistor F2 are connected to the gate of the fifth PMOS transistor N5 and the drain of the seventh NMOS transistor N7, and the drain of the seventh NMOS transistor N7 are connected to the drain of the seventh NMOS transistor N6;
as shown in fig. 5, the SET suppression circuit has a first input terminal connected to a storage node N1 in the main latch of the flip-flop, a second input terminal connected to the data input terminal of the flip-flop, a third input terminal connected to the clock signal CLK, and an output terminal connected to the clock terminal of the flip-flop. When the global clock CLK jumps from '1' to '0', the trigger enters a transparent state, when the global clock CLK jumps from '0' to '1', the trigger enters a sampling state, at this time, the trigger performs data sampling only when the input data accessed by the data input end of the trigger is different from the data stored by the trigger, when the data of the trigger storage node N1 is '0', the data input end of the trigger generates a positive SET pulse, CLK is low, the trigger is in the transparent state, at this time, due to the delay action of the single-input delay inverter C1, a negative short pulse is generated after the NOR gate, so that the first input end of the three-input delay inverter C3 also generates a negative short pulse, thereby generating a positive short pulse CP at the output end of the three-input delay inverter C3, turning off the transparent state of the trigger, preventing errors generated by SET from being sampled when the rising edge of the clock comes, and thus restraining SEU errors generated by SET. When the SET occurs in the flip-flop, the CLK waveform is shown in fig. 6 (a), the waveform of the input signal accessed to the data input terminal of the flip-flop is shown in fig. 6 (b), the waveform of the output signal NDR of the nor gate is shown in fig. 6 (c), and the waveform of the output signal CP of the three-input delay inverter is shown in fig. 6 (d).
Claims (1)
1. The SET suppression circuit for the anti-radiation trigger is characterized by comprising a two-input exclusive-OR gate, a two-input NOR gate, a single-input delay inverter, a double-input delay inverter and a three-input delay inverter, wherein the two-input exclusive-OR gate is provided with a first input end, a second input end and an output end, the two-input NOR gate is provided with a first input end, a second input end and an output end, the single-input delay inverter is provided with an input end and an output end, the double-input delay inverter is provided with a first input end, a second input end and an output end, and the three-input delay inverter is provided with a first input end, a second input end, a third input end and an output end; the first input end of the two-input exclusive-OR gate is the first input end of the SET suppression circuit, the second input end of the two-input exclusive-OR gate, the input end of the single-input delay inverter and the second input end of the two-input nor gate are connected, the output end of the two-input exclusive-OR gate is connected with the first input end of the three-input delay inverter, the second input end of the three-input delay inverter is the third input end of the SET suppression circuit, the third input end of the three-input delay inverter, the output end of the two-input nor gate and the second input end of the two-input delay inverter are connected, the output end of the three-input delay inverter is the output end of the SET suppression circuit, and the output end of the single-input delay inverter is connected with the first input end of the two-input exclusive-OR gate; the single-input delay inverter comprises a delay chain, a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, wherein the delay chain comprises 2k+1 inverters, k is an integer greater than or equal to 0, when k=0, the input end of the 1 st inverter is the input end of the delay chain, the output end of the 1 st inverter is the output end of the delay chain, when k > 0, the input end of the 1 st inverter is the input end of the delay chain, the output end of the j-th inverter is connected with the input end of the j+1th inverter, j=1, 2, …,2k, and the output end of the 2k+1th inverter is the output end of the delay chain; the input end of the delay chain, the grid electrode of the first PMOS tube and the grid electrode of the second NMOS tube are connected, the connection end of the delay chain is the input end of the single-input delay inverter, the output end of the delay chain, the grid electrode of the second PMOS tube and the grid electrode of the first NMOS tube are connected, the source electrode of the first PMOS tube is connected with a power supply, the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube, the connection end of the second PMOS tube is the output end of the single-input delay inverter, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded; the double-input delay inverter comprises a first inverter, a third PMOS tube, a fourth PMOS tube, a third NMOS tube and a fourth NMOS tube, wherein the first inverter is provided with an input end and an output end, the input end of the first inverter is connected with the grid electrode of the third NMOS tube, the connection end of the first inverter is the first input end of the double-input delay inverter, the output end of the first inverter is connected with the grid electrode of the fourth PMOS tube, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth NMOS tube, the connection end of the third NMOS tube is the second input end of the double-input delay inverter, the source electrode of the third PMOS tube is connected with a power supply, the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube, the source electrode of the fourth PMOS tube is connected with the drain electrode of the third NMOS tube, the connection end of the third NMOS tube is the output end of the double-input delay inverter, and the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube; the third input delay inverter comprises a second inverter, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube, wherein the second inverter is provided with an input end and an output end, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the seventh NMOS tube, the connection end of the grid electrode of the fifth PMOS tube is the third input end of the third input delay inverter, the source electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube, the grid electrode of the sixth PMOS tube is connected with the grid electrode of the sixth NMOS tube, the connection end of the grid electrode of the sixth PMOS tube is the first input end of the third input delay inverter, the drain electrode of the fifth PMOS tube, the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube, the grid electrode of the seventh PMOS tube is connected with the output end of the seventh NMOS tube, and the drain electrode of the seventh NMOS tube is connected with the drain electrode of the seventh NMOS tube; a first input end of the SET suppression circuit is connected with a storage node N1 in a main latch of the trigger, a second input end of the SET suppression circuit is connected with a data input end of the trigger, a third input end of the SET suppression circuit is connected with a clock signal CLK, and an output end of the SET suppression circuit is connected with a clock end of the trigger; when the global clock CLK jumps from '1' to '0', the trigger enters a transparent state, when the global clock CLK jumps from '0' to '1', the trigger enters a sampling state, at this time, the trigger performs data sampling only when the input data accessed by the data input end of the trigger is different from the data stored by the trigger, when the data of the trigger storage node N1 is '0', the data input end of the trigger generates a positive SET pulse, CLK is low, the trigger is in the transparent state, at this time, due to the delay effect of the single-input delay inverter, a negative short pulse is generated after the NOR gate, thus a positive short pulse CP is generated at the output end of the three-input delay inverter, the transparent state of the trigger is turned off, the SEU error generated by the SET is prevented from being sampled when the clock rising edge arrives, and the SEU error generated by the SET is restrained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010016917.6A CN111241770B (en) | 2020-01-08 | 2020-01-08 | Low-power-consumption SET suppression circuit for trigger under radiation environment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010016917.6A CN111241770B (en) | 2020-01-08 | 2020-01-08 | Low-power-consumption SET suppression circuit for trigger under radiation environment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111241770A CN111241770A (en) | 2020-06-05 |
| CN111241770B true CN111241770B (en) | 2023-11-24 |
Family
ID=70865847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010016917.6A Active CN111241770B (en) | 2020-01-08 | 2020-01-08 | Low-power-consumption SET suppression circuit for trigger under radiation environment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111241770B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101022035A (en) * | 2007-03-02 | 2007-08-22 | 清华大学 | 'Soft error' suppress circuit based on isolate method |
| CN104202037A (en) * | 2014-08-20 | 2014-12-10 | 合肥工业大学 | Single event radiation effect resistant reinforced latch circuit |
| CN104270141A (en) * | 2014-08-14 | 2015-01-07 | 合肥工业大学 | Latch capable of resisting single event upset and single event transient pulse |
| CN105897223A (en) * | 2016-03-31 | 2016-08-24 | 中国人民解放军国防科学技术大学 | D trigger resistant to single event upset |
| CN108352834A (en) * | 2016-09-12 | 2018-07-31 | 纳尔逊曼德拉大学 | Method and circuit for inhibiting single-event transients or burr in Fundamental Digital Circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060119410A1 (en) * | 2004-12-06 | 2006-06-08 | Honeywell International Inc. | Pulse-rejecting circuit for suppressing single-event transients |
| CN105897243B (en) * | 2016-03-31 | 2017-06-06 | 中国人民解放军国防科学技术大学 | A kind of clock driver circuit of anti-single particle transient state |
-
2020
- 2020-01-08 CN CN202010016917.6A patent/CN111241770B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101022035A (en) * | 2007-03-02 | 2007-08-22 | 清华大学 | 'Soft error' suppress circuit based on isolate method |
| CN104270141A (en) * | 2014-08-14 | 2015-01-07 | 合肥工业大学 | Latch capable of resisting single event upset and single event transient pulse |
| CN104202037A (en) * | 2014-08-20 | 2014-12-10 | 合肥工业大学 | Single event radiation effect resistant reinforced latch circuit |
| CN105897223A (en) * | 2016-03-31 | 2016-08-24 | 中国人民解放军国防科学技术大学 | D trigger resistant to single event upset |
| CN108352834A (en) * | 2016-09-12 | 2018-07-31 | 纳尔逊曼德拉大学 | Method and circuit for inhibiting single-event transients or burr in Fundamental Digital Circuit |
Non-Patent Citations (2)
| Title |
|---|
| 一种单粒子效应加固RS触发器电路设计;王佳;李萍;郑然;魏晓敏;胡永才;;微电子学与计算机(第09期);第61-64、69页 * |
| 抗单粒子翻转的低功耗锁存器设计;梁华国;李昕;王志;黄正峰;;计算机辅助设计与图形学学报(第08期);第164-171页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111241770A (en) | 2020-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Calin et al. | Upset hardened memory design for submicron CMOS technology | |
| US7236001B2 (en) | Redundancy circuits hardened against single event upsets | |
| Sasaki et al. | Soft error masking circuit and latch using Schmitt trigger circuit | |
| Jagannathan et al. | Single-event tolerant flip-flop design in 40-nm bulk CMOS technology | |
| US8324951B1 (en) | Dual data rate flip-flop circuit | |
| US7679403B2 (en) | Dual redundant dynamic logic | |
| Guo et al. | Design and evaluation of low-complexity radiation hardened CMOS latch for double-node upset tolerance | |
| Rajaei et al. | Single event upset immune latch circuit design using C-element | |
| Devarapalli et al. | SEU-hardened dual data rate flip-flop using C-elements | |
| US8384419B2 (en) | Soft-error resistant latch | |
| Sayil | A survey of circuit-level soft error mitigation methodologies | |
| CN111211769B (en) | Latch capable of resisting single event upset and data trigger | |
| US7411411B1 (en) | Methods and systems for hardening a clocked latch against single event effects | |
| CN111988030B (en) | Single-particle three-point overturning reinforced latch | |
| CN111241770B (en) | Low-power-consumption SET suppression circuit for trigger under radiation environment | |
| Garg et al. | A novel, highly SEU tolerant digital circuit design approach | |
| Atias et al. | Single event upset mitigation in low power SRAM design | |
| Chen et al. | Improving circuit robustness with cost-effective soft-error-tolerant sequential elements | |
| Tajima et al. | Soft error tolerant latch designs with low power consumption | |
| Nan et al. | Soft error tolerant latch design with low cost for nanoelectronic systems | |
| Gupta et al. | Soft error resilient and energy efficient dual modular TSPC flip-flop | |
| CN111181545B (en) | Soft error self-checking circuit of running water structure | |
| US20120025885A1 (en) | Multi-bit interlaced latch | |
| CN113726326B (en) | Latch structure capable of tolerating single-event double-point overturn | |
| Jahinuzzaman et al. | Soft error robust impulse and TSPC flip-flops in 90nm CMOS |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |