WO2024060469A1

WO2024060469A1 - Flip-flop circuit and electronic device

Info

Publication number: WO2024060469A1
Application number: PCT/CN2023/070546
Authority: WO
Inventors: 周润发
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-09-19
Filing date: 2023-01-04
Publication date: 2024-03-28
Also published as: CN117767918A

Abstract

A flip-flop circuit (100) and an electronic device. The flip-flop circuit (100) comprises a plurality of signal inverting elements (1), wherein a substrate of a P-type transistor (MP) of each signal inverting element (1) is correspondingly connected to a bias voltage providing circuit (2). The bias voltage providing circuit (2) is used for responding to an input end signal (Vin) of the corresponding signal inverting element (1), providing a first substrate bias voltage (V1) for the P-type transistor (MP) when the P-type transistor (MP) in the signal inverting element (1) is turned on, and providing a second substrate bias voltage (V2) for the P-type transistor (MP) when the P-type transistor (MP) in the signal inverting element (1) is not turned on, wherein the first substrate bias voltage (V1) is less than the second substrate bias voltage (V2) and is greater than a PN junction turn-on voltage. The signal inverting element (1) is used for inverting the input end signal (Vin). The flip-flop circuit (100) can repair a signal timing deviation caused by element aging.

Description

Trigger circuits and electronics

cross reference

This disclosure claims priority to the Chinese patent application with application number 202211139843.0 and titled "Trigger Circuit and Electronic Device" filed on September 19, 2022. The entire content of the Chinese patent application is incorporated herein by reference.

Technical field

The present disclosure relates to the field of integrated circuit technology, and in particular, to a flip-flop circuit capable of correcting signal duty cycle deviation problems and electronic equipment applying the flip-flop circuit.

Background technique

NBTI (Negative Bias Temperature Instability) is a major reliability issue faced by current and future processes.

NBTI mainly refers to the instability caused by device parameters (such as turn-on voltage Vt, transconductance Gm, drain current Id) drifting over time when PMOS is in the inversion working state. The main reason is the degradation of PMOS during the static stress process. If PMOS does not receive effective recovery time after long-term stress, it will lead to signal waveform deformation, timing drift (including duty cycle changes) in the logic circuit, and even potential circuit failure.

It should be noted that the information disclosed in the above background section is only used to enhance understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to those of ordinary skill in the art.

Contents of the invention

The purpose of the present disclosure is to provide a flip-flop circuit and electronic device for overcoming, at least to a certain extent, the problem of PMOS causing output signal waveform changes after long-term use.

According to a first aspect of the present disclosure, a flip-flop circuit is provided, including a plurality of signal inverting elements. The substrate of a P-type transistor of each signal inverting element is connected to a bias voltage providing circuit. The voltage providing circuit is used to respond to the input signal of the corresponding signal inverting element, and when the P-type transistor in the signal inverting element is turned on, provide a first substrate bias voltage to the P-type transistor. When the P-type transistor in the signal inverting element is not turned on, a second substrate bias voltage is provided to the P-type transistor, and the first substrate bias voltage is smaller than the second substrate bias voltage and Greater than the PN junction conduction voltage, the signal inverting element is used to invert the input signal.

In an exemplary embodiment of the present disclosure, each of the bias supply circuits includes: a first switching element, a first end connected to the first substrate bias, and a second end connected to the bias. Provide the substrate of the P-type transistor in the signal inverting element corresponding to the circuit, and the control terminal is connected to the gate of the P-type transistor in the signal inverting element corresponding to the bias providing circuit; the second switching element, the first The second terminal is connected to the second substrate bias, the second terminal is connected to the second terminal of the first switching element, and the control terminal is connected to the drain of the P-type transistor of the signal inverting element corresponding to the bias providing circuit. .

In an exemplary embodiment of the present disclosure, the flip-flop circuit includes: a first inverter, the input terminal is the input terminal of the flip-flop circuit, the output terminal is connected to a first node, and the first inverter The substrate of the P-type transistor in the phase device is connected to a first bias supply circuit, and the first inverter is one of the plurality of signal inversion elements; the first transmission gate, the first control terminal is connected to the clock signal, The second control terminal is connected to the complementary clock signal, the input terminal is connected to the first node, and the output terminal is connected to the second node; the second inverter has the input terminal connected to the second node, and the output terminal is connected to the third node. The substrate of the P-type transistor in the two inverters is connected to the second bias supply circuit, and the second inverter is one of the plurality of signal inverting elements; the second transmission gate, the first control terminal is connected to The complementary clock signal, the second control terminal is connected to the clock signal, the input terminal is connected to the third node, and the output terminal is connected to the fourth node; the third inverter, the input terminal is connected to the fourth node, and the output terminal is connected to the third node. Five nodes, the substrate of the P-type transistor in the third inverter is connected to a third bias providing circuit, the third inverter is one of the plurality of signal inverting elements; the fourth inverter , the input end is connected to the fifth node, the output end is the first output end of the flip-flop circuit, the substrate of the P-type transistor in the fourth inverter is connected to the fourth bias supply circuit, and the third The four inverters are one of the plurality of signal inverting elements; the fifth inverter has an input terminal connected to the output terminal of the fourth inverter, and the output terminal is the second output terminal of the flip-flop circuit, The substrate of the P-type transistor in the fifth inverter is connected to the third bias supply circuit, and the fifth inverter is one of the plurality of signal inversion elements.

In an exemplary embodiment of the present disclosure, it further includes: a first feedback circuit, with an input terminal connected to the third node and an output terminal connected to the second node, for converting the clock signal and the complementary clock signal to the first feedback circuit. The potential of the third node is inverted and then fed back to the second node, and the first feedback circuit includes an odd number of the signal inverting elements.

In an exemplary embodiment of the present disclosure, the first feedback circuit includes: a first P-type transistor with a source connected to the power supply voltage and a gate connected to the third node; a second P-type transistor with a source connected to the power supply voltage. The drain of the first P-type transistor is connected, the gate is connected to the clock signal, and the drain is connected to the second node; the source of the first N-type transistor is connected to ground, and the gate is connected to the third node; the second An N-type transistor has a source connected to the drain of the first N-type transistor, a gate connected to the complementary clock signal, and a drain connected to the second node.

In an exemplary embodiment of the present disclosure, the substrates of the first P-type transistor and the second P-type transistor are both connected to a fifth bias providing circuit.

In an exemplary embodiment of the present disclosure, the first feedback circuit includes an odd number of inverters connected in series and a first feedback transmission gate, and two control terminals of the first feedback transmission gate are respectively connected to the clock signal and the complementary clock signal.

In an exemplary embodiment of the present disclosure, it further includes: a second feedback circuit, the input end is connected to the fifth node, and the output end is connected to the fourth node, for converting the clock signal and the complementary clock signal according to the clock signal and the complementary clock signal. The potential of the fifth node is inverted and then fed back to the fourth node, and the second feedback circuit includes an odd number of the signal inverting elements.

In an exemplary embodiment of the present disclosure, the second feedback circuit includes: a third P-type transistor with a source connected to the power supply voltage and a gate connected to the fifth node; a fourth P-type transistor with a source connected to the power supply voltage. The drain of the third P-type transistor is connected, the gate is connected to the complementary clock signal, and the drain is connected to the fourth node; the source of the third N-type transistor is connected to ground, and the gate is connected to the fifth node; Four N-type transistors, the source is connected to the drain of the third N-type transistor, the gate is connected to the clock signal, and the drain is connected to the fourth node.

In an exemplary embodiment of the present disclosure, substrates of the third P-type transistor and the fourth P-type transistor are both connected to the fourth bias supply circuit.

In an exemplary embodiment of the present disclosure, the second feedback circuit includes an odd number of inverters and a second feedback transmission gate connected in series, and two control terminals of the second feedback transmission gate are respectively connected to the clock signal and the complementary clock signal.

In an exemplary embodiment of the present disclosure, it further includes: a reset circuit, the input end is used to receive a reset signal, the output end is connected to the fourth node, and is used to output to the fourth node in response to the reset signal. reset level.

In an exemplary embodiment of the present disclosure, the reset level is a low level, the reset circuit includes a first reset transistor, the first reset transistor is an N-type transistor, and the first reset transistor The source electrode is connected to ground, the drain electrode is connected to the fourth node, and the gate electrode is used to connect the first reset signal.

In an exemplary embodiment of the present disclosure, the reset level is a high level, the reset circuit includes a second reset transistor, the second reset transistor is a P-type transistor, and the second reset transistor The source electrode is connected to the power supply voltage, the drain electrode is connected to the fourth node, and the gate electrode is used to connect the second reset signal.

According to a second aspect of the present disclosure, an electronic device is provided, including the flip-flop circuit as described in any one of the above.

Embodiments of the present disclosure can effectively overcome the NBTI effect of the P-type transistor caused by increased stress time and insufficient recovery time by increasing the substrate bias of the P-type transistor when the P-type transistor is turned on, and correct the signal distortion caused by the NBTI effect. .

It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and do not limit the present disclosure.

Description of the drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

FIG. 1 is a schematic diagram of a flip-flop circuit in an embodiment of the present disclosure.

FIG. 2 is a schematic diagram of a bias voltage providing circuit in an embodiment of the present disclosure.

FIG. 3 is a schematic structural diagram of a flip-flop circuit in an embodiment of the present disclosure.

FIG. 4 is a timing diagram of the circuit shown in FIG. 3 .

Figures 5A and 5B are timing diagrams of the flip-flop circuit before and after the improvement respectively.

Figure 6 is a schematic structural diagram of a first feedback circuit in an embodiment of the present disclosure.

Figure 7 is a schematic structural diagram of a second feedback circuit in an embodiment of the present disclosure.

FIG. 8 is a schematic structural diagram of a reset circuit in an embodiment of the present disclosure.

Detailed ways

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments. To those skilled in the art. The described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details described, or other methods, components, devices, steps, etc. may be adopted. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the disclosure.

In addition, the drawings are only schematic illustrations of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and/or processor devices and/or microcontroller devices.

Example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

Referring to Figure 1, the flip-flop circuit 100 includes a plurality of signal inverting elements 1. The substrate of the P-type transistor of each signal inverting element 1 is connected to a bias providing circuit 2. The bias providing circuit 2 is used to respond to the corresponding The input signal of the signal inverting element 1, when the P-type transistor in the signal inverting element is turned on, provides the first substrate bias V1 to the P-type transistor, and the P-type transistor in the signal inverting element is not turned on. When turned on, the second substrate bias V2 is provided to the P-type transistor. The first substrate bias V1 is smaller than the second substrate bias V2 and larger than the PN junction turn-on voltage. The signal inverting element 1 is used to invert the input signal Perform inversion.

In the embodiment of the present disclosure, the flip-flop circuit 100 may be a D flip-flop, for example. Figure 1 shows a D flip-flop. The D flip-flop is an information storage device with memory function and two stable states. The two stable states of the D flip-flop are "0" and "1" respectively. Under the action of a certain external signal, it can flip from one stable state to another. The D flip-flop is composed of multiple gate circuits. The triggering methods are level triggering and edge triggering. The former can be triggered when CP (clock pulse) is equal to 1, and the latter can be triggered on the leading edge of CP (positive transition 0→1). For edge D flip-flops, since the circuit has a maintaining blocking effect during CP=1, the change in data state at the input terminal of the D flip-flop during CP=1 will not affect the output state of the D flip-flop. The D flip-flop in the embodiment of the present disclosure may be edge triggered or level triggered.

In the embodiment of the disclosure, the flip-flop shown in Figure 1 is taken as an example for explanation. In other embodiments of the disclosure, the flip-flop can also be in other circuit forms, and the P-type transistor connected to the bias supply circuit can also be located in other Locations where NBTI effects may exist.

The transmission delay time t _d of the P-type transistor conforms to the following formula:

Among them, V _DD is the power circuit, I _D is the drain current of the P-type transistor, W and L are the channel width and channel length of the P-type transistor respectively, μ _eff is the carrier mobility, and _VT is the P-type transistor. The threshold voltage of the transistor, C _OX is the capacitance per unit area of the oxide layer between the gate and the substrate.

As the stress time prolongs, the carrier mobility μ _eff decreases and the threshold voltage _VT drifts, causing the transmission delay time t _d to increase and forming a timing drift (a change in the duty cycle).

The embodiment of the present disclosure connects the bias voltage providing circuit 2 to the substrate of the P-type transistor, and enables the bias voltage providing circuit 2 to increase when the corresponding P-type transistor is turned on (that is, the gate voltage of the P-type transistor is lower than the threshold voltage VT). The substrate bias voltage output to the substrate of the P-type transistor can reduce the threshold voltage _VT when the P-type transistor is turned on, correct the increase in the transmission delay time t _d caused by the reduction of the carrier mobility μ _eff , and repair Timing drift.

Referring to Figure 2, in the embodiment of the present disclosure, each bias voltage providing circuit 2 includes:

The first switching element K1 has a first end connected to the first substrate bias V1, a second end connected to the substrate of the P-type transistor in the signal inverting element 1 corresponding to the bias providing circuit, and a control end connected to the corresponding bias providing circuit. The gate of the P-type transistor of the signal inverting element;

The second switching element K2 has a first end connected to the second substrate bias voltage V2, a second end connected to the second end of the first switching element, and a control end connected to the P-type transistor of the signal inverting element 1 corresponding to the bias supply circuit. drain.

In the embodiment shown in FIG. 2 , an inverter is used as an example of the signal inversion element 1 . In other embodiments, the signal inversion element 1 can also be other elements with inversion functions, such as NOT gates and NANDs. Gate, NOR gate and other logic gate circuits. In addition, both the first switching element K1 and the second switching element K2 are P-type transistors.

The signal inversion element 1 includes a P-type transistor MP and an N-type transistor MN, where the source voltage of the P-type transistor MP is connected to a power supply voltage equal to the second substrate bias voltage V2, that is, in one embodiment, the second substrate bias voltage Voltage V2 is equal to the supply voltage of flip-flop circuit 100.

When the input signal Vin of the signal inverting element 1 is low level, the first switching element K1 is turned on, the P-type transistor MP is turned on, the substrate bias of the P-type transistor MP is equal to the first substrate bias V1, and the N-type transistor MN is turned off, the output signal Vout of the signal inverting element 1 is equal to the high level, and the second switching element K2 is turned off.

When the input signal Vin of the signal inverting element 1 is at a high level, the first switch element K1 is turned off, the P-type transistor MP is turned off, the N-type transistor MN is turned on, the output signal Vout of the signal inverting element 1 is equal to a low level, the second switch element K2 is turned on, and the substrate bias of the P-type transistor MP is equal to the second substrate bias V2, that is, the power supply voltage connected to the source of the P-type transistor MP, so that the threshold voltage _VT when the P-type transistor MP is turned on is negatively offset compared to when the P-type transistor MP is not turned on, and the drain current increases, thereby reducing the transmission delay time _td .

Next, the application scenarios of the bias voltage supply circuit shown in Figure 2 are introduced through specific circuits.

Referring to Figure 3, flip-flop circuit 300 may include:

The input terminal of the first inverter OP1 is the input terminal of the flip-flop circuit, and the output terminal is connected to the first node N1. The substrate of the P-type transistor in the first inverter OP1 is connected to the first bias supply circuit 31. The inverter OP1 is one of multiple signal inverting components;

The first transmission gate TG1 has a first control terminal connected to the clock signal CLK, a second control terminal connected to the complementary clock signal CLKB, an input terminal connected to the first node N1, and an output terminal connected to the second node N2;

The input terminal of the second inverter OP2 is connected to the second node N2, and the output terminal is connected to the third node N3. The substrate of the P-type transistor in the second inverter OP2 is connected to the second bias supply circuit 32, and the second inverter OP2 is connected to the third node N3. OP2 is one of multiple signal inverting components;

In the second transmission gate TG2, the first control terminal is connected to the complementary clock signal CLKB, the second control terminal is connected to the clock signal CLK, the input terminal is connected to the third node N3, and the output terminal is connected to the fourth node N4;

A third inverter OP3, the input end of which is connected to the fourth node N4, the output end of which is connected to the fifth node N5, the substrate of the P-type transistor in the third inverter OP3 is connected to the third bias supply circuit 33, and the third inverter OP3 is one of the plurality of signal inverting elements;

The input terminal of the fourth inverter OP4 is connected to the fifth node N5, and the output terminal is the first output terminal Q of the flip-flop circuit. The substrate of the P-type transistor in the fourth inverter OP4 is connected to the fourth bias supply circuit 34 , the fourth inverter OP4 is one of multiple signal inverting elements;

The input terminal of the fifth inverter OP5 is connected to the output terminal of the fourth inverter OP4, the output terminal is the second output terminal QB of the flip-flop circuit, and the substrate of the P-type transistor in the fifth inverter OP5 is connected to the third In the bias voltage providing circuit 33, the fifth inverter OP5 is one of a plurality of signal inverting elements.

The level states of the complementary clock signal CLKB and the clock signal CLK are completely opposite.

In the embodiment shown in FIG. 3 , the structure and working principle of the bias providing circuit corresponding to each inverter are the same as those of the bias providing circuit in the embodiment shown in FIG. 2 . The output node of the first bias providing circuit 31 is A1, the output node of the second bias providing circuit 32 is A2, the output node of the third bias providing circuit 33 is A3, and the output node of the fourth bias providing circuit 34 is A4. The substrate of the P-type transistor of the fifth inverter OP5 is connected to the output node A3 of the third bias supply circuit 33 .

The first transmission gate TG1 is used to control the output signal of the first inverter OP1 to be transmitted from the first node N1 to the second node N2 when the clock signal CLK is high level; the transmission gate TG2 is used to control the output signal of the first inverter OP1 from the first node N1 to the second node N2 when the clock signal CLK is low level. Normally, the output signal controlling the second inverter OP2 is transmitted from the third node N3 to the fourth node N4.

The structure of the first transmission gate TG1 can be seen in the example of the dotted line box on the left side of Figure 3 . The first transmission gate TG1 can be composed of a P-type transistor MPTG and an N-type transistor MNTG. The first end of the P-type transistor MPTG is connected to the first node N1, and the second end is connected to the second node N2. The gate is connected to the complementary clock signal CLKB; The first terminal of the N-type transistor MNTG is connected to the first node N1, the second terminal is connected to the second node N2, and the gate is connected to the clock signal CLK. When the clock signal CLK is at a low level and the complementary clock signal CLKB is at a high level, the N-type transistor MNTG is turned off, the P-type transistor MPTG is turned off, and the first transmission gate TG1 is turned off; when the clock signal CLK is at a high level and the complementary clock signal When the clock signal CLKB is low level, the N-type transistor MNTG is turned on, the P-type transistor MPTG is turned on, and the first transmission gate TG1 transmits the signal of the first node N1 to the second node N2.

The structure of the second transmission gate TG2 may be the same as that of the first transmission gate TG1. Only the gate of the P-type transistor is connected to the clock signal CLK, and the gate of the N-type transistor is connected to the complementary clock signal CLKB, so that the second transmission gate TG2 only It is turned on when the clock signal CLK is low level and the complementary clock signal CLKB is high level, and the signal of the third node N3 is transmitted to the fourth node N4.

The first transmission gate TG1 and the second transmission gate TG2 are used to control the timing of signals transmitted within the flip-flop circuit. Below, the signal timing of each node will be explained by taking the circuit shown in Figure 3 as an example.

Figure 4 is a timing diagram of the circuit shown in Figure 3.

Referring to Figure 4, the clock signal CLK is a periodic signal with alternating high and low levels. The input signal D of the flip-flop circuit has a rising edge at the first moment T1 and changes from low level to high level. The output node A1 of the first bias supply circuit 31 provides the second substrate bias V2. At the same time, the first inverter OP1 outputs the inverted signal of D, that is, low level, to the first node N1. At the first moment T1, the clock signal CLK is high level, and the first transmission gate TG1 is turned on, turning on the first node N1. The signal at the node N1 is transmitted to the second node N2, the P-type transistor in the second inverter OP2 is turned on, and the second bias supply circuit 32 provides the P-type transistor in the second inverter OP2 with the output node A2. When the substrate bias voltage V1 is applied, the second inverter OP2 outputs a complete rising edge to the third node N3.

Since the clock signal CLK is high level at the first time T1, the second transmission gate TG2 is not conductive until the second time T2, the clock signal CLK is converted to a low level, the second transmission gate TG2 is conductive, and the third transmission gate TG2 is turned on. The high level of node N3 is transmitted to the fourth node N4, the output terminal of the third inverter OP3 outputs a low level to the fifth node N5, and the output node A3 of the third bias supply circuit 33 provides a higher second offset voltage. Bottom bias voltage V2, the output node A4 of the fourth bias voltage providing circuit 34 provides a lower first substrate bias voltage V1.

At the third time T3, the input signal D of the flip-flop circuit changes from high level to low level, the first inverter OP1 outputs a high level to the first node N1, and the output node A1 of the first bias providing circuit 31 Output a lower first substrate bias voltage V1; at this time, the clock signal CLK is high level, the first transmission gate TG1 is turned on, and the signal of the first node N1 is transmitted to the second node N2, and the second inverter OP2 The third node N3 outputs a low level, and the output node A2 of the second bias voltage providing circuit 32 outputs a higher second substrate bias voltage V2.

Since the clock signal CLK is at a high level at the third time T3, the second transmission gate TG2 is turned off, and the fourth node N4 remains at a high level. At the fourth time T4, the clock signal CLK switches to low level, and the second transmission gate TG2 is turned on, transmitting the low level of the third node N3 to the fourth node N4, and then transmits the low level of the third node N3 to the fourth node N4 through the third inverter OP3. The node N5 outputs a high level. At this time, the third bias voltage providing circuit 33 outputs a lower first substrate bias voltage V1 through the output node A3, and the fourth bias voltage providing circuit 34 outputs a lower second substrate bias voltage V1 through the output node A4. Substrate bias V2.

Similar to the above, at the fifth time T5, since the rising edge of the input signal D appears when the clock signal CLK is low level, the first transmission gate TG1 is turned off, and the low level of the first node N1 remains until the sixth time T6. The signal CLK is transmitted from the first node N1 to the second node N2 only when it is high level. When the second inverter OP2 inverts the signal of the second node N2 and then outputs a high level to the third node N3, the second transmission gate TG2 is turned off until the clock signal CLK of the seventh moment T7 switches to a low level. The second transmission gate TG2 is turned on and transmits the high level of the third node N3 to the fourth node N4, causing the third inverter OP3 to present a low level signal to the fifth node N5.

At the eighth time T8, the input signal D appears with a falling edge, the clock signal CLK is low level, and the first transmission gate TG1 is turned off. Therefore, the high level of the first node N1 is not transmitted to the second node N2 until the clock signal CLK is high level at the ninth time T9 and the first transmission gate TG1 is turned on. At the tenth time T10, the clock signal CLK appears with a falling edge, and the second transmission gate TG2 is turned on, transmitting the signal of the third node N3 to the fourth node N4, causing the third inverter OP3 to present a high level to the fifth node N5. Signal.

During the above process, the voltages of the output nodes A1, A2, A3, and A4 of each bias voltage supply circuit change with the input signals of their corresponding inverters, which will not be described again here.

It can be seen from the timing diagram shown in FIG. 4 that through the first transmission gate TG1 and the second transmission gate TG2, the duration of the output signal of the flip-flop circuit is controlled to be an integer multiple of the period of the clock signal CLK.

Referring to Figure 5A, when the bias supply circuit is not added, at the first time T1, after the input signal D is transmitted to the input terminal of the first inverter OP1, the output terminal of the first inverter OP1 outputs the inverse of the input signal D. Believe the signal. The first transmission gate TG1 is turned on, the second node N2 appears low level, and the third node N3, as the output node of the second inverter OP2, is affected by the NBTI effect of the P-type transistor in the second inverter OP2 and appears rising. Along the deformation, the second transmission gate TG2 is turned off.

At the second time T2, the clock signal CLK has a falling edge, the second transmission gate TG2 is turned on, and the high-level signal of the third node N3 is transmitted to the fourth node N4, causing the third inverter OP3 to output to the fifth node N5. low level.

At the third time T3, when the input signal D transitions from high level to low level, the P-type transistor in the first inverter OP1 is turned on. Affected by the NBTI effect, the transmission delay time of the P-type transistor increases, resulting in the The signal output from the inverter OP1 to the second node N2 is deformed. At this time, the clock signal CLK is at a high level, and the first transmission gate TG1 is turned on. However, because the signal at the second node N2 is deformed and the rising amplitude is small, the rising edge cannot be transmitted to the second node N2. Moreover, at the subsequent fourth time T4, when the falling edge of the clock signal CLK occurs and the first transmission gate TG1 is turned off, the rising amplitude of the signal at the first node N1 still does not meet the transmission requirement to pass through the first transmission gate TG1, resulting in the The new drug of the second node N2 has been maintained at a low level. Correspondingly, the timing of signals at other locations is out of order.

It is not until one clock cycle later that the first transmission gate TG1 is turned on again that the rising edge of the first node N1 is transmitted to the second node N2. However, at this time, the signal timing is already significantly different from the input signal D.

In addition, it can be seen that the rising edge of the output signal of the third inverter OP3 (fifth node N5) is also deformed.

Referring to Figure 5B, after adding the bias supply circuit, since each inverter reduces the substrate bias of the P-type transistor at the rising edge of the output signal, the output delay time of the rising edge of the signal (i.e., signal deformation) is reduced. , the signal of the first node N1 can be transmitted to the second node N2 while the first transmission gate TG1 is turned on, and the signal shape and timing of subsequent nodes have also been repaired.

Therefore, embodiments of the present disclosure can repair the rising edge deformation of the output signal of each signal inverting element caused by the NBTI effect by reducing the substrate bias of the P-type transistor when the P-type transistor of the signal inverting element is turned on. The signal timing is then effectively repaired.

In another embodiment of the present disclosure, in order to further control the signal timing, the flip-flop circuit may further include a first feedback circuit FB1, the input end of the first feedback circuit FB1 is connected to the third node N3, and the output end is connected to the second node N2, The first feedback circuit FB1 is used to invert the potential of the third node N3 and then feed it back to the second node N2 according to the clock signal CLK and the complementary clock signal CLKB. The first feedback circuit FB1 includes an odd number of signal inverting elements.

FIG. 6 is a schematic diagram of the structure of a first feedback circuit in an embodiment of the present disclosure.

Referring to Figure 6, in one embodiment, the first feedback circuit FB1 may include:

The source of the first P-type transistor MP1 is connected to the power supply voltage VDD, and the gate is connected to the third node N3;

The source of the second P-type transistor MP2 is connected to the drain of the first P-type transistor MP1, the gate is connected to the clock signal CLK, and the drain is connected to the second node N2;

The first N-type transistor MN1 has its source connected to ground and its gate connected to the third node N3;

The source of the second N-type transistor MN2 is connected to the drain of the first N-type transistor MN1, the gate is connected to the complementary clock signal CLKB, and the drain is connected to the second node N2.

In the embodiment shown in FIG. 6 , when the clock signal CLK is at a high level and the complementary clock signal CLKB is at a low level, both the second P-type transistor MP2 and the second N-type transistor MN2 are turned off, and the first feedback circuit FB1 does not Work.

Only when the clock signal CLK is low level and the complementary clock signal CLKB is high level, the second P-type transistor MP2 is turned on and the second N-type transistor MN2 is turned on. The first feedback circuit FB1 conducts the signal according to the signal of the third node N3. The second node N2 outputs a signal.

Therefore, the first feedback circuit FB1 can only output a feedback signal to the second node N2 when the clock signal CLK is low level, thereby adjusting the signal of the third node N3 to be aligned with the falling edge of the clock signal CLK, and adjusting the signal of the third node N3 Timing is aligned with the clock signal.

For example, when the clock signal CLK transitions from high level to low level (that is, a falling edge occurs), if the voltage of the second node N2 is high level and is inverted through the second inverter OP2, the voltage of the third node N3 The voltage is low level. At this time, the first P-type transistor MP1 is turned on, the first N-type transistor MN1 is turned off, and the first feedback circuit FB1 outputs a high level to the second node N2. The high level is consistent with the clock signal CLK. Falling edge alignment; if the voltage of the second node N2 is low level, it is inverted through the second inverter OP2, and the voltage of the third node N3 is high level. At this time, the first P-type transistor MP1 is turned off, and the first The N-type transistor MN1 is turned on, and the first feedback circuit FB1 outputs a low level to the second node N2, and the low level is aligned with the falling edge of the clock signal CLK.

In order to prevent the signal quality of the feedback signal output by the first feedback circuit FB1 to the second node N2 from being affected by the NBTI effect, in one embodiment, the substrates of the first P-type transistor MP1 and the second P-type transistor MP2 can be A fifth bias supply circuit (not shown) is connected. The fifth bias supply circuit is used to provide the first substrate bias V1 to the first P-type transistor MP1 and the second P-type transistor MP2 when the first P-type transistor MP1 and the second P-type transistor MP2 are turned on. When the first P-type transistor MP1 and the second P-type transistor MP2 are turned off, the second substrate bias V2 is provided to the first P-type transistor MP1 and the second P-type transistor MP2. Wherein, the second substrate bias voltage V2 is equal to the power supply voltage VDD, for example.

In addition to the first feedback circuit FB1 shown in FIG6 , in another embodiment, the first feedback circuit FB1 may also be implemented by an odd number of inverters connected in series and a first feedback transmission gate (not shown), wherein two control terminals of the first feedback transmission gate are respectively connected to the clock signal CLK and the complementary clock signal CLKB to implement the same control logic as the embodiment shown in FIG4 , i.e., when the clock signal CLK is at a high level, the first feedback circuit FB1 does not output a signal to the second node N2; when the clock signal CLK is at a low level, the first feedback circuit FB1 outputs an inverted signal of the third node N3 to the second node N2, thereby adjusting the signal timing of the second node N2 and the third node N3 to be aligned with the falling edge of the clock signal CLK.

In another embodiment, the flip-flop circuit may also provide a second feedback circuit FB2 between the fourth node N4 and the fifth node N5 to further adjust the timing within the flip-flop circuit. The input end of the second feedback circuit FB2 is connected to the fifth node N5, and the output end is connected to the fourth node N4. It is used to invert the potential of the fifth node N5 and then feed it back to the fourth node N4 according to the clock signal CLK and the complementary clock signal CLKB. The second feedback circuit FB2 includes an odd number of signal inverting elements.

It should be noted that the first feedback circuit FB1 and the second feedback circuit FB2 can be provided separately or jointly, and the present disclosure does not place special restrictions on this.

Referring to Figure 7, in one embodiment, the second feedback circuit FB2 may include:

The source of the third P-type transistor MP3 is connected to the power supply voltage VDD, and the gate is connected to the fifth node N5;

The source of the fourth P-type transistor MP4 is connected to the drain of the third P-type transistor MP3, the gate is connected to the complementary clock signal CLKB, and the drain is connected to the fourth node N4;

The third N-type transistor MN3 has its source connected to ground and its gate connected to the fifth node N5;

The source of the fourth N-type transistor MN4 is connected to the drain of the third N-type transistor MN3, the gate is connected to the clock signal CLK, and the drain is connected to the fourth node N4.

The structure and principle of the second feedback circuit FB2 are similar to the first feedback circuit FB1, and is used to transmit the inverted signal of the signal of the fifth node N5 to the fourth node when the clock signal CLK is low level and the complementary clock signal CLKB is high level. Node N4 will not be described again here.

In one embodiment, the fourth bias supply circuit 34 is connected to the substrates of the third P-type transistor MP3 and the fourth P-type transistor MP4. Since the control signal of the first substrate bias V1 in the fourth bias supply circuit 34 is the signal of the fifth node N5, and the control signal of the second substrate bias V2 is the inverse signal of the signal of the fifth node N5, It can be realized that when the signal of the fifth node N5 is low level and the third P-type transistor MP3 is turned on, the first substrate bias V1 is input to the third P-type transistor MP3 and the fourth P-type transistor MP4. When the signal of the node N5 is high level and the third P-type transistor MP3 is turned off, the second substrate bias V2 is input to the third P-type transistor MP3 and the fourth P-type transistor MP4 to correct the output of the second feedback circuit FB2 The signal is deformed due to the NBTI effect.

Like the first feedback circuit FB1, the second feedback circuit FB2 can also be composed of an odd number of inverters and a second feedback transmission gate connected in series. The two control terminals of the second feedback transmission gate FB2 are connected to the clock signal CLK and the complementary clock respectively. The signal CLKB is used to control the operation of the second feedback circuit FB2 when the clock signal CLK is at a low level and the complementary clock signal CLKB is at a high level.

By setting up the first feedback circuit FB1 and the second feedback circuit FB2, the signal transmission speed between nodes can be accelerated through the clock signal CLK, and charging and discharging conflicts with the main circuit signal can be avoided.

In another embodiment, the flip-flop circuit may include a reset circuit RST, the input terminal is used to receive the reset signal, and the output terminal is connected to the fourth node N4, and is used to output a reset level to the fourth node N4 in response to the reset signal.

Referring to FIG. 8 , the reset circuit 81 may include a first reset transistor MNS and a second reset transistor MPS. The first reset transistor MNS and the second reset transistor MPS are selectively set according to the reset level, that is, the first reset transistor MNS and the second reset transistor MPS. It is sufficient to set only one transistor MPS.

When the reset level is low, the reset circuit 81 may include a first reset transistor MNS. The first reset transistor MNS is an N-type transistor. The source of the first reset transistor MNS is grounded, the drain is connected to the fourth node N4, and the gate is connected to the ground. It is used to connect the first reset signal RST1, and the effective level of the first reset signal RST1 is high level.

When the reset level is high, the reset circuit 81 may include a second reset transistor MPS. The second reset transistor MPS is a P-type transistor. The source of the second reset transistor MPS is connected to the power supply voltage VDD, and the drain is connected to the fourth node N4. , the gate is used to connect the second reset signal RST2, and the effective level of the second reset signal RST2 is low level.

The reset circuit 81 and the first feedback circuit FB1 and the second feedback circuit FB2 can be set selectively or at the same time, and the present disclosure does not place special restrictions on this.

According to a second aspect of the present disclosure, an electronic device is provided, comprising a trigger circuit as shown in any of the above embodiments.

It should be noted that although several modules or units of equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided into being embodied by multiple modules or units.

Other embodiments of the disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure that follow the general principles of the disclosure and include common knowledge or customary technical means in the technical field that are not disclosed in the disclosure. . It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Industrial Applicability

Claims

A flip-flop circuit includes a plurality of signal inverting elements. The substrate of the P-type transistor of each signal inverting element is correspondingly connected to a bias voltage providing circuit. The bias voltage providing circuit is used to respond to all corresponding signals. The input signal of the signal inverting element provides a first substrate bias to the P-type transistor when the P-type transistor in the signal inverting element is turned on. In the signal inverting element When the P-type transistor is not turned on, a second substrate bias voltage is provided to the P-type transistor, and the first substrate bias voltage is smaller than the second substrate bias voltage and larger than the PN junction turn-on voltage, and the The signal inverting element is used to invert the input signal.
The trigger circuit according to claim 1, wherein each of the bias supply circuits comprises:

The first switching element has a first terminal connected to the first substrate bias voltage, a second terminal connected to the substrate of the P-type transistor in the signal inverting element corresponding to the bias voltage providing circuit, and a control terminal connected to the bias voltage. voltage provides the gate of the P-type transistor of the signal inverting element corresponding to the circuit;

The second switching element has a first end connected to the second substrate bias, a second end connected to the second end of the first switching element, and a control end connected to the signal inverting element corresponding to the bias providing circuit. the drain of the P-type transistor.
The flip-flop circuit of claim 1 or 2, wherein the flip-flop circuit includes:

The input terminal of the first inverter is the input terminal of the flip-flop circuit, the output terminal is connected to the first node, and the substrate of the P-type transistor in the first inverter is connected to the first bias supply circuit, and the The first inverter is one of the plurality of signal inverting elements;

In the first transmission gate, the first control terminal is connected to the clock signal, the second control terminal is connected to the complementary clock signal, the input terminal is connected to the first node, and the output terminal is connected to the second node;

A second inverter, an input end of which is connected to the second node, an output end of which is connected to a third node, a substrate of a P-type transistor in the second inverter is connected to a second bias supply circuit, and the second inverter is one of the plurality of signal inverting elements;

In the second transmission gate, the first control terminal is connected to the complementary clock signal, the second control terminal is connected to the clock signal, the input terminal is connected to the third node, and the output terminal is connected to the fourth node;

A third inverter has an input terminal connected to the fourth node and an output terminal connected to a fifth node. The substrate of the P-type transistor in the third inverter is connected to a third bias supply circuit. The third inverter The phaser is one of the plurality of signal inverting elements;

The fourth inverter has an input terminal connected to the fifth node, an output terminal being the first output terminal of the flip-flop circuit, and a substrate of the P-type transistor in the fourth inverter connected to a fourth bias voltage supply. circuit, the fourth inverter is one of the plurality of signal inverting elements;

The input terminal of the fifth inverter is connected to the output terminal of the fourth inverter, the output terminal is the second output terminal of the flip-flop circuit, and the substrate of the P-type transistor in the fifth inverter is connected to The third bias voltage providing circuit, the fifth inverter is one of the plurality of signal inverting elements.
The flip-flop circuit of claim 3, further comprising:

A first feedback circuit, with an input terminal connected to the third node and an output terminal connected to the second node, for inverting the potential of the third node and feeding it back to the second node according to the clock signal and the complementary clock signal. , the first feedback circuit includes an odd number of the signal inverting elements.
The flip-flop circuit of claim 4, wherein the first feedback circuit includes:

The first P-type transistor has a source connected to the power supply voltage and a gate connected to the third node;

A second P-type transistor has a source connected to the drain of the first P-type transistor, a gate connected to the clock signal, and a drain connected to the second node;

A first N-type transistor, with a source connected to the ground and a gate connected to the third node;

The source of the second N-type transistor is connected to the drain of the first N-type transistor, the gate is connected to the complementary clock signal, and the drain is connected to the second node.
The flip-flop circuit of claim 5, wherein substrates of the first P-type transistor and the second P-type transistor are both connected to a fifth bias supply circuit.
The flip-flop circuit of claim 4, wherein the first feedback circuit includes an odd number of inverters and a first feedback transmission gate connected in series, and two control terminals of the first feedback transmission gate are respectively connected to the clock signal and the complementary clock signal.
The flip-flop circuit of claim 3, further comprising:

A second feedback circuit, with an input terminal connected to the fifth node and an output terminal connected to the fourth node, for inverting the potential of the fifth node and then feeding it back to the fourth node according to the clock signal and the complementary clock signal. , the second feedback circuit includes an odd number of the signal inverting elements.
The flip-flop circuit of claim 8, wherein the second feedback circuit includes:

The third P-type transistor has its source connected to the power supply voltage and its gate connected to the fifth node;

The fourth P-type transistor has a source connected to the drain of the third P-type transistor, a gate connected to the complementary clock signal, and a drain connected to the fourth node;

The third N-type transistor has a source connected to ground and a gate connected to the fifth node;

The source of the fourth N-type transistor is connected to the drain of the third N-type transistor, the gate is connected to the clock signal, and the drain is connected to the fourth node.
The flip-flop circuit of claim 9, wherein substrates of the third P-type transistor and the fourth P-type transistor are both connected to the fourth bias supply circuit.
The flip-flop circuit of claim 8, wherein the second feedback circuit includes an odd number of inverters and a second feedback transmission gate connected in series, and two control terminals of the second feedback transmission gate are respectively connected to the clock signal and the complementary clock signal.
The flip-flop circuit of claim 3, further comprising:

A reset circuit has an input terminal for receiving a reset signal, and an output terminal connected to the fourth node, for outputting a reset level to the fourth node in response to the reset signal.
The flip-flop circuit of claim 12, wherein the reset level is a low level, the reset circuit includes a first reset transistor, the first reset transistor is an N-type transistor, and the first reset transistor The source electrode is connected to ground, the drain electrode is connected to the fourth node, and the gate electrode is used to connect the first reset signal.
The flip-flop circuit of claim 12, wherein the reset level is a high level, the reset circuit includes a second reset transistor, the second reset transistor is a P-type transistor, and the second reset transistor The source electrode is connected to the power supply voltage, the drain electrode is connected to the fourth node, and the gate electrode is used to connect the second reset signal.
An electronic device including the flip-flop circuit according to any one of claims 1-14.