CN114567291A

CN114567291A - D flip-flop, and processor and computing device including the same

Info

Publication number: CN114567291A
Application number: CN202210455591.6A
Authority: CN
Inventors: 田文博; 龚川; 范志军; 杨作兴; 郭海丰
Original assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Current assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Priority date: 2022-04-28
Filing date: 2022-04-28
Publication date: 2022-05-31

Abstract

The present disclosure relates to D flip-flops and processors and computing devices including D flip-flops. Provided is a D flip-flop including: an input stage for receiving a flip-flop input (D); an output stage for outputting a flip-flop output (Q)_N) (ii) a An intermediate stage for receiving the output of the input stage via an intermediate node (B) and providing an output to the output stage; and a feedback stage receiving the flip-flop output and providing feedback to the intermediate node, wherein the feedback stage has a logic high state, a logic low state, and a high impedance state, wherein the output of the flip-flop is inverted from the input of the flip-flop.

Description

D flip-flop, and processor and computing device including the same

Technical Field

The present disclosure relates to D flip-flops and processors and computing devices including D flip-flops.

Background

In recent years, digital money has received increasing attention. There is a need in the relevant art for improvements in processors and computing devices for digital currency.

Processors for digital currency require a large number of repetitive logic calculations during operation, which requires a large number of D-flip-flops for data storage. Therefore, the performance of the D flip-flop will directly affect the performance of the processor, including chip area, power consumption, operation speed, and the like.

Compared with a static D trigger, the dynamic D trigger has the advantages that a positive feedback circuit for keeping the working state is reduced, so that the circuit structure is greatly simplified, the area of a chip is reduced, and the power consumption can be reduced. However, since there is a node in the dynamic D flip-flop that floats (floating) in potential for a portion of time, the parasitic capacitance at that node needs to maintain the correct voltage state for that period of time.

To mitigate or avoid device leakage from affecting the voltage at the node, the circuit devices connected to the node need to use low leakage devices. Low leakage devices are typically high threshold devices and are slower than low threshold devices, which also affects the speed of the D flip-flop. Also, the D flip-flop needs to operate at a higher frequency to prevent malfunction. While in certain states of the processor (e.g., sleep or idle states), the D flip-flops may operate at a relatively low frequency, in which case the prior art D flip-flops may experience functional errors.

To solve one or more of the above problems, the present invention provides a semi-static D flip-flop, and a processor and a computing device including the D flip-flop.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a D flip-flop including: an input stage for receiving a flip-flop input (D); an output stage for outputting a flip-flop output (Q)_N) (ii) a An intermediate stage for receiving the output of the input stage via an intermediate node (B) and providing an output to the output stage; and a feedback stage receiving the flip-flop output and providing feedback to the intermediate node, wherein the feedback stage has a logic high state, a logic low state, and a high impedance state, wherein the output of the flip-flopInverted with respect to the input of the flip-flop.

In some embodiments, the feedback stage comprises a tri-state gate comprising: first to fourth transistors connected in series, the first and second transistors being transistors of a first conductivity type, the third and fourth transistors being transistors of a second conductivity type, the second conductivity type being different from the first conductivity type, a control terminal of one of the first and second transistors being connected to the flip-flop output, a control terminal of the other of the first and second transistors being connected to a first clock signal, a control terminal of one of the third and fourth transistors being connected to the flip-flop output, a control terminal of the other of the third and fourth transistors being connected to a second clock signal, wherein the second clock signal is an inverse of the first clock signal, and a node at which the second and third transistors are connected to each other being connected to the intermediate node.

In some embodiments, the feedback stage comprises a series connection of an inverter and a transmission gate, an input of the inverter being connected to the flip-flop output, an output of the inverter being connected to an input of the transmission gate, an output of the transmission gate being connected to the intermediate node, the inverter comprising a first transistor of a first conductivity type and a fourth transistor of a second conductivity type connected in series, the transmission gate comprising a second transistor of the first conductivity type and a third transistor of the second conductivity type connected in parallel, the second conductivity type being different from the first conductivity type, two control terminals of the transmission gate receiving a first clock signal and a second clock signal, respectively, wherein the second clock signal is the inverse of the first clock signal.

In some embodiments, the first conductivity type is P-type, the second conductivity type is N-type, and the feedback stage is turned off when the first clock signal changes from low to high and the second clock signal changes from high to low, thereby assuming a high impedance state; the feedback stage provides feedback to the intermediate node according to the flip-flop output when the first clock signal changes from high to low and the second clock signal changes from low to high.

In some embodiments, the input stage comprises tristate logic which receives the signal input and the first and second clock signals and provides an output to the intermediate stage, the tristate logic assuming a logic high state, a logic low state and a high impedance state in dependence on the input and the first and second clock signals, the input stage being configured to: when the first clock signal changes from low to high and the second clock signal changes from high to low, the input stage is turned off, thereby assuming a high impedance state; the input stage provides an output to the intermediate stage according to the flip-flop input when the first clock signal changes from high to low and the second clock signal changes from low to high.

In some embodiments, the intermediate stage comprises tristate logic receiving the output of the input stage and the first and second clock signals, the tristate logic assuming a logic high state, a logic low state and a high impedance state in dependence on the output of the input stage and the first and second clock signals, the intermediate stage being configured to: the intermediate stage providing an output to the intermediate node according to the output of the input stage when the first clock signal changes from low to high and the second clock signal changes from high to low; when the first clock signal changes from high to low and the second clock signal changes from low to high, the intermediate stage is turned off and assumes a high impedance state.

In some embodiments, the tristate logic comprises an inverter and a transmission gate, the inverter receiving as input the output of the input stage, the output of the inverter being connected to one end of the transmission gate, the other end of the transmission gate being connected to the intermediate node, the control ends of the transmission gate receiving the first and second clock signals respectively.

In some embodiments, the tri-state logic comprises a tri-state gate comprising: fifth to eighth transistors connected in series, the fifth and sixth transistors being transistors of a first conductivity type, the seventh and eighth transistors being transistors of a second conductivity type, a control terminal of one of the fifth and sixth transistors being connected to the output of the input stage, a control terminal of the other of the fifth and sixth transistors being connected to one of the first and second clock signals, a control terminal of one of the seventh and eighth transistors being connected to the output of the input stage, a control terminal of the other of the seventh and eighth transistors being connected to the other of the first and second clock signals, a node at which the sixth and seventh transistors are connected to each other being connected to the intermediate node.

In some embodiments, the D flip-flop is a semi-static flip-flop, and the output stage, the feedback stage, and the intermediate node form a latch.

In some embodiments, the transistors of the first conductivity type are PMOS transistors and the transistors of the second conductivity type are NMOS transistors.

According to an aspect of the present disclosure, there is provided a processor including: at least one D flip-flop, the D flip-flop being a D flip-flop according to any embodiment of the present disclosure.

In some embodiments, the at least one D flip-flop comprises a plurality of D flip-flops, and the processor further comprises a clock circuit for providing a required clock signal to each of the plurality of D flip-flops.

According to an aspect of the present disclosure, there is provided a computing device comprising a processor according to any embodiment of the present disclosure.

In some embodiments, the computing device is a computing device for digital currency.

Compared with the traditional static D trigger, the semi-static D trigger provided by the disclosure changes the main register into the dynamic register, and saves the area and the power consumption under the condition of keeping the same speed. Compared with a dynamic D flip-flop, the slave register is added with one-stage tri-state gate feedback and is changed into a semi-static register (or latch), so that the slave register can work at a lower working frequency. In addition, the speed of the D flip-flop can be increased by using a part of the low threshold device.

The D flip-flop according to the embodiment of the present disclosure may stably maintain the potential of the floating node, and may reduce power consumption of the D flip-flop. The D flip-flop according to the embodiment of the disclosure can work at a lower frequency and also can work at a higher frequency, so that flexibility is provided for processor design, and power consumption is reduced.

Processors and computing devices according to the present disclosure may be used for correlation calculations for digital currencies (e.g., bitcoin, lexel, ethernet, and other digital currencies).

Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The present disclosure may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 shows a schematic block diagram of a D flip-flop according to one embodiment of the present disclosure;

FIG. 2 shows a circuit diagram of a D flip-flop according to one embodiment of the present disclosure;

FIG. 3A shows a schematic circuit diagram of a D flip-flop according to another embodiment of the present disclosure;

FIG. 3B shows a schematic circuit diagram of a D flip-flop according to another embodiment of the present disclosure;

FIG. 3C shows a schematic circuit diagram of a D flip-flop according to another embodiment of the present disclosure;

FIG. 4 shows a schematic block diagram of a processor including a clock circuit and a D flip-flop according to one embodiment of the present disclosure;

FIG. 5 shows a schematic block diagram of a clock circuit according to one embodiment of the present disclosure;

FIG. 6 shows a schematic block diagram of a processor including a clock circuit and a plurality of D flip-flops, according to one embodiment of the present disclosure.

Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In this specification, like reference numerals and letters are used to designate like items, and therefore, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.

For convenience of understanding, the positions, dimensions, ranges, and the like of the respective structures shown in the drawings and the like do not necessarily indicate actual positions, dimensions, ranges, and the like. Therefore, the disclosed invention is not limited to the positions, dimensions, ranges, etc., disclosed in the drawings and the like.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise. Additionally, techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification as appropriate.

It should be appreciated that the following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the disclosure, its application, or uses. It should also be understood that any implementation exemplarily described herein does not necessarily represent that it is preferred or advantageous over other implementations. This disclosure is not limited by any expressed or implied theory presented in the preceding technical field, background, brief summary or the detailed description.

In this context, "tri-state logic" means a logic circuit whose output assumes three states depending on the input and the control signal: a logic high state, a logic low state, and a high impedance state. The control signal may be, for example, a clock signal.

In this context, "tri-state gate" means a "minimum level" of logic gates (or referred to as logic gate circuits) whose output can achieve the three states (logic high state, logic low state, and high resistance state). Here, "logic gate of the minimum hierarchy" means that an individual logic gate or logic unit as a part thereof cannot be separated from the logic gate (tri-state gate).

In addition, certain terminology may also be used in the following description for the purpose of reference only, and is thus not intended to be limiting. For example, the terms "first," "second," and other such numerical terms referring to structures or elements do not imply a sequence or order unless clearly indicated by the context.

It will be further understood that the terms "comprises/comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Fig. 1 shows a schematic block diagram of a D flip-flop according to one embodiment of the present disclosure. As shown IN fig. 1, a D flip-flop 100 according to an embodiment of the present disclosure includes an input stage 101 for receiving an Input (IN), and an output stage 105 for outputting a flip-flop Output (OUT).

D flip-flop 100 includes an intermediate stage (e.g., 103) disposed between output stage 105 and input stage 101. The intermediate stage 103 receives the output of the input stage 101 (via node a) and provides the output to the output stage 105 (via intermediate node B) as an input. An intermediate node B is provided between the output of the intermediate stage 103 and the input of the output stage 105. In operation, the potential of the intermediate node B is floating for a portion of the clock cycle. An input of the output stage 105 receives a signal (e.g., a voltage) at the intermediate node.

The D flip-flop 100 further comprises a feedback stage 107, the feedback stage 107 receiving the flip-flop output OUT and providing feedback to the intermediate node B. According to an embodiment of the present disclosure, the feedback stage 107 has a logic high state, a logic low state, and a high impedance state.

In addition, one or more of the components of the D flip-flop 100 may receive a respective clock signal. As shown in fig. 1, the input stage 101, the intermediate stage 103, and the feedback stage 107 each receive a respective clock. Here, it should be understood that the clock CKs is merely exemplary and does not mean that the input stage 101, the intermediate stage 103, the feedback stage 107, and other components, etc., all receive the same clock signal. Furthermore, although in the embodiment shown in fig. 1, the output stage 105 is shown as not receiving a clock signal, the disclosure is not limited thereto.

Fig. 2 shows a circuit diagram of a D flip-flop according to one embodiment of the present disclosure. As shown in fig. 2, a D flip-flop 200 according to an embodiment of the present disclosure includes an input stage 201, an output stage 205, an intermediate node B, and a feedback stage 207. An intermediate node B is arranged between the output of the input stage and the input of the output stage. During part of the time of operation, the potential at the intermediate node B is floating. The D flip-flop 200 further comprises an intermediate stage 203 between the intermediate node B and the input stage 201.

Input stage 201 receives input D and provides an input (via node a) that is output to intermediate stage 203. Node a is disposed between the input stage and the intermediate stage 203. Here, the input stage 201 is implemented as tristate logic which assumes a logic high state, a logic low state and a high impedance state according to the input D and the first clock signal (CLKP or CLKN) and the second clock signal (CLKN or CLKP). Specifically, the input stage 201 is implemented as a tri-state gate. As shown in fig. 2, the CMOS tri-state gate includes:

transistors

551, 553, 555, and 557 connected in series, wherein the

transistors

551 and 553 are PMOS transistors and the

transistors

555 and 557 are NMOS transistors.

The

transistors

551 and 553 are connected in series with each other, and one end (here, a source) of the transistor 553 is connected to one end (here, a drain) of the transistor 551. A control terminal (gate) of one of the

transistors

551 and 553 is connected to the flip-flop input D, and a control terminal (gate) of the other of the

transistors

551 and 553 is connected to the clock signal CLKP. Preferably, as shown in fig. 2, the gate of transistor 551 is connected to input D and the gate of transistor 553 is connected to clock signal CLKP. One terminal (here, a source) of the transistor 551 is connected to the power supply voltage VDD.

A drain of the PMOS transistor 553 and a drain of the NMOS transistor 555 are connected to each other and to the node a.

Transistors

555 and 557 are connected in series with each other. One terminal (here, a source) of the transistor 555 is connected to one terminal (here, a drain) of the transistor 557. A control terminal (gate) of one of the

transistors

555 and 557 is connected to the input D, while a control terminal (gate) of the other of the

transistors

555 and 557 is connected to the clock signal CLKN. Preferably, as shown in fig. 2, the gate of transistor 557 is connected to input D and the gate of transistor 555 is connected to clock signal CLKN. The other end (here, a source) of the transistor 557 is connected to a low potential Vss (for example, ground GND).

The clock signals CLKP and CLKN are a pair of clock signals having the same frequency but opposite phases; in other words, clock signal CLKP is the inverse of CLKN.

The intermediate stage 203 is connected between node a and an intermediate node B, receives the voltage at node a as an input, and provides an output to node B. Intermediate stage 203 also receives clock signals CLKP and CLKN. Preferably, the intermediate stage 203 is implemented as tristate logic that assumes a logic high state, a logic low state, and a high impedance state according to the received input (e.g., the voltage at node a) and the first clock (CLKP or CLKN) and second clock signal (CLKN or CLKP).

In a preferred embodiment, as shown in FIG. 2, the intermediate stage 203 is implemented as a CMOS tri-state gate comprising four transistors. The CMOS tri-state gate includes:

transistors

541, 543, 545, and 547 are serially connected, wherein

transistors

541 and 543 are PMOS transistors and

transistors

545 and 547 are NMOS transistors.

The

transistors

541 and 543 are connected in series with each other, and one end (here, a source) of the transistor 543 is connected to one end (here, a drain) of the transistor 541. A control terminal (gate) of one of the

transistors

541 and 543 is connected to the output of the input stage 201 (via node a), and a control terminal (gate) of the other of the

transistors

541 and 543 is connected to the clock signal CLKN. Preferably, as shown in fig. 2, a gate of transistor 541 is connected to the output of input stage 201 (via node a), and a gate of transistor 543 is connected to clock signal CLKN. One end (here, a source) of the transistor 541 is connected to the power supply voltage VDD.

The drain of the PMOS transistor 543 and the drain of the NMOS transistor 545 are connected to each other and to the

node B. Transistors

545 and 547 are connected in series with each other. One terminal (here, a source) of the transistor 545 is connected to one terminal (here, a drain) of the transistor 547. A control terminal (gate) of one of the

transistors

545 and 547 is connected to the output of the input stage 201, and a control terminal (gate) of the other of the

transistors

545 and 547 is connected to the clock signal CLKP. Preferably, as shown in fig. 2, the gate of transistor 547 is connected to the output of input stage 201 (via node a) and the gate of transistor 545 is connected to clock signal CLKP. The other end (here, the source) of the transistor 547 is connected to the low potential Vss.

The output stage 205 receives a signal (e.g., voltage) at node B as an input and its output as a flip-flop output Q_N. In the present embodiment, the output stage is implemented as an inverter including

CMOS transistors

511 and 513 connected in series with each other. The transistor 511 is a PMOS transistor, and the transistor 513 is an NMOS transistor. The transistor 511 has a control terminal (gate) connected to the node B, a source connected to the power supply voltage VDD, a drain connected to the drain of the transistor 513, and an output Q_N. The transistor 513 has a gate connected to the node B and a source connected to the low potential Vss.

Here, since the output of the flip-flop is inverted from the flip-flop input D, the flip-flop output is Q-switched_NTo indicate.

Feedback stage 207 receives flip-flop output Q_NAs input and provides feedback to the intermediate node B. Here, the feedback stage is implemented as tri-state logic. In the embodiment shown in fig. 2, the feedback stage 207 is implemented as a tri-state gate having a logic high state, a logic low state and a high impedance state.

In particular, as shown in fig. 2, the tri-state gates of the feedback stage 207 may be implemented by CMOS transistors. The tri-state gate includes:

transistors

521 and 527 connected in series in sequence. The

transistors

521, 523, 525, and 527 are referred to herein as first to fourth transistors, respectively. The first and

second transistors

521 and 523 are PMOS transistors, and the third and

fourth transistors

525 and 527 are NMOS transistors.

The first and

second transistors

521 and 523 are connected in series with each other. One end (here, drain) of the transistor 521 is connected to one end (here, source) of the transistor 523. A control terminal (gate) of one of the first and

second transistors

521 and 523 is connected to the triggerOutput Q of the device_NThe control terminal of the other of the first and

second transistors

521 and 523 is connected to one of the clock signals CLKP and CLKN. Here, in the embodiment shown in fig. 2, the gate of the first transistor 521 is connected to the flip-flop output Q_NThe gate of the second transistor 523 is connected to the clock signal CLKP. The other end (here, source) of the transistor 521 is connected to the power supply voltage VDD. The drain of the PMOS transistor 523 and the drain of the NMOS transistor 525 are connected to each other and to the intermediate node B. The third and

fourth transistors

525 and 527 are connected in series with each other. One end (here, a source) of the transistor 525 is connected to one end (here, a drain) of the transistor 527. A control terminal (gate) of one of the third and

fourth transistors

525 and 527 is connected to the flip-flop output Q_NThe control terminal (gate) of the other of the third and

fourth transistors

525 and 527 is connected to the other of the clock signals CLKP and CLKN. The clock signal CLKN is the inverse of the clock signal CLKP. The other end (here, source) of the transistor 527 is connected to the low potential Vss.

A node F where the second and

third transistors

523 and 525 are connected to each other is connected to the intermediate node B. Here, the drain of the transistor 523 is connected to the drain of the transistor 525 and to the intermediate node B.

It should be appreciated that although in the embodiment shown in fig. 2, the input stage 201, the intermediate stage 203 and the feedback stage 207 are each implemented as tristate gates, in other embodiments they may be implemented in a variety of other ways. Those skilled in the art will readily appreciate that there are many different implementations for implementing tri-state logic and are not limited to the one shown in fig. 2. For example, the tristate logic may also be implemented to include an inverter and a transmission gate, as will be described later with reference to the illustrations of FIGS. 3A-3C. In other embodiments, the signals received by the gates of the P-type transistors in each tri-state gate may be swapped, and correspondingly, the signals received by the gates of the N-type transistors may be swapped. For example, in the feedback stage, it may be configured that the gates of

transistors

521 and 527 are connected to the clock signals CLKP and CLKN, respectively, while the gates of

transistors

523 and 525 are connected to the output Q_N. In the input stage, it may be configured that gates of the

transistors

551 and 557 are connected toClock signals CLKP and CLKN, and the gates of

transistors

553 and 555 are connected to input D. In the intermediate stage, it may be configured that the gates of

transistors

541 and 547 are connected to the clock signals CLKN and CLKP, respectively, and the gates of

transistors

543 and 545 are connected to the output of the input stage 201.

The clock signals CLKN and CLKP may be obtained from the clock signal CK in a manner such as that shown in fig. 5 (which will be described in more detail later). The clock signal CLKP and the clock signal CLKN are inverted with respect to each other, one of which may substantially coincide with the clock signal CK, without regard for delay. For example, here, the clock signal CLKP substantially coincides with the clock signal CK, and the clock signal CLKN is the inverse of the clock signal CLKP (or the clock signal CK).

According to an embodiment of the present disclosure, when clock CK is high (at which time clock signal CLKP is high and clock signal CLKN is low, see, e.g., FIG. 5), tri-state gate 201 is closed, tri-state gate 203 is conductive, and tri-state gate 207 is closed, thereby passing the signal stored at node A through the output stage to output Q_N. When the clock goes low (at which time clock signal CLKP is low and clock signal CLKN is high), tri-state gate 201 is turned on, receiving the signal at input D, tri-state gate 203 is turned off, and tri-state gate 207 is turned on, latching the signal stored at node B, preventing leakage from changing the node signal level. Such an inverted output semi-static D flip-flop according to an embodiment of the present disclosure is not limited by the lowest operating frequency when the clock CK is at a low level. When the clock CK is high, the lowest operating frequency is determined by the leakage rate of the node A.

In addition, to speed up the clock-to-output delay, tri-state gate 203 may use a low threshold device, thereby speeding up the speed of the flip-flop. And tristate gates 207 may use high threshold devices to reduce power leakage.

When the clock signal CLKN changes from low to high, the clock signal CLKP changes from high to low accordingly:

for input stage 201,

transistors

553 and 555 become conductive, at which time tristate gate 201 acts according to input D: when input D is low (logic 0), transistor 551 is on and transistor 557 is off, so node a is high (logic 1); when the input D is high (logic 1), the transistor 551 is turned off and the transistor 557 is turned on, so that the node a is low (logic 0).

For the intermediate stage 203:

transistors

543 and 545 become off at this time, causing tri-state gate 203 to turn off, assuming a high resistance state.

For the feedback stage 207: at this

point transistors

523 and 525 become conductive and tri-state gate 207 is turned on according to output Q_NAnd the action is as follows: when outputting Q_NLow (i.e., high at node B), transistor 521 is on and transistor 527 is off, so that node B is high; when outputting Q_NHigh (i.e., low at node B), transistor 521 is off and transistor 527 is on, so that node B is low (logic 0). So that the signal at node B (also referred to as signal B) can be maintained at a desired potential by feedback.

When the clock signal CLKN changes from high to low, the clock signal CLKP changes from low to high accordingly:

for input stage 201,

transistors

553 and 555 become off, so that tristate gate 201 turns off, assuming a high impedance state. The signal at node a (hereinafter also referred to as signal a) depends on its original logic level.

For the intermediate stage 203:

transistors

543 and 545 become conductive, at which time tri-state gate 203 acts according to the signal at node a: when the signal at node a (signal a) is low (logic 0), the transistor 541 is on and the transistor 547 is off, so that node B is high (logic 1); when the signal a is high (logic 1), the transistor 541 is turned off and the transistor 547 is turned on, so that the node B is low (logic 0).

For the feedback stage 207: at this

point transistors

523 and 525 are turned off and tri-state gate 207 is turned off, assuming a high impedance state.

As such, according to the D flip-flop of the embodiments of the present disclosure, the potential of the floating node (e.g., node B) may be stably maintained, and power consumption of the D flip-flop may be reduced. Also, since the potential of the floating node can be maintained, the use of high threshold devices (e.g., high threshold transistors) can be avoided.

Here, those skilled in the art will appreciate that although the transistor devices in the D flip-flop are designed to have the same threshold value, the variation in the process of manufacturing may cause a certain deviation in the threshold value of the actually manufactured device. Generally, in this context, substantially the same threshold may mean within ± 20%, more preferably within ± 15%, more preferably within ± 10%, more preferably within ± 5% of the design or target threshold.

In addition, according to the D flip-flop of the embodiment of the disclosure, as few transistors as possible are adopted. In a computationally intensive processor (e.g., a processor for digital currency), there may be a large number of D flip-flops, so even a one transistor reduction in D flip-flops is significant for reducing chip area and power consumption.

Further, according to the D flip-flop of the embodiment of the present disclosure, since the potential of the floating node can be effectively maintained, even when operating at a low frequency (for example, in a standby or sleep state), malfunction is not caused. The D flip-flop according to the embodiment of the present disclosure may also operate at a higher frequency (e.g., in a normal operating state) to increase the processing speed, thereby providing flexibility for processor design and reducing power consumption.

According to the semi-static D flip-flop disclosed by the embodiment of the disclosure, compared with a traditional static D flip-flop, a main register is changed into a dynamic register, and a certain area and power consumption are saved under the condition of keeping the same speed. Compared with a dynamic D trigger, the slave register is added with one-stage tri-state gate feedback and is changed into a semi-static register, so that the slave register can work at a lower working frequency. In addition, the speed of the D flip-flop can be increased by using a part of the low threshold device.

Fig. 3A shows a schematic circuit diagram of a D flip-flop according to another embodiment of the present disclosure. The D flip-flop 300A shown in fig. 3A differs from the D flip-flop 200 shown in fig. 2 only in the intermediate stage. In the D flip-flop 300A, the tristate logic of the intermediate stage 303 is implemented as a series connection of an inverter and a transmission gate.

As shown in fig. 3A, the

CMOS transistors

541 and 547 constitute an inverter, and the

CMOS transistors

543 and 545 constitute a transfer gate. The input of the inverter is connected to the output of the input stage 201 (node a), the output of the inverter is connected to the input of the transmission gate (node E), and the output of the transmission gate is connected to the intermediate node (node B). Two control terminals of the transmission gate (i.e., gates of CMOS transistors 543 and 545) receive the clock signal CLKN and the clock signal CLKP, respectively. The clock signal CLKN and the clock signal CLKP are inverted, i.e., the clock signal CLKN and the clock signal CLKP are the opposite of each other.

The operation and logic level changes of the intermediate stage 303 are the same as the intermediate stage 203 shown in fig. 2, and therefore the operation and logic level changes described above with respect to the intermediate stage 203 may be equally applicable thereto. In addition, the remaining components of fig. 3A are the same as the corresponding components in fig. 2, and thus further detailed description thereof is omitted here.

Fig. 3B shows a schematic circuit diagram of a D flip-flop according to another embodiment of the present disclosure. The D flip-flop 300B shown in fig. 3B differs from the D flip-flop 300A shown in fig. 3A only in the feedback stage. In D flip-flop 300B, the tristate logic of feedback stage 307 is implemented as a series connection of an inverter and a transmission gate.

As shown in fig. 3B, the

CMOS transistors

521 and 527 constitute an inverter, and the

CMOS transistors

523 and 525 constitute a transfer gate. The input of the inverter is connected to the output node (Q) of the flip-flop_N) The output of the inverter is connected to the input of the transmission gate (node G). The output of the transmission gate is connected to an intermediate node (node B). Two control terminals of the transmission gate (i.e., gates of CMOS transistors 523 and 525) receive the clock signal CLKP and the clock signal CLKN, respectively. The operation and logic level changes of the feedback stage 307 are the same as the feedback stage 207 shown in fig. 2, and therefore the operation and logic level changes described above in relation to the feedback stage 207 may be equally applied thereto. In addition, the remaining components of fig. 3B are the same as the corresponding components in fig. 2, and thus further detailed description thereof is omitted here.

In the embodiment shown in FIG. 3B, the flip-flop output Q may be output using node G as one output_NThe inverse Q of (1).

Fig. 3C shows a schematic circuit diagram of a D flip-flop according to another embodiment of the present disclosure. The D flip-flop 300C shown in fig. 3C differs from the D flip-flop 300B shown in fig. 3B only in the input stage. In D flip-flop 300C, the tristate logic of input stage 301 is implemented as a series connection of an inverter and a transmission gate.

As shown in fig. 3C,

CMOS transistors

551 and 557 constitute an inverter, and

CMOS transistors

553 and 555 constitute a transfer gate. The input of the inverter is connected to the flip-flop input D and the output of the inverter is connected to the input of the transmission gate (node F). The output of the transmission gate is connected to the intermediate node (node a). Two control terminals of the transmission gate (i.e., gates of CMOS transistors 553 and 555) receive the clock signal CLKP and the clock signal CLKN, respectively. The operation and logic level variations of input stage 301 are the same as input stage 201 shown in fig. 2, and thus the operation and logic level variations described above with respect to input stage 201 may be equally applicable thereto. In addition, the remaining components of fig. 3C are the same as the corresponding components in fig. 2, and thus further detailed description thereof is omitted here.

In addition, one skilled in the art will readily appreciate that the different implementations of the input stage, the intermediate stage and the feedback stage in the embodiments of the present disclosure may be combined in any combination as appropriate. For example, one or more of the input stage, the intermediate stage and the feedback stage may be implemented as a tri-state gate, while another one or more may be implemented as a combination of an inverter and a transmission gate.

It should also be understood that although described in the above examples with a rising edge efficient embodiment, in other embodiments of the present disclosure, a falling edge efficient manner may be employed. In this case, the waveforms of the clock signals CLKN and CLKP will be inverted.

A D flip-flop according to an embodiment of the present disclosure is a semi-static flip-flop whose output stage, feedback stage, and intermediate node B constitute a latch, so that a potential or logic level at the intermediate node B can be statically maintained, while a potential of some nodes (e.g., node a) is not maintained or latched.

On the other hand, as previously described, in order to mitigate or avoid device leakage from affecting the voltage at a node (e.g., node B), the circuit device connected to that node needs to use a low leakage device. Low leakage devices are typically high threshold devices and are slower than low threshold devices, which also affects the speed of the D flip-flop. Also, the D flip-flop needs to operate at a higher frequency to prevent malfunction. While in certain states of the processor (e.g., sleep or idle states), the D flip-flops may operate at a relatively low frequency, in which case the prior art D flip-flops may experience functional errors. In contrast, the D flip-flop according to the embodiment of the present disclosure, because of its semi-static configuration, the threshold of the transistors therein can be configured to be substantially the same, avoiding the use of high threshold devices. Thereby, the speed of the D flip-flop can be provided and the normal operation can be made without a functional error even at a low frequency.

According to the present disclosure, a processor is also provided. FIG. 4 shows a schematic block diagram of a processor including a clock circuit and a D flip-flop according to one embodiment of the present disclosure. As shown in fig. 4, the processor 400 includes at least one D flip-flop 401. The D flip-flop may be a D flip-flop according to any embodiment of the present disclosure. The processor 400 may also include a clock circuit 403 for providing the required clock signal to each D flip-flop. As shown in fig. 4, the clock circuit 403 receives a clock signal CK (which may be a system clock or a clock signal received from the outside) and outputs different clock signals CLKN and CLKP. As previously described, in some embodiments, the clock signals CLKN and CLKP are opposite in phase.

FIG. 5 shows a schematic block diagram of a clock circuit according to one embodiment of the present disclosure. The clock circuit 500 includes a first inverter 551 and a second inverter 553 connected in series. The first inverter 551 receives a clock signal (e.g., a system clock) CK and outputs a first clock signal (e.g., a clock signal CLKN or CLKP), and the second inverter receives the first clock signal and outputs a second clock signal (e.g., a clock signal CLKP or CLKN). As such, the first clock signal and the second clock signal are inverted with respect to each other. The first clock signal and the second clock signal may be provided to one or more of the plurality of D flip-flops.

FIG. 6 shows a schematic block diagram of a processor including a clock circuit and a plurality of D flip-flops, according to one embodiment of the present disclosure. As shown in fig. 6, the processor 600 includes a plurality of D flip-flops 601 and a clock circuit 602 that provides a clock signal for the plurality of D flip-flops 601. The clock circuit 602 receives the clock CK and outputs clock signals CLKN and CLKP to each D flip-flop 601. The clock circuit 602 may be, for example, the clock circuit shown in fig. 4.

According to the present disclosure, there is also provided a computing device, which may comprise a processor according to any embodiment of the present disclosure. In some embodiments, the computing device may be a computing device for digital currency. The digital currency may be, for example, digital RMB, Bitty, Ether, Lett, and the like.

Those skilled in the art will appreciate that the boundaries between the operations (or steps) described in the above embodiments are merely illustrative. Multiple operations may be combined into a single operation, single operations may be distributed in additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any combination without departing from the spirit and scope of the present disclosure. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A D flip-flop, comprising:

an input stage for receiving a flip-flop input (D);

an output stage for outputting the output voltage of the power amplifier,for outputting flip-flop outputs (Q)_N）；

An intermediate stage for receiving the output of the input stage via an intermediate node (B) and providing an output to the output stage; and

a feedback stage receiving the flip-flop output and providing feedback to the intermediate node,

wherein the feedback stage has a logic high state, a logic low state, and a high impedance state,

wherein an output of the flip-flop is inverted with respect to an input of the flip-flop.

2. The D flip-flop of claim 1, wherein said feedback stage comprises a tri-state gate comprising:

first to fourth transistors connected in series in this order, wherein the first and second transistors are transistors of a first conductivity type, the third and fourth transistors are transistors of a second conductivity type, the second conductivity type being different from the first conductivity type,

a control terminal of one of the first and second transistors is connected to the flip-flop output, a control terminal of the other of the first and second transistors is connected to a first clock signal,

a control terminal of one of the third and fourth transistors is connected to the flip-flop output, a control terminal of the other of the third and fourth transistors is connected to a second clock signal, wherein the second clock signal is the inverse of the first clock signal,

a node at which the second and third transistors are connected to each other is connected to the intermediate node.

3. The D flip-flop of claim 1, wherein said feedback stage comprises a series connected inverter and transmission gate,

an input of the inverter is connected to the flip-flop output, an output of the inverter is connected to an input of the transmission gate, an output of the transmission gate is connected to the intermediate node,

the inverter includes a first transistor of a first conductivity type and a fourth transistor of a second conductivity type connected in series, the transmission gate includes a second transistor of the first conductivity type and a third transistor of a second conductivity type, which is different from the first conductivity type, connected in parallel,

two control terminals of the transmission gate respectively receive a first clock signal and a second clock signal, wherein the second clock signal is the inverse of the first clock signal.

4. The D flip-flop according to claim 2 or 3, wherein: the first conductivity type is a P-type, the second conductivity type is an N-type,

when the first clock signal changes from low to high and the second clock signal changes from high to low, the feedback stage turns off, thereby assuming a high impedance state;

the feedback stage provides feedback to the intermediate node according to the flip-flop output when the first clock signal changes from high to low and the second clock signal changes from low to high.

5. The D flip-flop according to claim 2 or 3, wherein said input stage comprises tri-state logic receiving said flip-flop input and said first and second clock signals and providing an output to said intermediate stage, said tri-state logic assuming a logic high state, a logic low state and a high impedance state depending on said flip-flop input and said first and second clock signals,

the input stage is configured to:

when the first clock signal changes from low to high and the second clock signal changes from high to low, the input stage is turned off, thereby assuming a high impedance state;

the input stage provides an output to the intermediate stage according to the flip-flop input when the first clock signal changes from high to low and the second clock signal changes from low to high.

6. The D flip-flop of claim 2, wherein the intermediate stage comprises tri-state logic receiving the output of the input stage and the first and second clock signals, the tri-state logic assuming a logic high state, a logic low state, and a high impedance state based on the output of the input stage and the first and second clock signals,

the intermediate stage is configured to:

the intermediate stage providing an output to the intermediate node according to the output of the input stage when the first clock signal changes from low to high and the second clock signal changes from high to low;

when the first clock signal changes from high to low and the second clock signal changes from low to high, the intermediate stage is turned off and assumes a high impedance state.

7. The D flip-flop of claim 3, wherein the intermediate stage comprises tri-state logic that receives the output of the input stage and the first and second clock signals, the tri-state logic assuming a logic high state, a logic low state, and a high impedance state based on the output of the input stage and the first and second clock signals,

the intermediate stage is configured to:

8. The D flip-flop of claim 5, wherein said intermediate stage comprises tri-state logic, said tri-state logic receiving an output of said input stage and said first and second clock signals, said tri-state logic assuming a logic high state, a logic low state and a high impedance state based on said output of said input stage and said first and second clock signals,

the intermediate stage is configured to:

9. The D flip-flop according to any one of claims 6 to 8, wherein

The tristate logic comprises an inverter and a transmission gate, the inverter receives the output of the input stage as an input, the output of the inverter is connected to one end of the transmission gate, the other end of the transmission gate is connected to the intermediate node, and the control ends of the transmission gate receive the first and second clock signals respectively.

10. The D flip-flop according to any one of claims 6 to 8, wherein

The tri-state logic comprises a tri-state gate comprising:

fifth to eighth transistors connected in series in this order, the fifth and sixth transistors being transistors of a first conductivity type, the seventh and eighth transistors being transistors of a second conductivity type,

a control terminal of one of the fifth and sixth transistors is connected to an output of the input stage, a control terminal of the other of the fifth and sixth transistors is connected to one of the first and second clock signals,

a control terminal of one of the seventh and eighth transistors is connected to an output of the input stage, a control terminal of the other of the seventh and eighth transistors is connected to the other of the first and second clock signals,

a node at which the sixth and seventh transistors are connected to each other is connected to the intermediate node.

11. The D flip-flop of claim 1, wherein the D flip-flop is a semi-static flip-flop, and wherein the output stage, the feedback stage, and the intermediate node comprise a latch.

12. The D flip-flop of claim 10, wherein said first conductivity type transistor is a PMOS transistor and said second conductivity type transistor is an NMOS transistor.

13. A processor, comprising:

at least one D flip-flop, the D flip-flop being the D flip-flop of any one of claims 1-12.

14. The processor of claim 13, wherein the at least one D flip-flop comprises a plurality of D flip-flops,

the processor also includes a clock circuit for providing a desired clock signal to each of the plurality of D flip-flops.

15. A computing device comprising a processor according to any of claims 13-14.

16. The computing device of claim 15, wherein the computing device is a computing device for digital currency.