CN114567292B

CN114567292B - Static latch and processor and computing device including same

Info

Publication number: CN114567292B
Application number: CN202210455592.0A
Authority: CN
Inventors: 田文博; 龚川; 范志军; 杨作兴; 郭海丰
Original assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Current assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Priority date: 2022-04-28
Filing date: 2022-04-28
Publication date: 2023-05-19
Anticipated expiration: 2042-04-28
Also published as: CN114567292A

Abstract

The present disclosure relates to static latches and processors and computing devices including static latches. There is provided a static latch comprising: an input stage for receiving a latch input (D); an output stage for outputting a latch output (Q); an intermediate node (B) disposed between an output of the input stage and an input of the output stage, wherein the output stage receives as input a signal at the intermediate node; and a feedback stage receiving the latch output and providing feedback to the intermediate node, wherein the feedback stage and input stage have a logic high state, a logic low state, and a high resistance state.

Description

Static latch and processor and computing device including same

Technical Field

The present disclosure relates to static latches and processors and computing devices including static latches.

Background

In recent years, digital money has received increasing attention. There is a need in the related art for improved processors and computing devices for digital currency.

Processors for digital currency require a large number of repeated logic computations during the operation, which requires a large number of latches for data storage. Thus, the performance of the latch will directly impact the performance of the processor, including chip area, power consumption, speed of operation, etc.

Compared with a static latch, the dynamic latch has the advantages that the circuit structure is greatly simplified due to the fact that a positive feedback circuit for keeping the working state is reduced, and therefore the chip area is reduced, and the power consumption is reduced. However, since there is a node in the dynamic latch that is potential floating (floating) for a portion of the time, the parasitic capacitance at that node needs to remain in the correct voltage state during that time.

To mitigate or avoid device leakage affecting the voltage at the node, the circuit devices connected to the node require the use of low leakage devices. The low leakage devices are typically high threshold devices and are slower than low threshold devices, which also affects the speed of the dynamic latch. At the same time, the dynamic latch needs to operate at a higher frequency to prevent functional errors. While in certain states of the processor (e.g., sleep or idle states), dynamic latches may operate at a relatively low frequency, in which case prior art dynamic latches may be subject to functional errors.

To address one or more of the above problems, the present invention provides a static latch and a processor and computing device including the same.

Disclosure of Invention

According to one aspect of the present disclosure, there is provided a static latch comprising: an input stage for receiving a latch input (D); an output stage for outputting a latch output (Q); an intermediate node (B) disposed between an output of the input stage and an input of the output stage, wherein the output stage receives as input a signal at the intermediate node; and a feedback stage receiving the latch output and providing feedback to the intermediate node, wherein the feedback stage and input stage have a logic high state, a logic low state, and a high resistance state.

In some embodiments, the feedback stage comprises a tri-state gate comprising: first to fourth transistors connected in series in order, the first and second transistors being transistors of a first conductivity type, the third and fourth transistors being transistors of a second conductivity type, the second conductivity type being different from the first conductivity type, a control terminal of one of the first and second transistors being connected to the latch output, a control terminal of the other of the first and second transistors being connected to a first clock signal, a control terminal of the one of the third and fourth transistors being connected to the latch output, a control terminal of the other of the third and fourth transistors being connected to a second clock signal, wherein the second clock signal is an inverse of the first clock signal, a node to which the second and third transistors are connected to each other being connected to the intermediate node.

In some embodiments, the feedback stage comprises an inverter and a transmission gate connected in series, an input of the inverter being connected to the latch output, an output of the inverter being connected to an input of the transmission gate, an output of the transmission gate being connected to the intermediate node, two control terminals of the transmission gate receiving a first clock signal and a second clock signal, respectively, wherein the second clock signal is an inverse of the first clock signal.

In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type. When the first clock signal is high and the second clock signal is low, the feedback stage is turned off, thereby assuming a high resistance state. The feedback stage provides feedback to the intermediate node according to the latch output when the first clock signal is low and the second clock signal is high.

In some embodiments, the input stage is tristate logic receiving the latch input and the first and second clock signals, the tristate logic assuming a logic high state, a logic low state and a high resistance state in accordance with the input and the first and second clock signals.

In some embodiments, the tristate logic comprises an inverter and a transmission gate connected in series, the inverter receiving the latch input, an output of the inverter being connected to one end of the transmission gate, the other end of the transmission gate being connected to the intermediate node, a control end of the transmission gate receiving the first and second clock signals, respectively.

In some embodiments, the tristate logic comprises a tristate gate comprising: fifth to eighth transistors connected in series in order, the fifth and sixth transistors being transistors of a first conductivity type, the seventh and eighth transistors being transistors of a second conductivity type, a control terminal of one of the fifth and sixth transistors being connected to the latch input, a control terminal of the other of the fifth and sixth transistors being connected to the second clock signal, a control terminal of the one of the seventh and eighth transistors being connected to the latch input, a control terminal of the other of the seventh and eighth transistors being connected to the first clock signal, a node of the sixth and seventh transistors being connected to each other being connected to the intermediate node.

In some embodiments, the transistor of the first conductivity type is a PMOS transistor and the transistor of the second conductivity type is an NMOS transistor. The input stage provides an output to the intermediate node according to the latch input when the first clock signal is high and the second clock signal is low. When the first clock signal is low and the second clock signal is high, the input stage is turned off, thereby assuming a high impedance state.

In some embodiments, the threshold values of the transistors in the static latch are substantially the same.

According to one aspect of the present disclosure, there is provided a processor comprising: at least one static latch, the static latch being a static latch according to any embodiment of the present disclosure.

In some embodiments, the at least one static latch comprises a plurality of static latches; and clock circuitry for providing a desired clock signal to each of the plurality of static latches.

In some embodiments, the clock circuit includes a first inverter and a second inverter in series, the first inverter receiving a clock signal and outputting a first clock signal, the second inverter receiving the first clock signal and outputting a second clock signal, the first clock signal and the second clock signal being provided to each of the plurality of static latches.

According to some aspects of the present disclosure, there is provided a computing device comprising a processor according to any embodiment of the present disclosure.

In some embodiments, the computing device is a computing device for digital currency.

The static latch according to the embodiment of the disclosure can stably maintain the potential of the floating node, reduce the power consumption of the static latch and reduce the complexity of the preparation process. Static latches according to embodiments of the present disclosure may operate at lower frequencies as well as higher frequencies, thereby providing flexibility in processor design and reducing power consumption.

Processors and computing devices according to the present disclosure may be used for related computation of digital money.

Other features of the present disclosure and its advantages will become apparent from the following detailed description of exemplary embodiments of the disclosure, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The disclosure may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 illustrates a schematic block diagram of a static latch according to one embodiment of the present disclosure;

FIG. 2 illustrates a circuit diagram of a static latch according to one embodiment of the present disclosure;

FIG. 3A shows a schematic circuit diagram of a static latch according to another embodiment of the present disclosure;

FIG. 3B shows a schematic circuit diagram of a static latch according to another embodiment of the present disclosure;

FIG. 4 shows a schematic block diagram of a processor including a clock circuit and a static latch according to one embodiment of the present disclosure;

FIG. 5 shows a schematic block diagram of a clock circuit according to one embodiment of the present disclosure;

FIG. 6 shows a schematic block diagram of a processor including a clock circuit and a plurality of static latches, according to one embodiment of the present disclosure; and

fig. 7 shows a timing diagram of schematic signal waveforms of a static latch according to one embodiment of the present disclosure.

Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same parts or parts having the same functions, and a repetitive description thereof may be omitted. In this specification, like reference numerals and letters are used to designate like items, and thus once an item is defined in one drawing, no further discussion thereof is necessary in subsequent drawings.

For ease of understanding, the positions, dimensions, ranges, etc. of the respective structures shown in the drawings and the like may not represent actual positions, dimensions, ranges, etc. Accordingly, the disclosed invention is not limited to the disclosed positions, dimensions, ranges, etc. as illustrated in the drawings.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. Note that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise. In addition, techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate.

It should be appreciated that the following description of at least one exemplary embodiment is merely illustrative, and is not intended to limit the present disclosure, application or uses thereof. It should also be appreciated that any implementation illustratively described herein is not necessarily indicative of a preferred or advantageous embodiment over other implementations. The disclosure is not to be limited by any expressed or implied theory presented in the preceding technical field, background, brief summary or the detailed description.

In this context, "tri-state logic" means a logic circuit whose output assumes three states according to inputs and control signals: a logic high state, a logic low state, and a high resistance state. The control signal may be, for example, a clock signal.

Herein, "tri-state gate" means a logic gate (or referred to as a logic gate circuit) whose output can achieve the "minimum level" of the three states (logic high state, logic low state, and high resistance state). Here, "a logic gate of a minimum hierarchy" means that an independent logic gate or a logic cell, which is a part thereof, cannot be separated from the logic gate (tri-state gate).

In addition, certain terminology may be used in the following description for the purpose of reference only and is therefore not intended to be limiting. For example, the terms "first," "second," and other such numerical terms referring to structures or elements do not imply a sequence or order unless clearly indicated by the context.

It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components, and/or groups thereof.

FIG. 1 illustrates a schematic block diagram of a static latch according to one embodiment of the present disclosure. As shown IN fig. 1, a static latch 100 according to an embodiment of the present disclosure includes an input stage 103 for receiving an Input (IN), and an output stage 105 for outputting a latch Output (OUT).

The static latch 100 also has an intermediate node (B) disposed between the output of the input stage and the input of the output stage. In operation, the potential of the intermediate node B is floating.

In some embodiments, as shown in fig. 1, the intermediate node B may be directly connected to the output of the input stage.

The input of the output stage 105 receives a signal according to the potential of the intermediate node. Preferably, as shown in the embodiment of fig. 1, the input of the output stage 105 is directly connected to the intermediate node B.

The static latch 100 further comprises a feedback stage 107, the feedback stage 107 receiving the latch output OUT and providing feedback to the intermediate node B. In accordance with an embodiment of the present disclosure, feedback stage 107 has a logic high state, a logic low state, and a high resistance state.

Further, one or more of the components of the static latch 100 may receive a corresponding clock signal. As shown in fig. 1, the input stage 103 and the feedback stage 107 each receive a respective clock. Here, it should be understood that the clock CKs are merely exemplary and do not mean that the input stage 103, the feedback stage 107, and other components (if any) etc. all receive the same clock signal. Furthermore, although in the embodiment shown in fig. 1, the output stage 105 is shown as not receiving a clock signal, the present disclosure is not limited thereto.

Fig. 2 illustrates a circuit diagram of a static latch according to one embodiment of the present disclosure. As shown in fig. 2, a static latch 200 according to an embodiment of the present disclosure includes an input stage 203, an output stage 205, an intermediate node B, and a feedback stage 207. An intermediate node B is arranged between the output of the input stage 203 and the input of the output stage 205. In operation, the potential at the intermediate node B is floating.

Input stage 203 receives input D and provides an output to intermediate node B. Here, input stage 203 receives input D (also referred to as a latch input) and provides an output to intermediate node B. The input stage 203 also receives clock signals CLKP and CLKN. Preferably, the input stage 203 is implemented as tri-state logic that assumes a logic high state, a logic low state, and a high resistance state depending on the input D and the first (CLKP or CLKN) and second clock signals (CLKN or CLKP).

In a preferred embodiment, as shown in fig. 2, the input stage 203 is implemented as a CMOS tri-state gate comprising four transistors. The CMOS tri-state gate includes:

transistors

531, 533, 535, and 537 are sequentially connected in series, wherein

transistors

531 and 533 are PMOS transistors and

transistors

535 and 537 are NMOS transistors.

Transistors

531 and 533 are connected in series with each other. One terminal (here, source) of the transistor 533 is connected to one terminal (here, drain) of the transistor 531. A control terminal (gate) of one of the

transistors

531 and 533 is connected to the latch input D, and a control terminal (gate) of the other of the

transistors

531 and 533 is connected to the clock signal CLKN. Preferably, as shown in fig. 2, the gate of transistor 531 is connected to input D and the gate of transistor 533 is connected to clock signal CLKN. One end (here, a source) of the transistor 531 is connected to a power supply voltage VDD.

The drain of PMOS transistor 533 and the drain of NMOS transistor 535 are connected to each other and to intermediate

node B. Transistors

535 and 537 are in series with each other. One terminal (here, source) of the transistor 535 is connected to one terminal (here, drain) of the transistor 537. The control terminal (gate) of one of the

transistors

535 and 537 is connected to the input D, and the control terminal (gate) of the other of the

transistors

535 and 537 is connected to the clock signal CLKP. Preferably, as shown in fig. 2, the gate of transistor 537 is connected to input D and the gate of transistor 535 is connected to clock signal CLKP. The other end (here, the source) of the transistor 537 is connected to the ground GND.

Those skilled in the art will readily appreciate that there are many implementations of tri-state logic for implementing input stage 203 and that it is not limited to the manner shown in fig. 2. For example, the tri-state logic may also be implemented to include inverters and transmission gates, as will be described later with reference to fig. 3A-3B. In addition, in other embodiments, the signals received by the gates of

transistors

531 and 533 may be exchanged, and correspondingly, the signals received by the gates of

transistors

535 and 537 may be exchanged. That is, it may be configured that the gates of the

transistors

531 and 537 are connected to the clock signals CLKN and CLKP, respectively, and the gates of the

transistors

533 and 535 are connected to the input D.

The output stage 205 receives as input the signal (voltage) at node B and its output as latch output Q. In the present embodiment, the output stage 205 is implemented as an inverter including

CMOS transistors

511 and 513 connected in series with each other. Transistor 511 is a PMOS transistor and transistor 513 is an NMOS transistor. The control terminal (gate) of the transistor 511 is connected to the node B, its source is connected to the power supply voltage VDD, its drain is connected to the drain of the transistor 513, and to the output Q. A gate of the transistor 513 is connected to the node B, and a source thereof is connected to the ground GND. Herein, the output Q may be used to indicate an output signal or an output terminal, depending on the context. Similarly, input D may be used to indicate an input signal, or may be used to indicate an input terminal.

The feedback stage 207 receives the latch output Q as an input and provides feedback to the intermediate node B. Here, the feedback stage 207 is implemented as tri-state logic. In the embodiment shown in fig. 2, the feedback stage 207 is implemented as a tri-state gate having a logic high state, a logic low state, and a high resistance state.

Specifically, as shown in fig. 2, the tri-state gate of the feedback stage 207 is implemented by a CMOS transistor. The tri-state gate includes: transistors 521-527 are serially connected in series. The

transistors

521, 523, 525, and 527 are referred to herein as first to fourth transistors, respectively, and the

aforementioned transistors

531, 533, 535, and 537 are referred to herein as fifth to eighth transistors, respectively. The first and

second transistors

521 and 523 are PMOS transistors, and the third and

fourth transistors

525 and 527 are NMOS transistors.

The first and

second transistors

521 and 523 are connected in series with each other. One terminal (here, the drain) of the transistor 521 is connected to one terminal (here, the source) of the transistor 523. A control terminal (gate) of one of the first and

second transistors

521 and 523 is connected to the latch output Q, and a control terminal of the other of the first and

second transistors

521 and 523 is connected to the clock signal CLKP. Here, in the embodiment shown in fig. 2, the gate of the first transistor 521 is connected to the latch output Q, and the gate of the second transistor 523 is connected to the clock signal CLKP. The other end (here, the source) of the transistor 521 is connected to the power supply voltage VDD.

The drain of PMOS transistor 523 and the drain of NMOS transistor 525 are connected to each other and to intermediate node B. The third and

fourth transistors

525 and 527 are connected in series with each other. One terminal (here, source) of the transistor 525 is connected to one terminal (here, drain) of the transistor 527. A control terminal (gate) of one of the third and

fourth transistors

525 and 527 is connected to the latch output Q, and a control terminal (gate) of the other of the third and

fourth transistors

525 and 527 is connected to the clock signal CLKN. In the embodiment shown in fig. 2, the gate of the fourth transistor 527 is connected to the latch output Q and the gate of the third transistor 525 is connected to the clock signal CLKN. The clock signal CLKN is the inverse of the clock signal CLKP. The other end (here, the source) of the transistor 527 is connected to the ground GND.

The node at which the second and

third transistors

523 and 525 are connected to each other is connected to the intermediate node B. Here, the drain of the transistor 523 is connected to the drain of the transistor 525 and to the intermediate node B.

It should be appreciated that although in the embodiment shown in fig. 2, feedback stage 207 is implemented as a tri-state gate, in other embodiments feedback stage 207 may be implemented in a variety of other ways.

The timing of the static latch according to an embodiment of the present disclosure is described below in conjunction with fig. 7 and 2. Fig. 7 shows a timing diagram of schematic signal waveforms for a static latch according to an embodiment of the present disclosure. The clock signals CLKN and CLKP may be obtained from the clock signal CK (to be described in more detail later) in a manner such as that shown in fig. 5. The clock signal CLKP and the clock signal CLKN are inverted from each other irrespective of the delay, one of which may substantially coincide with the clock signal CK. For example, here, the clock signal CLKP substantially coincides with the clock signal CK, and the clock signal CLKN is the inverse of the clock signal CLKP (or the clock signal CK).

The partial clocks preceding two complete clock cycles T1 and T2, T1 and at least part of cycle T3 are shown in fig. 7. As shown in fig. 7, immediately before the start time T1 of the period of T1: the clock signal CK is low, and correspondingly the clock signal CLKN is high and the clock signal CLKP is low; input D is high;

transistors

533 and 535 are off and tri-state gate 203 is off; b is high and output Q is low. While

transistors

525 and 523 are on, tri-state gate 207 is on, thereby maintaining the signal at node B (hereinafter signal B) high.

As shown in fig. 7, at time t1, the clock signal CK changes from logic low to logic high. Accordingly, the clock signal CLKP goes from low to high and the clock signal CLKN goes from high to low. At this point, input D is high.

Since clock signal CLKN toggles low, clock signal CLKP toggles high, and input D is high, so that

transistors

533 and 535 are turned on, and signal B goes from high to low. The output stage 205 is an inverter and therefore its output signal Q goes from low to high. On the other hand, since clock signal CLKN is low and clock signal CLKP is high, transistor 523 and transistor 525 in tri-state gate 207 are also turned off, so that tri-state gate 207 is turned off in a high-impedance state. B is low.

At time T2 within the first period T1 of clock CK, clock signals CLKN and CLKP flip high and low, respectively, and Q is high, so that

transistors

525 and 523 in tri-state gate 207 are turned on, thereby maintaining signal B low. Thus, the potential at the intermediate node B is maintained at the desired logic low potential.

In the period of t2-t3, clock CK is low, and accordingly, clock signal CLKP is low and clock signal CLKN is high. And output Q is high. Thus, feedback stage 207 turns on, keeping the signal at node B low.

Thereafter, immediately before the period T2, the D signal goes from high to low. Before time t3, the clock signal CK is low, and correspondingly the clock signal CLKN is high and the clock signal CLKP is low, similar to before time t 1. At this point, input D is low.

Transistors

533 and 535 are off and tri-state gate 203 is off; b is low and output Q is high, and

transistors

525 and 523 are turned on, so that signal B remains low.

In period T2, at time T3, clock signal CLKP goes high again and clock signal CLKN goes low again. At this point, signal D is low. Thus, in input stage 203,

transistors

535 and 533 are turned on, so that signal B toggles high. Accordingly, the transistor output Q toggles low.

In the feedback stage 207, however, the

transistors

523 and 525 in the tri-state gate 207 are turned off and the tri-state gate is turned off in a high impedance state as the clock signals CLKP and CLKN flip high and low, respectively. B remains high.

Similarly, during period T2, signals B and Q maintain their logic levels. At time t4, clock signals CLKN and CLKP flip accordingly, while signals B and Q maintain their logic levels. At this point, clock signals CLKN and CLKP flip high and low, respectively, so that

transistors

525 and 523 in tri-state gate 207 are on and Q is low, maintaining signal B high. In this manner, the potential at the intermediate node B is maintained at the desired logic high potential.

The D signal goes from low to high before period T3. The situation at T5 is substantially the same as at time T1, while the situation at time T6 in period T3 is substantially the same as at time T2; and thus will not be described in detail herein.

As such, according to the static latch of the embodiment of the present disclosure, the potential of the floating node (e.g., node B) can be stably maintained, and the power consumption of the static latch can be reduced. Moreover, since the potential of the floating node may be maintained, the use of high threshold devices (e.g., high threshold transistors) may be avoided, and thus the transistors in the static latch may be configured to have substantially the same threshold. Thus, the complexity of the preparation process is reduced.

Here, those skilled in the art will appreciate that although transistor devices in a static latch are designed to have the same based threshold, variations in process fabrication may result in some deviation in the threshold of the device actually fabricated. Generally, substantially the same threshold value may be expressed herein as being within ±20% of the design threshold value or the target threshold value, more preferably within ±15%, more preferably within ±10%, more preferably within ±5%.

In addition, static latches according to embodiments of the present disclosure may employ as few transistors as possible. In computationally intensive processors (e.g., processors for digital money), there may be a large number of static latches, so even one transistor reduction in static latches is significant for reducing both chip area and power consumption.

Further, according to the static latch of the embodiment of the present disclosure, since the potential of the floating node can be effectively maintained, malfunction is not caused even when operating at a low frequency. Static latches according to embodiments of the present disclosure may also operate at higher frequencies, thereby providing flexibility in processor design and reduced power consumption.

It should also be appreciated that while the above examples have been described in terms of active high level embodiments, in other embodiments of the present disclosure, active low level implementations may be employed. In this case, the waveforms of the clock signals CLKN and CLKP will be inverted.

Fig. 3A shows a schematic circuit diagram of a static latch according to another embodiment of the present disclosure. The static latch 300A shown in fig. 3A differs from the static latch 200 shown in fig. 2 only in the input stage. In static latch 300A, the tri-state logic of input stage 303 is implemented as a series of inverters and transmission gates.

As shown in fig. 3A,

CMOS transistors

531A and 535A constitute inverters, and CMOS transistors 533A and 537A constitute transmission gates. The input of the inverter is connected to input D, the output of the inverter is connected to the input of the transmission gate (node E), and the output of the transmission gate is connected to the intermediate node (node B). The two control terminals of the transmission gate (i.e., the gates of CMOS transistors 533A and 537A) receive the clock signal CLKN and the clock signal CLKP, respectively. The clock signal CLKN and the clock signal CLKP are inverted, that is, the clock signal CLKN and the clock signal CLKP are inverted with respect to each other.

The operation and logic level variation of input stage 303 is the same as input stage 203 shown in fig. 2, and thus the operation and logic level variation described above with respect to input stage 203 may be equally applicable thereto. In addition, the remaining components of fig. 3A are the same as the corresponding components in fig. 2, and thus a further detailed description thereof is omitted here.

Fig. 3B shows a schematic circuit diagram of a static latch according to another embodiment of the present disclosure. The static latch 300B shown in fig. 3B differs from the static latch 300A shown in fig. 3A only in the feedback stage. In static latch 300B, the tri-state logic of feedback stage 307 is implemented as a series of an inverter and a transmission gate.

As shown in fig. 3B,

CMOS transistors

521A and 527A constitute inverters, and CMOS transistors 523A and 525A constitute transmission gates. The input of the inverter is connected to the latch output node (Q) and the output of the inverter is connected to the input of the transmission gate (node F). The output of the transmission gate is connected to an intermediate node (node B). The two control terminals of the transmission gate (i.e., the gates of CMOS transistors 523A and 525A) receive the clock signal CLKP and the clock signal CLKN, respectively.

In the embodiment shown in fig. 3B, the inverse QN of latch output Q may also be output using node F as an output.

In addition, one skilled in the art will readily appreciate that the different implementations of the input and feedback stages in the disclosed embodiments may be arbitrarily combined, as appropriate. For example, one or more of the input stage and the feedback stage may be implemented as a tri-state gate or as a combination of an inverter and a transmission gate.

The output stage, feedback stage, and intermediate node B of a static latch according to embodiments of the present disclosure constitute a latch, thereby enabling static maintenance of the potential or logic level at the node B.

On the other hand, as described above, in order to mitigate or avoid device leakage affecting the voltage of a node (e.g., node B), a circuit device connected to the node needs to use a low leakage device. The low leakage devices are typically high threshold devices and are slower than low threshold devices, which also affects the speed of the dynamic latch. At the same time, the dynamic latch needs to operate at a higher frequency to prevent functional errors. While in certain states of the processor (e.g., sleep or idle states), dynamic latches may operate at a relatively low frequency, in which case prior art dynamic latches may be subject to functional errors. While the threshold of the transistors in a static latch according to embodiments of the present disclosure may be configured to be substantially the same, the use of high threshold devices is avoided. Thereby, the speed of the latch can be provided and normal operation can be made without occurrence of functional errors even at a low frequency.

According to the present disclosure, there is also provided a processor. Fig. 4 shows a schematic block diagram of a processor including a clock circuit and a static latch according to one embodiment of the present disclosure. As shown in fig. 4, the processor 400 includes at least one static latch 401. The static latch may be a static latch according to any embodiment of the present disclosure. The processor 400 may also include a clock circuit 403 for providing the required clock signals to each of the static latches. As shown in fig. 4, the clock circuit 403 receives a clock signal CK (which may be a system clock or a clock signal received from the outside) and outputs different clock signals CLKN and CLKP. As previously described, in some embodiments, the clock signals CLKN and CLKP are opposite in phase.

Fig. 5 shows a schematic block diagram of a clock circuit according to one embodiment of the present disclosure. The clock circuit 500 includes a first inverter 551 and a second inverter 553 connected in series. The first inverter 551 receives a clock signal (e.g., a system clock) CK and outputs a first clock signal (e.g., a clock signal CLKN or CLKP), and the second inverter receives the first clock signal and outputs a second clock signal (e.g., a clock signal CLKP or CLKN). In this way, the first clock signal and the second clock signal are inverted from each other. The first clock signal and the second clock signal may be provided to one or more of the plurality of static latches.

Fig. 6 shows a schematic block diagram of a processor including a clock circuit and a plurality of static latches, according to one embodiment of the present disclosure. As shown in fig. 6, a processor 600 includes a plurality of static latches 601 and a clock circuit 602 that provides a clock signal to the plurality of static latches 601. The clock circuit 602 receives the clock 602 and outputs clock signals CLKN and CLKP to each of the static latches 601. The clock circuit 602 may be, for example, a clock circuit as shown in fig. 4.

In accordance with the present disclosure, a computing device is also provided, which may include a processor in accordance with any embodiment of the present disclosure. In some embodiments, the computing device may be a computing device for digital currency. The digital currency may be, for example, digital RMB or other digital currency, and the like.

Those skilled in the art will recognize that the boundaries between the operations (or steps) described in the above embodiments are merely illustrative. The operations may be combined into a single operation, the single operation may be distributed among additional operations, and the operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in other various embodiments. However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The embodiments disclosed herein may be combined in any desired manner without departing from the spirit and scope of the present disclosure. Those skilled in the art will also appreciate that various modifications might be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A computing device for digital money comprising at least one static latch, the static latch comprising:

an input stage for receiving a latch input (D);

an output stage for outputting a latch output (Q);

an intermediate node (B) disposed between an output of the input stage and an input of the output stage, wherein in operation a potential at the intermediate node is floating, and wherein the output stage receives as an input a signal at the intermediate node; and

a feedback stage receiving the latch output and providing feedback to the intermediate node,

wherein the feedback stage and the input stage have a logic high state, a logic low state and a high impedance state,

wherein in the static latch, the potential at the intermediate node can be maintained such that the static latch can use no high threshold transistor as a transistor connected to the intermediate node, and the static latch is configured such that the threshold of the transistor in the static latch connected to the intermediate node is substantially the same as the threshold of the other transistors in the static latch, and

wherein the static latch is operable in an operational state at a first frequency and in a sleep or idle state at a second frequency lower than the first frequency without a functional error, the first and second frequencies being configured such that a dynamic latch is more prone to a functional error at the second frequency than at the first frequency, the dynamic latch having no feedback stage than the static latch.

2. The computing device of claim 1, wherein the feedback stage comprises a tri-state gate comprising:

first to fourth transistors connected in series in order, wherein the first and second transistors are transistors of a first conductivity type, the third and fourth transistors are transistors of a second conductivity type, the second conductivity type being different from the first conductivity type,

a control terminal of one of the first and second transistors is connected to the latch output, a control terminal of the other of the first and second transistors is connected to a first clock signal,

a control terminal of one of the third and fourth transistors is connected to the latch output, a control terminal of the other of the third and fourth transistors is connected to a second clock signal, wherein the second clock signal is an inverse of the first clock signal,

a node at which the second transistor and the third transistor are connected to each other is connected to the intermediate node.

3. The computing device of claim 1, wherein the feedback stage comprises an inverter and a transmission gate connected in series,

an input of the inverter is connected to the latch output, an output of the inverter is connected to an input of the transmission gate, an output of the transmission gate is connected to the intermediate node,

the two control terminals of the transmission gate receive a first clock signal and a second clock signal, respectively, wherein the second clock signal is the inverse of the first clock signal.

4. The computing device of any of claims 2-3, wherein:

the first conductivity type is P-type, the second conductivity type is N-type,

when the first clock signal is high and the second clock signal is low, the feedback stage is turned off, thereby exhibiting a high resistance state;

the feedback stage provides feedback to the intermediate node according to the latch output when the first clock signal is low and the second clock signal is high.

5. The computing device of any of claims 2-3, wherein the input stage is tri-state logic that receives the latch input and the first and second clock signals, the tri-state logic assuming a logic high state, a logic low state, and a high impedance state according to the latch input and the first and second clock signals.

6. The computing device of claim 5, wherein

The tristate logic comprises an inverter and a transmission gate connected in series, the inverter receiving the latch input, the output of the inverter being connected to one end of the transmission gate, the other end of the transmission gate being connected to the intermediate node, the control end of the transmission gate receiving the first clock signal and the second clock signal, respectively.

7. The computing device of claim 4, wherein

The input stage includes a tri-state gate, the tri-state gate including:

fifth to eighth transistors connected in series in order, wherein the fifth transistor and the sixth transistor are transistors of a first conductivity type, the seventh transistor and the eighth transistor are transistors of a second conductivity type,

a control terminal of one of the fifth and sixth transistors is connected to the latch input, a control terminal of the other of the fifth and sixth transistors is connected to the second clock signal,

a control terminal of one of the seventh and eighth transistors is connected to the latch input, a control terminal of the other of the seventh and eighth transistors is connected to the first clock signal,

a node at which the sixth transistor and the seventh transistor are connected to each other is connected to the intermediate node.

8. The computing device of claim 7, wherein:

when the first clock signal is high and the second clock signal is low, the input stage provides an output to the intermediate node according to the latch input;

when the first clock signal is low and the second clock signal is high, the input stage is turned off, thereby assuming a high impedance state.

9. The computing device of claim 1, comprising a processor,

the at least one static latch is included in the processor.

10. The computing device of claim 9, wherein the at least one static latch comprises a plurality of static latches; and

a clock circuit for providing a desired clock signal to each of the plurality of static latches.

11. The computing device of claim 10, wherein the clock circuit comprises a first inverter and a second inverter in series, the first inverter receiving a clock signal and outputting a first clock signal, the second inverter receiving the first clock signal and outputting a second clock signal,

the first clock signal and the second clock signal are provided to each of the plurality of static latches.