CN106788341B - Asynchronous reset D trigger resisting single event upset - Google Patents
Asynchronous reset D trigger resisting single event upset Download PDFInfo
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- CN106788341B CN106788341B CN201710020136.2A CN201710020136A CN106788341B CN 106788341 B CN106788341 B CN 106788341B CN 201710020136 A CN201710020136 A CN 201710020136A CN 106788341 B CN106788341 B CN 106788341B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
Abstract
The invention is suitable for the technical field of D triggers, and provides a single event upset resistanceThe D flip-flop is asynchronously reset. The D flip-flop includes: the dual-mode redundancy circuit comprises a clock signal input circuit, a reset signal input circuit, a master latch buffer circuit, a slave latch buffer circuit, a master latch and a slave latch, wherein the master latch and the slave latch are dual-mode redundancy reinforced latches. Compared with the prior art, the invention improves the single event upset resistance of the asynchronous reset D trigger by adding the buffer circuit in front of the master latch and the slave latch, and performs dual-mode redundancy reinforcement on the master latch and the slave latch, namely the master latch and the slave latch are separated into the mutually redundant C2The pull-up PMOS tube and the pull-down NMOS tube in the MOS circuit avoid a feedback loop possibly caused by a single-event transient pulse in the slave latch from affecting C in the master latch circuit and the slave latch circuit2The MOS circuit is improved, the control of a clock signal to the circuit is realized through a CMOS transmission gate, and the single event upset resistance of the asynchronous reset D trigger is further improved.
Description
Technical Field
The invention belongs to the technical field of D triggers, and particularly relates to an asynchronous reset D trigger resistant to single event upset.
Background
After the combination circuit in the integrated circuit is bombarded by the high-energy particles, transient electric pulses can be generated, the effect is called single-particle transient effect, the higher the value of L ET (linear energy transfer) of the single-particle bombarded integrated circuit is, the more easily the electric pulses are collected by the time sequence circuit, if the state of the time sequence circuit is falsely overturned, or the transient electric pulses generated by the single-particle transient effect are falsely collected by the time sequence circuit, the more seriously the operation of the integrated circuit is unstable and even errors are generated, which is particularly serious in the fields of aerospace and military, therefore, the integrated circuit is reinforced so as to reduce the single-particle upset effect and the single-particle transient effect.
The D flip-flop is one of the most used sequential cell structures in an integrated circuit, and the resistance to single event upset determines the single event resistance of the whole integrated circuit. In some integrated circuits, it is desirable that the state of the D flip-flop be controllable, such as to force the D flip-flop to enter a low level. The asynchronous reset signal input end and the asynchronous reset circuit are added on the basis of the structure of the existing D trigger, the asynchronous reset structure of the D trigger can be realized, the asynchronous reset function of the D trigger can be controlled by the asynchronous reset signal, but the asynchronous reset D trigger has poor single event upset resistance and is not suitable for being applied to high-reliability integrated circuit chips.
Disclosure of Invention
The embodiment of the invention provides a single event upset resistant asynchronous reset D trigger, aiming at solving the problem that the asynchronous reset D trigger in the prior art is not high in single event upset resistance.
The embodiment of the invention provides a single event upset resistant asynchronous reset D trigger, which comprises:
the dual-mode redundancy circuit comprises a clock signal input circuit, a reset signal input circuit, a master latch buffer circuit, a slave latch buffer circuit, a master latch and a slave latch, wherein the master latch and the slave latch are dual-mode redundancy reinforced latches;
the asynchronous reset D trigger is provided with three input ends and two output ends, wherein the three input ends are a clock signal input end C L K, a reset signal input end R and a data signal input end D respectively, and the two output ends are a first output end Q and a second output end QN respectively;
the clock signal input circuit is respectively connected with the clock signal input end C L K, the reset signal input circuit, the master latch and the slave latch;
the reset signal input circuit is also respectively connected with the reset signal input end R, the master latch and the slave latch;
the main latch buffer circuit is respectively connected with the data signal input end D and the main latch;
the slave latch buffer circuit is respectively connected with the master latch and the slave latch;
the slave latch is further connected to the first output Q and the second output QN.
Compared with the prior art, the embodiment of the invention has the advantages that the buffering circuit is added in front of the master latch and the slave latch, the single event upset resistance of the asynchronous reset D trigger is improved, and dual-mode redundancy reinforcement is carried out on the master latch and the slave latch, namely the master latch and the slave latch are separated into the mutually redundant C2The pull-up PMOS tube and the pull-down NMOS tube in the MOS circuit avoid a feedback loop possibly caused by a single-event transient pulse in the slave latch from affecting C in the master latch circuit and the slave latch circuit2The MOS circuit is improved, the control of a clock signal to the circuit is realized through a CMOS transmission gate, and the single event upset resistance of the asynchronous reset D trigger is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic circuit diagram of a C-cell circuit based on a DICE structure in the prior art;
fig. 2 is a schematic structural diagram of an asynchronous reset D flip-flop resisting single event upset according to a first embodiment of the present invention;
fig. 3 is a schematic circuit structure diagram of a clock signal input circuit in the asynchronous reset D flip-flop resisting single event upset according to the first embodiment of the present invention;
fig. 4 is a schematic circuit structure diagram of a reset signal input circuit in the asynchronous reset D flip-flop resistant to single event upset according to the first embodiment of the present invention;
fig. 5 is a schematic circuit structure diagram of a master latch buffer circuit in an asynchronous reset D flip-flop with resistance to single event upset according to a first embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a master latch in the asynchronous reset D flip-flop with single event upset resistance according to the first embodiment of the present invention;
fig. 7 is a schematic circuit structure diagram of a slave latch buffer circuit in an asynchronous reset D flip-flop resistant to single event upset according to a first embodiment of the present invention;
fig. 8 is a schematic circuit diagram of a slave latch in an asynchronous reset D flip-flop resistant to single event upset according to a first embodiment of the present invention.
Detailed Description
In order to make the objects, features and advantages of the embodiments of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic circuit diagram of a C-cell circuit based on a DICE structure, the C-cell circuit based on the DICE structure includes:
the circuit comprises a first signal input end IN1, a second signal input end IN2, a signal output end OUT, a P-channel MOS tube MP1, a P-channel MOS tube MP2, an N-channel MOS tube MN1 and an N-channel MOS tube MN 2. The substrates of MP1 and MP2 are connected to power VDD (not shown in the figure), and the substrates of MN1 and MN2 are connected to ground (not shown in the figure).
Wherein, the gate of MP1 is connected to the first signal input terminal IN1, the source is connected to the power VDD, and the drain is connected to the source of MP 2; the gate of MP2 is connected to the second signal input terminal IN2, and the drain is connected to the signal output terminal OUT; the gate of MN1 is connected to the first signal input end IN1, the source is connected to the drain of MN2, and the drain is connected to the signal output end OUT; the gate of MN2 is connected to the second signal input IN2, and the source is connected to ground.
When the logic values of the first signal input terminal IN1 and the second signal input terminal IN2 of the C-cell circuit are the same (both 0 or both 1), the signal output terminal OUT provides the opposite logic value to the first signal input terminal IN1 and the second signal input terminal IN2, and the C-cell circuit behaves as an inverter; when the logic values of the first signal input terminal IN1 and the second signal input terminal IN2 are different (one is 0 and the other is 1), the signal output terminal OUT enters a hold state, providing the logic value IN the previous state. Therefore, the C-cell can be used to shield the node from logic inversion, so as to prevent transient logic inversion of the first signal input terminal IN1 or the second signal input terminal IN2 from affecting the output terminal OUT.
Referring to fig. 2, fig. 2 is a schematic structural diagram of an asynchronous reset D flip-flop with resistance to single event upset according to a first embodiment of the present invention, where the asynchronous reset D flip-flop includes:
the circuit comprises a clock signal input circuit 1, a reset signal input circuit 2, a master latch buffer circuit 3, a slave latch buffer circuit 4, a master latch 5 and a slave latch 6, wherein the master latch 5 and the slave latch 6 are dual-mode redundancy reinforced latches.
The asynchronous reset D flip-flop is provided with three input ends and two output ends, wherein the three input ends are a clock signal input end C L K, a reset signal input end R and a data signal input end D respectively, the two output ends are a first output end Q and a second output end QN. respectively, a clock signal input by the clock signal input end C L K is C L K0, a reset signal input by the reset signal input end R is R0, and a data signal input by the data signal input end D is D0.
The clock signal input circuit is respectively connected with a clock signal input end C L K, a reset signal input circuit, a master latch and a slave latch, the reset signal input circuit is also respectively connected with a reset signal input end R, the master latch and the slave latch, the master latch buffer circuit is respectively connected with a data signal input end D and the master latch, the slave latch buffer circuit is respectively connected with the master latch and the slave latch, and the slave latch is also connected with a first output end Q and a second output end QN.
Referring to fig. 3, fig. 3 is a schematic circuit diagram of a clock signal input circuit in an asynchronous reset D flip-flop with single event upset resistance according to a first embodiment of the present invention, where the clock signal input circuit includes:
one input terminal is a clock signal input terminal C L K, and one output terminal is C L K1.
The clock signal input circuit is composed of a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube.
The substrates of the first PMOS tube and the second PMOS tube are connected with a power supply VDD (not shown in the figure), and the substrates of the first NMOS tube and the second NMOS tube are grounded (not shown in the figure).
The grid Pg1 of the first PMOS tube is connected with a clock signal input end C L K, the source Ps1 is connected with a power supply VDD, the drain Pd1 is connected with the source Ps2 of the second PMOS tube, the grid Pg2 of the second PMOS tube is connected with a clock signal input end C L K, the drain Pd2 is connected with C L K1, the grid Ng1 of the first NMOS tube is connected with a clock signal input end C L K, the source Ns1 is connected with the drain Nd2 of the second NMOS tube, the drain Nd1 is connected with C L K1, the grid Ng2 of the second NMOS tube is connected with a clock signal input end C L K, and the source Ns2 is grounded.
The circuit is characterized in that when the logic values of input signals of the grids of the first PMOS tube and the second PMOS tube are the same, or when the logic values of input signals of the grids of the first NMOS tube and the second NMOS tube are the same, the output end outputs an output signal with the logic value opposite to that of the input signal, and when the logic values of the input signals of the grids of the first PMOS tube and the second PMOS tube are different, or when the logic values of the input signals of the grids of the first NMOS tube and the second NMOS tube are different, the logic value of the output signal is kept unchanged before the state.
Referring to fig. 4, fig. 4 is a schematic circuit structure diagram of a reset signal input circuit in an asynchronous reset D flip-flop with single event upset resistance according to a first embodiment of the present invention, where the reset signal input circuit includes:
one input terminal is a reset signal input terminal R and one output terminal is R1.
The reset signal input circuit is composed of a third PMOS tube, a fourth PMOS tube, a third NMOS tube and a fourth NMOS tube.
The substrates of the third PMOS tube and the fourth PMOS tube are connected with a power supply VDD (not shown in the figure), and the substrates of the third NMOS tube and the fourth NMOS tube are grounded (not shown in the figure).
A grid electrode Pg3 of the third PMOS tube is connected with a reset signal input end R, a source electrode Ps3 is connected with a power supply VDD, and a drain electrode Pd3 is connected with a source electrode Ps4 of the fourth PMOS tube; the grid Pg4 of the fourth PMOS tube is connected with the reset signal input end R, and the drain Pd4 is connected with R1; the grid Ng3 of the third NMOS tube is connected with a reset signal input end R, the source Ns3 is connected with the drain Nd4 of the fourth NMOS tube, and the drain Nd3 is connected with R1; the gate Ng4 of the fourth NMOS transistor is connected to the reset signal input terminal R, and the source Ns4 is grounded.
The third PMOS tube, the fourth PMOS tube, the third NMOS tube and the fourth NMOS tube form a circuit of a C unit. The circuit is characterized in that when the logic values of input signals of the grids of a third PMOS tube and a fourth PMOS tube are the same, or when the logic values of the input signals of the grids of a third NMOS tube and a fourth NMOS tube are the same, the output end outputs an output signal with the logic value opposite to that of the input signal; and when the logic values of the input signals of the gates of the third PMOS tube and the fourth PMOS tube are different, or when the logic values of the input signals of the gates of the third NMOS tube and the fourth NMOS tube are different, the logic value of the output signal is kept unchanged before. Therefore, the logic states of the output signal R01 of the output end R1 and the input signal R0 of the input end R are always opposite, and the output signal can be effectively prevented from following single event upset when the logic state of the reset signal of the input end is inverted.
Referring to fig. 5, fig. 5 is a schematic circuit structure diagram of a main latch buffer circuit in an asynchronous reset D flip-flop with resistance to single event upset according to a first embodiment of the present invention, where the main latch buffer circuit includes:
one input terminal is a data signal input terminal D, and two output terminals are D1 and D2, respectively.
The main latch buffer circuit is composed of a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube.
The substrates of the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube, the tenth PMOS tube, the eleventh PMOS tube and the twelfth PMOS tube are connected with a power supply VDD (not shown in the figure), and the substrates of the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube and the twelfth NMOS tube are grounded (not shown in the figure).
A grid Pg5 of the fifth PMOS tube is connected with a data signal input end D, a source electrode Ps5 is connected with a power supply VDD, and a drain electrode Pd5 is respectively connected with a grid Pg6 of the sixth PMOS tube, a drain electrode Nd5 of the fifth NMOS tube and a grid electrode Ng6 of the sixth NMOS tube; a grid Ng5 of the fifth NMOS tube is connected with the data signal input end D, and a source Ns5 is grounded; a source electrode Ps6 of the sixth PMOS tube is connected with a power supply VDD, and a drain electrode Pd6 is respectively connected with a gate electrode Pg7 of the seventh PMOS tube, a drain electrode Nd6 of the sixth NMOS tube and a gate electrode Ng7 of the seventh NMOS tube; the source electrode Ns6 of the sixth NMOS tube is grounded; a source electrode Ps7 of the seventh PMOS tube is connected with a power supply VDD, and a drain electrode Pd7 is respectively connected with a gate electrode Pg8 of the eighth PMOS tube, a drain electrode Nd7 of the seventh NMOS tube and a gate electrode Ng8 of the eighth NMOS tube; the source electrode Ns7 of the seventh NMOS transistor is grounded; the source Ps8 of the eighth PMOS tube is connected with the power supply VDD, and the drain Pd8 is respectively connected with the drains Nd8 and D1 of the eighth NMOS tube; the source Ns8 of the eighth NMOS transistor is grounded.
A grid Pg9 of the ninth PMOS tube is connected with a data signal input end D, a source electrode Ps9 is connected with a power supply VDD, and a drain electrode Pd9 is respectively connected with a grid Pg10 of the tenth PMOS tube, a drain electrode Nd9 of the ninth NMOS tube and a grid electrode Ng12 of the twelfth NMOS tube; a gate Ng9 of the ninth NMOS transistor is respectively connected to a drain Pd10 of the tenth PMOS transistor, a gate Pg11 of the eleventh PMOS transistor, and a drain Nd10 of the tenth NMOS transistor, and a source Ns9 is grounded; a source electrode Ps10 of the tenth PMOS tube is connected with the power supply VDD; a grid Ng10 of the tenth NMOS transistor is respectively connected with a drain Pd11 of the eleventh PMOS transistor, a grid Pg12 of the twelfth PMOS transistor and a drain Nd11 of the eleventh NMOS transistor, and a source Ns10 is grounded; a source electrode Ps11 of the eleventh PMOS tube is connected with a power supply VDD; a grid Ng11 of the eleventh NMOS transistor is respectively connected with a drain Pd12 of the twelfth PMOS transistor, a drain Nd12 of the twelfth NMOS transistor, data signal input ends D and D2, and a source Ns11 is grounded; a source electrode Ps12 of the twelfth PMOS tube is connected with a power supply VDD; the source Ns12 of the twelfth NMOS transistor is grounded.
The DICE unit composed of a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube in the buffer circuit of the master latch reversely forms a feedback loop to form 4 interlocking phase inverter cascades, and 4 storage nodes with phase inverters are connected back to back in the unit structure: n0, n1, n2, n3, where n0 and n2, n1 and n3 are nodes with the same logic state. Different from the traditional interlocking circuit, the grid electrodes of the PMOS tube and the NMOS tube of each stage in the unit structure are respectively triggered by the output signals of the previous stage and the next stage. Thus, the state of each storage node in the cell structure is controlled by the state of its neighboring storage nodes, and neighboring storage nodes are independent of each other. When only one storage node in the circuit has a voltage change, the storage state of each storage node in the DICE unit will not change due to the feedback effect of other nodes. The fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube and the eighth NMOS tube in the buffer circuit of the master latch respectively form four phase inverters in pairs, and a delay circuit is formed. Therefore, the logic state of the signal D01 obtained at the output end D2 after the input signal D0 of the data signal input end D is buffered by the DICE unit should be consistent with the logic state of the signal D0 obtained at the output end D1 after the input signal D0 is delayed by the inverter, and the single event effect resistance effect is achieved.
Referring to fig. 6, fig. 6 is a schematic circuit diagram of a main latch in an asynchronous reset D flip-flop with single event upset resistance according to a first embodiment of the present invention, where the main latch includes:
eleven input ends and one output end, wherein four input ends are respectively connected with the clock signal input end C L K, four input ends are respectively connected with the clock signal input end C L K1, one input end is connected with the R1, one input end is connected with the D1, one input end is connected with the D2, and the other output end is D3.
The main latch is composed of a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-third PMOS tube, a twenty-fourth PMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube and a twenty-third NMOS tube.
Substrates of a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-third PMOS tube and a twenty-fourth PMOS tube are connected with a power supply VDD (not shown in the figure), and substrates of a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube and a twenty-third NMOS tube are grounded (not shown in the figure).
The grid Ng13 of the thirteenth NMOS tube is connected with C L K, the source Ns13 is connected with the sources Ps13 and D13 of the thirteenth PMOS tube respectively, the drain Nd13 is connected with the drain Pd13 of the thirteenth PMOS tube, the source Ns13 of the sixteenth NMOS tube, the source Ps13 of the sixteenth PMOS tube, the grid Ng13 of the seventeenth NMOS tube, the grid Pg13 of the eighteenth PMOS tube, the grid Ng13 of the nineteenth NMOS tube and the grid Pg13 of the twentieth PMOS tube respectively, the grid Pg13 of the thirteenth PMOS tube is connected with C13K 13, the grid Ng13 of the fourteenth NMOS tube is connected with C13K, the source Ns13 of the fourteenth NMOS tube is connected with the source Ps13 and D13 of the fourteenth PMOS tube, the drain Nd13 is connected with the drain Pd13 of the fourteenth PMOS tube, the source Ng13 of the fifteenth NMOS tube, the source Ps13 of the fifteenth PMOS tube, the source Pps 13 of the seventeenth PMOS tube, the grid Pg13 of the seventeenth PMOS tube, the eighteenth NMOS tube, the grid Pg13 of the fourteenth PMOS tube and the grid Pg13 of the nineteenth PMOS tube, and the grid Pg 36.
The grid Ng15 of the fifteenth NMOS tube is connected with C L K1, the drain Nd15 is respectively connected with the drain Pd15 of the fifteenth PMOS tube, the drain Pd21 of the twenty-first PMOS tube and the drain Nd21 of the twenty-first NMOS tube, the grid Pg15 of the fifteenth PMOS tube is connected with C L K, the grid Ng16 of the sixteenth NMOS tube is connected with C L K1, the drain Nd16 is respectively connected with the drain Pd16 of the sixteenth PMOS tube, the drain Pd22 of the twenty-second PMOS tube and the drain Nd22 of the twenty-second NMOS tube, and the grid Pg16 of the sixteenth PMOS tube is connected with C L K.
A source electrode Ps17 of the seventeenth PMOS tube is connected with a power supply VDD, and a drain electrode Pd17 is connected with a source electrode Ps18 of the eighteenth PMOS tube; a drain electrode Pd18 of the eighteenth PMOS tube is respectively connected with a drain electrode Nd17 of the seventeenth NMOS tube, a drain electrode Pd23 of the twenty third PMOS tube, a gate electrode Ng21 of the twenty first NMOS tube, a gate electrode Pg22 of the twenty second PMOS tube, a gate electrode Pg24 of the twenty fourth PMOS tube and a gate electrode Ng23 of the twenty third NMOS tube; a grid electrode Pg23 of the twenty-third PMOS tube is connected with R1, and a source electrode Ps23 is connected with a power supply VDD; the source electrode Ns17 of the seventeenth NMOS transistor is connected with the drain electrode Nd18 of the eighteenth NMOS transistor; the source electrode Ns18 of the eighteenth NMOS tube is grounded; a source electrode Ps19 of the nineteenth PMOS tube is connected with the power supply VDD, and a drain electrode Pd19 is connected with a source electrode Ps20 of the twentieth PMOS tube; a drain electrode Pd20 of the twentieth PMOS tube is respectively connected with a drain electrode Nd19 of the nineteenth NMOS tube, a gate electrode Pg21 of the twenty-first PMOS tube and a gate electrode Ng22 of the twenty-second NMOS tube; the source electrode Ns19 of the nineteenth NMOS transistor is connected with the drain electrode Nd20 of the twentieth NMOS transistor; the source Ns20 of the twentieth NMOS transistor is grounded.
A source electrode Ps21 of the twenty-first PMOS tube is connected with a power supply VDD; the source electrode Ns21 of the twenty-first NMOS transistor is grounded; a source electrode Ps22 of the twenty-second PMOS tube is connected with a power supply VDD; the source electrode Ns22 of the twenty-second NMOS transistor is grounded; a source electrode Ps24 of the twenty-fourth PMOS tube is connected with a power supply VDD, and a drain electrode Pd24 is respectively connected with drain electrodes Nd23 and D3 of the twenty-third NMOS tube; the source Ns23 of the twenty-third NMOS transistor is grounded.
The master latch is formed by a dual redundant DICE fabric circuit. In the figure, a thirteenth PMOS tube and a thirteenth NMOS tube form a first transmission gate, a fourteenth PMOS tube and a fourteenth NMOS tube form a second transmission gate, a fifteenth PMOS tube and a fifteenth NMOS tube form a third transmission gate, a sixteenth PMOS tube and a sixteenth NMOS tube form a fourth transmission gate, the four transmission gates are controlled by clock signals, and the on-off states of the first transmission gate and the second transmission gate are opposite to the on-off states of the third transmission gate and the fourth transmission gate.
When the logic value of the signal C L K0 input from the C L K port is 1, the logic value of the signal C L K01 input from the C L K1 port is 0, the first and second transmission gates are turned on, and the third and fourth transmission gates are turned off, the D1 port is connected to the gate Ng17 of the seventeenth NMOS transistor and the gate Pg18 of the eighteenth PMOS transistor through the first transmission gate, respectively, and the D2 port is connected to the gate Pg17 of the seventeenth PMOS transistor and the gate ng18 of the eighteenth NMOS transistor through the second transmission gate, respectively, the seventeenth PMOS transistor, the eighteenth PMOS transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor together form a C unit circuit based on a DICE structure.
When the logic value of a signal C L K0 input by a C L K port is 0, the logic value of a signal C L K01 input by a C L K1 port is 1, a first transmission gate and a second transmission gate are turned off, a third transmission gate and a fourth transmission gate are turned on, at this time, the logic states of nodes a and b are latched by a feedback loop formed by a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a seventeenth NMOS tube, an eighteenth PMOS tube, a twenty-first PMOS tube, a twenty-second NMOS tube, a node a is the same as the logic state of a node b, a node C is the same as the logic state of a node D, the logic states of the node a and the node C are opposite, the logic state of an output signal D02 of an output end D3 is kept unchanged, the seventeenth PMOS tube, the eighteenth PMOS tube, the seventeenth tube, the eighteenth NMOS tube, the eighteenth NMOS tube, the nineteenth NMOS tube, the twenty-th NMOS tube and the twenty-ninth NMOS tube form a feedback loop which can effectively prevent single-event of the PMOS tube from being inverted, and effectively preventing the single-event of the single-event.
Referring to fig. 7, fig. 7 is a schematic circuit diagram of a slave latch buffer circuit in an asynchronous reset D flip-flop with resistance to single event upset according to a first embodiment of the present invention, where the slave latch buffer circuit includes:
one input end and two output ends, wherein the input end is connected with the D3, and the two output ends are respectively D4 and D5.
The slave latch buffer circuit is composed of a twenty-fifth PMOS (P-channel metal oxide semiconductor) tube, a twenty-sixth PMOS tube, a twenty-seventh PMOS tube, a twenty-eighth PMOS tube, a twenty-ninth PMOS tube, a thirtieth PMOS tube, a thirty-eleventh PMOS tube, a thirty-second PMOS tube, a twenty-fourth NMOS tube, a twenty-fifth NMOS tube, a twenty-sixth NMOS tube, a twenty-seventh NMOS tube, a twenty-eighth NMOS tube, a twenty-ninth NMOS tube, a thirty-NMOS tube and a thirty-eleventh NMOS tube.
Substrates of twenty-fifth PMOS tubes, twenty-sixth PMOS tubes, twenty-seventh PMOS tubes, twenty-eighth PMOS tubes, twenty-ninth PMOS tubes, thirtieth PMOS tubes, thirty-eleventh PMOS tubes and thirty-second PMOS tubes are connected with a power supply VDD (not shown in the figure), and substrates of twenty-fourth NMOS tubes, twenty-fifth NMOS tubes, twenty-sixth NMOS tubes, twenty-seventh NMOS tubes, twenty-eighth NMOS tubes, twenty-ninth NMOS tubes, thirty-NMOS tubes and thirty-eleventh NMOS tubes are grounded (not shown in the figure).
A grid Pg25 of the twenty-fifth PMOS tube is connected with D3, a source electrode Ps25 is connected with a power supply VDD, and a drain electrode Pd25 is respectively connected with a grid Pg26 of the twenty-sixth PMOS tube, a drain electrode Nd24 of the twenty-fourth NMOS tube and a grid electrode Ng25 of the twenty-fifth NMOS tube; the gate Ng24 of the twenty-fourth NMOS transistor is connected with D3, and the source Ns24 is grounded; a source electrode Ps26 of the twenty-sixth PMOS tube is connected with a power supply VDD, and a drain electrode Pd26 is respectively connected with a gate electrode Pg27 of the twenty-seventh PMOS tube, a drain electrode Nd25 of the twenty-fifth NMOS tube and a gate electrode Ng26 of the twenty-sixth NMOS tube; the twenty-fifth NMOS transistor source electrode Ns25 is grounded; a source electrode Ps27 of the twenty-seventh PMOS tube is connected with a power supply VDD, and a drain electrode Pd27 is respectively connected with a gate electrode Pg28 of the twenty-eighth PMOS tube, a drain electrode Nd26 of the twenty-sixth NMOS tube and a gate electrode Ng27 of the twenty-seventh NMOS tube; the twenty-sixth NMOS transistor source electrode Ns26 is grounded; a source electrode Ps28 of the twenty-eighth PMOS tube is connected with a power supply VDD, and a drain electrode Pd28 is respectively connected with drain electrodes Nd27 and D4 of the twenty-seventh NMOS tube; the source Ns27 of the twenty-seventh NMOS transistor is grounded.
A grid Pg29 of the twenty-ninth PMOS tube is connected with D3, a source electrode Ps29 is connected with a power supply VDD, and a drain electrode Pd29 is respectively connected with a grid Pg30 of the thirty-ninth PMOS tube, a drain electrode Nd28 of the twenty-eighth NMOS tube and a grid electrode Ng31 of the thirty-first NMOS tube; a grid Ng28 of the twenty-eighth NMOS transistor is respectively connected with a drain Pd30 of the thirty-eighth PMOS transistor, a grid Pg31 of the thirty-first PMOS transistor and a drain Nd29 of the twenty-ninth NMOS transistor, and a source Ns28 is grounded; a source electrode Ps30 of the thirtieth PMOS tube is connected with the power supply VDD; the grid Ng29 of the twenty-ninth NMOS transistor is respectively connected with the drain Pd31 of the thirty-first PMOS transistor, the grid Pg32 of the thirty-second PMOS transistor and the drain Nd30 of the thirty-second NMOS transistor, and the source Ns29 is grounded; a source electrode Ps31 of the thirty-first PMOS tube is connected with a power supply VDD; the grid Ng30 of the thirty-second NMOS transistor is respectively connected with the drain Pd32 of the thirty-second PMOS transistor and the drains Nd31, D3 and D5 of the thirty-first NMOS transistor, and the source Ns30 is grounded; a source electrode Ps32 of the thirty-second PMOS tube is connected with the power supply VDD; the source Ns31 of the thirty-first NMOS transistor is grounded.
The working principle of the slave latch buffer circuit is the same as that of the master latch buffer circuit, and the details are not repeated herein.
Referring to fig. 8, fig. 8 is a schematic circuit diagram of a slave latch in an asynchronous reset D flip-flop with resistance to single event upset according to a first embodiment of the present invention, where the slave latch includes:
the clock signal input end comprises eleven input ends and two output ends, wherein the four input ends are respectively connected with the clock signal input end C L K, the four input ends are respectively connected with the clock signal input end C L K1, one input end is connected with the R1, one input end is connected with the D4, one input end is connected with the D5, and the two output ends are respectively a first output end Q and a second output end QN.
The slave latch is composed of a thirty-third PMOS tube, a thirty-fourth PMOS tube, a thirty-fifth PMOS tube, a thirty-sixth PMOS tube, a thirty-seventh PMOS tube, a thirty-eighth PMOS tube, a thirty-ninth PMOS tube, a forty-first PMOS tube, a forty-second PMOS tube, a forty-third PMOS tube, a forty-fourth PMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a thirty-sixth NMOS tube, a thirty-seventh NMOS tube, a thirty-eighth NMOS tube, a thirty-ninth NMOS tube, a forty-fourth NMOS tube, a forty-first NMOS tube and a forty-second NMOS tube.
A substrate of the thirty-third PMOS transistor, the thirty-fourth PMOS transistor, the thirty-fifth PMOS transistor, the thirty-sixth PMOS transistor, the thirty-seventh PMOS transistor, the thirty-eighth PMOS transistor, the thirty-ninth PMOS transistor, the forty-first PMOS transistor, the forty-second PMOS transistor, the forty-third PMOS transistor and the forty-fourth PMOS transistor is connected with a power supply VDD (not shown in the figure), and a substrate of the thirty-second NMOS transistor, the thirty-third NMOS transistor, the thirty-fourth NMOS transistor, the thirty-fifth NMOS transistor, the thirty-sixth NMOS transistor, the thirty-seventh NMOS transistor, the thirty-eighth NMOS transistor, the thirty-ninth NMOS transistor, the forty-first NMOS transistor and the forty-second NMOS transistor is grounded (not shown in the figure).
The grid Ng32 of the thirty-second NMOS transistor is connected with the C L K1, the source Ns32 is connected with the sources Ps32 and D32 of the thirty-third PMOS transistor respectively, the drain Nd32 is connected with the drain Pd32 of the thirty-third PMOS transistor, the source Ns32 of the thirty-fifth NMOS transistor, the source Ps32 of the thirty-sixth PMOS transistor, the grid Ng32 of the thirty-sixth NMOS transistor, the grid Pg32 of the thirty-eighth PMOS transistor, the grid Ng32 of the thirty-eighth NMOS transistor, the grid Pg32 of the forty-fourth PMOS transistor, the grid Pg32 of the thirty-third PMOS transistor is connected with the C32K, the source Ng32 is connected with the source Ps32 and D32 of the thirty-fourth PMOS transistor respectively, the drain Ng32 of the thirty-fourth PMOS transistor, the source Pd32 of the thirty-fourth NMOS transistor, the source Ng32 of the thirty-fifth PMOS transistor, the thirty-ninth PMOS 72, the thirty-ninth PMOS, the grid Pg32 of the thirty-fourth PMOS transistor is connected with the grid Pg32, the thirty-ninth PMOS, the grid Ng32 of the thirty-ninth PMOS.
The grid Ng34 of the thirty-fourth NMOS transistor is connected with C L K, the drain Nd34 is respectively connected with the drain Pd35 of the thirty-fifth PMOS transistor, the drain Pd41 of the forty-first PMOS transistor and the drain Nd40 of the forty-NMOS transistor, the grid Pg35 of the thirty-fifth PMOS transistor is connected with C L K1, the grid Ng35 of the thirty-fifth NMOS transistor is connected with C L K, the drain Nd35 is respectively connected with the drain Pd36 of the thirty-sixth PMOS transistor, the drain Pd42 of the forty-second PMOS transistor and the drain Nd41 of the forty-first NMOS transistor, and the grid Pg36 of the thirty-sixth PMOS transistor is connected with C L K1.
A source electrode Ps37 of the thirty-seventh PMOS tube is connected with the power supply VDD, and a drain electrode Pd37 is connected with a source electrode Ps38 of the thirty-eighth PMOS tube; a drain electrode Pd38 of the thirty-eighth PMOS tube is respectively connected with a drain electrode Nd36 of the thirty-sixth NMOS tube, a drain electrode Pd43 of the forty-third PMOS tube, a gate electrode Ng40 of the forty-NMOS tube, a gate electrode Pg42 of the forty-second PMOS tube, a gate electrode Pg44 of the forty-fourth PMOS tube, a gate electrode Ng42 of the forty-second NMOS tube and a second output end QN; the gate Pg43 of the forty-third PMOS tube is connected with R1, and the source Ps43 is connected with the power supply VDD; the source electrode Ns36 of the thirty-sixth NMOS transistor is connected with the drain electrode Nd37 of the thirty-seventh NMOS transistor; the source electrode Ns37 of the thirty-seventh NMOS transistor is grounded; a source electrode Ps39 of the thirty-ninth PMOS tube is connected with a power supply VDD, and a drain electrode Pd39 is connected with a source electrode Ps40 of the forty-ninth PMOS tube; a drain Pd40 of the forty-eighth PMOS tube is respectively connected with a drain Nd38 of the thirty-eighth NMOS tube, a gate Pg41 of the forty-first PMOS tube and a gate Ng41 of the forty-first NMOS tube; the source electrode Ns38 of the thirty-eighth NMOS transistor is connected with the drain electrode Nd39 of the thirty-ninth NMOS transistor; the source Ns39 of the thirty-ninth NMOS transistor is grounded.
A source electrode Ps41 of the forty-first PMOS tube is connected with a power supply VDD; the source electrode Ns40 of the fortieth NMOS tube is grounded; the source electrode Ps42 of the forty-second PMOS tube is connected with the power supply VDD; the source Ns41 of the forty-first NMOS transistor is grounded; a source electrode Ps44 of the forty-fourth PMOS tube is connected with a power supply VDD, and a drain electrode Pd44 is respectively connected with a drain electrode Nd42 of the forty-second NMOS tube and a first output end Q; the source Ns42 of the forty-second NMOS transistor is grounded.
The working principle of the slave latch is the same as that of the master latch, and the description is omitted here.
The control of the reset signal to the circuit output in this patent is asynchronous to the clock signal, i.e. the control of the reset signal to the circuit output is independent of the state of the clock signal. When the reset signal R0 is equal to 1, no reset operation is performed; when the reset signal R0 is equal to 0, R1 is equal to 1, the twenty-third PMOS transistor in the master latch is turned on, the drain voltage of the twenty-third PMOS transistor is pulled high by the power voltage, and the output signal D02 is reset to 0 by the feedback loop. At this time, since the two transmission gates connected to the slave latch input terminals D4 and D5 in the slave latch are in the on state, the output signal of the slave latch output terminal Q is also set to 0, and the reset operation of the circuit is completed. The state of the clock signal does not affect the control of the reset signal on the circuit output in this process
Compared with the prior art, the asynchronous reset D trigger capable of resisting single event upset provided by the embodiment of the invention has the advantages that the buffer circuit is added in front of the master latch and the slave latch, the single event upset resistance of the asynchronous reset D trigger is improved, dual-mode redundancy reinforcement is carried out on the master latch and the slave latch, namely the asynchronous reset D trigger is separated into the C latches which are redundant with each other2The pull-up PMOS tube and the pull-down NMOS tube in the MOS circuit avoid a feedback loop possibly caused by a single-event transient pulse in the slave latch from affecting C in the master latch circuit and the slave latch circuit2The MOS circuit is improved, the control of a clock signal to the circuit is realized through a CMOS transmission gate, and the single event upset resistance of the asynchronous reset D trigger is further improved.
It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present invention is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no acts or modules are necessarily required of the invention.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The foregoing is a description of the single event upset resistant asynchronous reset D flip-flop provided in the present invention, and for those skilled in the art, there may be variations in the specific implementation and application scope according to the concepts of the embodiments of the present invention, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (6)
1. An asynchronous reset D flip-flop resistant to single event upset, comprising:
the dual-mode redundancy circuit comprises a clock signal input circuit, a reset signal input circuit, a master latch buffer circuit, a slave latch buffer circuit, a master latch and a slave latch, wherein the master latch and the slave latch are dual-mode redundancy reinforced latches;
the asynchronous reset D trigger is provided with three input ends and two output ends, wherein the three input ends are a clock signal input end C L K, a reset signal input end R and a data signal input end D respectively, and the two output ends are a first output end Q and a second output end QN respectively;
the clock signal input circuit is respectively connected with the clock signal input end C L K, the master latch and the slave latch;
the reset signal input circuit is also respectively connected with the reset signal input end R, the master latch and the slave latch;
the main latch buffer circuit is respectively connected with the data signal input end D and the main latch;
the slave latch buffer circuit is respectively connected with the master latch and the slave latch;
the slave latch is further connected with the first output end Q and the second output end QN;
wherein said clock signal input circuit has an input terminal and an output terminal, one of said input terminals being said clock signal input terminal C L K and one of said output terminals being C L K1;
the clock signal input circuit is composed of a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube;
the substrates of the first PMOS tube and the second PMOS tube are connected with a power supply VDD, and the substrates of the first NMOS tube and the second NMOS tube are grounded;
the grid Pg1 of the first PMOS tube is connected with the clock signal input end C L K, the source Ps1 is connected with the power supply VDD, the drain Pd1 is connected with the source Ps2 of the second PMOS tube, the grid Pg2 of the second PMOS tube is connected with the clock signal input end C L K, the drain Pd2 is connected with the clock signal input end C L K1, the grid Ng1 of the first NMOS tube is connected with the clock signal input end C L K, the source Ns1 is connected with the drain Nd2 of the second NMOS tube, the drain Nd1 is connected with the C L K1, the grid Ng2 of the second NMOS tube is connected with the clock signal input end C L K, and the source 36Ns 29 is grounded.
2. The asynchronous reset D flip-flop against single event upset of claim 1, wherein said reset signal input circuit has an input terminal and an output terminal, one of said input terminals being said reset signal input terminal R and one of said output terminals being R1;
the reset signal input circuit is composed of a third PMOS tube, a fourth PMOS tube, a third NMOS tube and a fourth NMOS tube;
the substrates of the third PMOS tube and the fourth PMOS tube are connected with a power supply VDD, and the substrates of the third NMOS tube and the fourth NMOS tube are grounded;
the grid electrode Pg3 of the third PMOS tube is connected with the reset signal input end R, the source electrode Ps3 is connected with the power supply VDD, and the drain electrode Pd3 is connected with the source electrode Ps4 of the fourth PMOS tube; the grid electrode Pg4 of the fourth PMOS tube is connected with the reset signal input end R, and the drain electrode Pd4 is connected with R1; the gate Ng3 of the third NMOS transistor is connected to the reset signal input terminal R, the source Ns3 is connected to the drain Nd4 of the fourth NMOS transistor, and the drain Nd3 is connected to R1; the gate Ng4 of the fourth NMOS transistor is connected to the reset signal input terminal R, and the source Ns4 is grounded.
3. The asynchronous reset D flip-flop against single event upset of claim 2, wherein said master latch buffer circuit has an input terminal and two output terminals, one of said input terminals being said data signal input terminal D and two of said output terminals being D1 and D2, respectively;
the master latch buffer circuit consists of a fifth PMOS (P-channel metal oxide semiconductor) tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube;
the substrates of the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube, the tenth PMOS tube, the eleventh PMOS tube and the twelfth PMOS tube are connected with a power supply VDD, and the substrates of the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube and the twelfth NMOS tube are grounded;
the grid Pg5 of the fifth PMOS tube is connected with the data signal input end D, the source electrode Ps5 is connected with the power supply VDD, and the drain electrode Pd5 is respectively connected with the grid Pg6 of the sixth PMOS tube, the drain electrode Nd5 of the fifth NMOS tube and the grid electrode Ng6 of the sixth NMOS tube; the grid Ng5 of the fifth NMOS transistor is connected with the data signal input end D, and the source Ns5 is grounded; a source electrode Ps6 of the sixth PMOS tube is connected with a power supply VDD, and a drain electrode Pd6 of the sixth PMOS tube is respectively connected with a gate electrode Pg7 of the seventh PMOS tube, a drain electrode Nd6 of the sixth NMOS tube and a gate electrode Ng7 of the seventh NMOS tube; the source electrode Ns6 of the sixth NMOS tube is grounded; a source electrode Ps7 of the seventh PMOS tube is connected with a power supply VDD, and a drain electrode Pd7 of the seventh PMOS tube is respectively connected with a gate electrode Pg8 of the eighth PMOS tube, a drain electrode Nd7 of the seventh NMOS tube and a gate electrode Ng8 of the eighth NMOS tube; the source electrode Ns7 of the seventh NMOS transistor is grounded; the source electrode Ps8 of the eighth PMOS tube is connected with a power supply VDD, and the drain electrode Pd8 is respectively connected with the drain electrodes Nd8 and D1 of the eighth NMOS tube; the source electrode Ns8 of the eighth NMOS transistor is grounded;
a gate Pg9 of the ninth PMOS transistor is connected to the data signal input terminal D, a source Ps9 is connected to the power supply VDD, and a drain Pd9 is connected to a gate Pg10 of the tenth PMOS transistor, a drain Nd9 of the ninth NMOS transistor, and a gate Ng12 of the twelfth NMOS transistor, respectively; the gate Ng9 of the ninth NMOS transistor is respectively connected to the drain Pd10 of the tenth PMOS transistor, the gate Pg11 of the eleventh PMOS transistor, and the drain Nd10 of the tenth NMOS transistor, and the source Ns9 is grounded; a source electrode Ps10 of the tenth PMOS tube is connected with a power supply VDD; the grid Ng10 of the tenth NMOS transistor is respectively connected with the drain Pd11 of the eleventh PMOS transistor, the grid Pg12 of the twelfth PMOS transistor and the drain Nd11 of the eleventh NMOS transistor, and the source Ns10 is grounded; a source electrode Ps11 of the eleventh PMOS tube is connected with a power supply VDD; the grid Ng11 of the eleventh NMOS transistor is respectively connected with the drain Pd12 of the twelfth PMOS transistor, the drain Nd12 of the twelfth NMOS transistor, the data signal input ends D and D2, and the source Ns11 is grounded; a source electrode Ps12 of the twelfth PMOS tube is connected with a power supply VDD; the source Ns12 of the twelfth NMOS transistor is grounded.
4. The asynchronous reset D flip-flop against single event upset of claim 3, wherein said master latch has eleven input terminals and one output terminal, wherein four of said input terminals are respectively connected to said clock signal input terminal C L K, four of said input terminals are respectively connected to C L K1, one of said input terminals is connected to R1, one of said input terminals is connected to D1, one of said input terminals is connected to D2;
the main latch is composed of a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-third PMOS tube, a twenty-fourth PMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube and a twenty-third NMOS tube;
the thirteenth PMOS tube, the fourteenth PMOS tube, the fifteenth PMOS tube, the sixteenth PMOS tube, the seventeenth PMOS tube, the eighteenth PMOS tube, the nineteenth PMOS tube, the twentieth PMOS tube, the twenty-first PMOS tube, the twenty-second PMOS tube, the twenty-third PMOS tube and the twenty-fourth PMOS tube have substrates connected with a power supply VDD, and the thirteenth NMOS tube, the fourteenth NMOS tube, the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube, the eighteenth NMOS tube, the nineteenth NMOS tube, the twenty-first NMOS tube, the twenty-second NMOS tube and the twenty-third NMOS tube have substrates grounded;
a grid Ng13 of the thirteenth NMOS tube is connected with C L K, a source Ns13 is connected with a source Ps13 and a source D13 of the thirteenth PMOS tube respectively, a drain Nd13 is connected with a drain Pd13 of the thirteenth PMOS tube, a source Ns13 of the sixteenth NMOS tube, a source Ps13 of the sixteenth PMOS tube, a gate Ng13 of the seventeenth NMOS tube, a gate Pg13 of the eighteenth PMOS tube, a gate Ng13 of the nineteenth NMOS tube and a gate Pg13 of the twentieth PMOS tube respectively, a gate Pg13 of the thirteenth PMOS tube is connected with C13K 13, a gate Ng13 of the fourteenth NMOS tube is connected with C13K, a source Ns13 of the fourteenth NMOS tube is connected with the source Ps13 and the D13 of the fourteenth PMOS tube, a drain Ng13 of the fourteenth NMOS tube, a source Ps13 of the fifteenth NMOS tube, a source Pg13 of the fifteenth PMOS tube, a source Pg13 of the seventeenth PMOS tube, a gate Pg13 of the fourteenth PMOS tube, a gate Pfourteenth PMOS tube and a gate Pg13 of the fourteenth PMOS tube;
the grid Ng15 of the fifteenth NMOS tube is connected with C L K1, the drain Nd15 of the fifteenth NMOS tube is respectively connected with the drain Pd15 of the fifteenth PMOS tube, the drain Pd21 of the twenty-first PMOS tube and the drain Nd21 of the twenty-first NMOS tube, the grid Pg15 of the fifteenth PMOS tube is connected with C L K, the grid Ng16 of the sixteenth NMOS tube is connected with C L K1, the drain Nd16 of the fifteenth NMOS tube is respectively connected with the drain Pd16 of the sixteenth PMOS tube, the drain Pd22 of the twenty-second PMOS tube and the drain Nd22 of the twenty-second NMOS tube, and the grid Pg16 of the sixteenth PMOS tube is connected with C L K;
a source electrode Ps17 of the seventeenth PMOS tube is connected with a power supply VDD, and a drain electrode Pd17 is connected with a source electrode Ps18 of the eighteenth PMOS tube; a drain electrode Pd18 of the eighteenth PMOS tube is respectively connected with a drain electrode Nd17 of the seventeenth NMOS tube, a drain electrode Pd23 of the twenty third PMOS tube, a gate electrode Ng21 of the twenty first NMOS tube, a gate electrode Pg22 of the twenty second PMOS tube, a gate electrode Pg24 of the twenty fourth PMOS tube and a gate electrode Ng23 of the twenty third NMOS tube; the gate Pg23 of the twenty-third PMOS tube is connected with R1, and the source Ps23 is connected with a power supply VDD; the source electrode Ns17 of the seventeenth NMOS tube is connected with the drain electrode Nd18 of the eighteenth NMOS tube; the source electrode Ns18 of the eighteenth NMOS tube is grounded; a source electrode Ps19 of the nineteenth PMOS tube is connected with a power supply VDD, and a drain electrode Pd19 is connected with a source electrode Ps20 of the twentieth PMOS tube; the drain electrode Pd20 of the twentieth PMOS tube is respectively connected with the drain electrode Nd19 of the nineteenth NMOS tube, the gate electrode Pg21 of the twenty-first PMOS tube and the gate electrode Ng22 of the twenty-second NMOS tube; the source electrode Ns19 of the nineteenth NMOS transistor is connected with the drain electrode Nd20 of the twentieth NMOS transistor; the source electrode Ns20 of the twentieth NMOS tube is grounded;
a source electrode Ps21 of the twenty-first PMOS tube is connected with a power supply VDD; the source electrode Ns21 of the twenty-first NMOS transistor is grounded; a source electrode Ps22 of the twenty-second PMOS tube is connected with a power supply VDD; the source electrode Ns22 of the twenty-second NMOS transistor is grounded; a source electrode Ps24 of the twenty-fourth PMOS tube is connected with a power supply VDD, and a drain electrode Pd24 is respectively connected with drain electrodes Nd23 and D3 of the twenty-third NMOS tube; the source Ns23 of the twenty-third NMOS transistor is grounded.
5. The asynchronous reset D flip-flop against single event upset of claim 4, wherein said slave latch buffer circuit has an input and two outputs, one of said inputs being connected to D3 and two of said outputs being D4 and D5, respectively;
the slave latch buffer circuit consists of a twenty-fifth PMOS (P-channel metal oxide semiconductor) tube, a twenty-sixth PMOS tube, a twenty-seventh PMOS tube, a twenty-eighth PMOS tube, a twenty-ninth PMOS tube, a thirtieth PMOS tube, a thirty-eleventh PMOS tube, a thirty-second PMOS tube, a twenty-fourth NMOS tube, a twenty-fifth NMOS tube, a twenty-sixth NMOS tube, a twenty-seventh NMOS tube, a twenty-eighth NMOS tube, a twenty-ninth NMOS tube, a thirty-NMOS tube and a thirty-eleventh NMOS tube;
the twenty-fifth PMOS tube, the twenty-sixth PMOS tube, the twenty-seventh PMOS tube, the twenty-eighth PMOS tube, the twenty-ninth PMOS tube, the thirty-sixth PMOS tube, the thirty-eleventh PMOS tube and the thirty-second PMOS tube have substrates connected with a power supply VDD, and the twenty-fourth NMOS tube, the twenty-fifth NMOS tube, the twenty-sixth NMOS tube, the twenty-seventh NMOS tube, the twenty-eighth NMOS tube, the twenty-ninth NMOS tube, the thirty-NMOS tube and the thirty-eleventh NMOS tube have substrates grounded;
the grid Pg25 of the twenty-fifth PMOS tube is connected with the D3, the source electrode Ps25 is connected with the power supply VDD, and the drain electrode Pd25 is respectively connected with the grid Pg26 of the twenty-sixth PMOS tube, the drain electrode Nd24 of the twenty-fourth NMOS tube and the grid electrode Ng25 of the twenty-fifth NMOS tube; the gate Ng24 of the twenty-fourth NMOS transistor is connected with the D3, and the source Ns24 is grounded; a source electrode Ps26 of the twenty-sixth PMOS tube is connected with a power supply VDD, and a drain electrode Pd26 of the twenty-sixth PMOS tube is respectively connected with a gate electrode Pg27 of the twenty-seventh PMOS tube, a drain electrode Nd25 of the twenty-fifth NMOS tube and a gate electrode Ng26 of the twenty-sixth NMOS tube; the twenty-fifth NMOS transistor source electrode Ns25 is grounded; a source electrode Ps27 of the twenty-seventh PMOS tube is connected with a power supply VDD, and a drain electrode Pd27 is respectively connected with a gate electrode Pg28 of the twenty-eighth PMOS tube, a drain electrode Nd26 of the twenty-sixth NMOS tube and a gate electrode Ng27 of the twenty-seventh NMOS tube; the twenty-sixth NMOS transistor source electrode Ns26 is grounded; a source electrode Ps28 of the twenty-eighth PMOS tube is connected with a power supply VDD, and a drain electrode Pd28 is respectively connected with drain electrodes Nd27 and D4 of the twenty-seventh NMOS tube; the source electrode Ns27 of the twenty-seventh NMOS transistor is grounded;
the grid Pg29 of the twenty-ninth PMOS tube is connected with D3, the source electrode Ps29 is connected with a power supply VDD, and the drain electrode Pd29 is respectively connected with the grid Pg30 of the thirty-ninth PMOS tube, the drain electrode Nd28 of the twenty-eighth NMOS tube and the grid electrode Ng31 of the thirty-first NMOS tube; the gate Ng28 of the twenty-eighth NMOS transistor is respectively connected to the drain Pd30 of the thirty-eighth PMOS transistor, the gate Pg31 of the thirty-eleventh PMOS transistor, and the drain Nd29 of the twenty-ninth NMOS transistor, and the source Ns28 is grounded; a source electrode Ps30 of the thirty-fifth PMOS tube is connected with a power supply VDD; the grid Ng29 of the twenty-ninth NMOS transistor is respectively connected with the drain Pd31 of the thirty-first PMOS transistor, the grid Pg32 of the thirty-second PMOS transistor and the drain Nd30 of the thirty-second NMOS transistor, and the source Ns29 is grounded; a source electrode Ps31 of the thirty-first PMOS tube is connected with a power supply VDD; the gate Ng30 of the thirty-second PMOS tube is respectively connected with the drain Pd32 of the thirty-second PMOS tube and the drains Nd31, D3 and D5 of the thirty-first NMOS tube, and the source Ns30 is grounded; a source electrode Ps32 of the thirty-second PMOS tube is connected with a power supply VDD; the source Ns31 of the thirty-first NMOS transistor is grounded.
6. The asynchronous reset D flip-flop against single event upset of claim 5, wherein said slave latch has eleven inputs and two outputs, four of said inputs being connected to said clock signal input C L K, four of said inputs being connected to C L K1, one of said inputs being connected to R1, one of said inputs being connected to D4, one of said inputs being connected to D5;
the slave latch is composed of a thirty-third PMOS (P-channel metal oxide semiconductor) tube, a thirty-fourth PMOS tube, a thirty-fifth PMOS tube, a thirty-sixth PMOS tube, a thirty-seventh PMOS tube, a thirty-eighth PMOS tube, a thirty-ninth PMOS tube, a forty-first PMOS tube, a forty-second PMOS tube, a forty-third PMOS tube, a forty-fourth PMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a thirty-sixth NMOS tube, a thirty-seventh NMOS tube, a thirty-eighth NMOS tube, a thirty-ninth NMOS tube, a forty-first NMOS tube and a forty-second NMOS tube;
the thirty-third PMOS tube, the thirty-fourth PMOS tube, the thirty-fifth PMOS tube, the thirty-sixth PMOS tube, the thirty-seventh PMOS tube, the thirty-eighth PMOS tube, the thirty-ninth PMOS tube, the forty-first PMOS tube, the forty-second PMOS tube, the forty-third PMOS tube and the forty-fourth PMOS tube have their substrates connected to a power supply VDD, and the thirty-second NMOS tube, the thirty-third NMOS tube, the thirty-fourth NMOS tube, the thirty-fifth NMOS tube, the thirty-sixth NMOS tube, the thirty-seventh NMOS tube, the thirty-eighth NMOS tube, the thirty-ninth NMOS tube, the forty-first NMOS tube and the substrate of the second NMOS tube are grounded;
the grid Ng32 of the thirty-second NMOS transistor is connected with the C L K1, the source Ns32 is respectively connected with the sources Ps32 and D32 of the thirty-third PMOS transistor, the drain Nd32 is respectively connected with the drain Pd32 of the thirty-third PMOS transistor, the source Ns32 of the thirty-fifth NMOS transistor, the source Ps32 of the thirty-sixth PMOS transistor, the grid Ng32 of the thirty-sixth NMOS transistor, the grid Pg32 of the thirty-eighth PMOS transistor, the grid Ng32 of the thirty-eighth NMOS transistor, the grid Pg32 of the forty-fourth PMOS transistor, the grid Pg32 of the thirty-third PMOS transistor is connected with the C32K, the grid Ng32 of the thirty-third NMOS transistor is connected with the C32K 32, the source Ns32 is respectively connected with the sources 32 and D32 of the thirty-fourth PMOS transistor, the drain Pd32 of the thirty-fourth NMOS transistor, the source Ng32 of the thirty-ninth PMOS transistor, the thirty-ninth PMOS, the thirty-fourth NMOS 32, the thirty-ninth PMOS, the drain Nd32 is respectively connected with the drain Pd32, the source Ng32 of the thirty-ninth NMOS, the thirty-ninth PMOS, the thirty-fifth NMOS;
the gate Ng34 of the thirty-fourth NMOS transistor is connected with C L K, the drain Nd34 of the thirty-fifth PMOS transistor is respectively connected with the drain Pd35 of the thirty-fifth PMOS transistor, the drain Pd41 of the forty-first PMOS transistor and the drain Nd40 of the forty-NMOS transistor, the gate Pg35 of the thirty-fifth PMOS transistor is connected with C L K1, the gate Ng35 of the thirty-fifth NMOS transistor is connected with C L K, the drain Nd35 of the thirty-sixth PMOS transistor is respectively connected with the drain Pd36 of the thirty-sixth PMOS transistor, the drain Pd42 of the forty-second PMOS transistor and the drain Nd41 of the forty-NMOS transistor, and the gate Pg36 of the thirty-sixth PMOS transistor is connected with C L K1;
a source electrode Ps37 of the thirty-seventh PMOS tube is connected with a power supply VDD, and a drain electrode Pd37 is connected with a source electrode Ps38 of the thirty-eighth PMOS tube; the drain electrode Pd38 of the thirty-eighth PMOS tube is respectively connected with the drain electrode Nd36 of the thirty-sixth NMOS tube, the drain electrode Pd43 of the forty-third PMOS tube, the gate electrode Ng40 of the forty-NMOS tube, the gate electrode Pg42 of the forty-second PMOS tube, the gate electrode Pg44 of the forty-fourth PMOS tube, the gate electrode Ng42 of the forty-second NMOS tube and the second output end QN; the gate Pg43 of the forty-third PMOS tube is connected with R1, and the source Ps43 is connected with a power supply VDD; the source electrode Ns36 of the thirty-sixth NMOS transistor is connected with the drain electrode Nd37 of the thirty-seventh NMOS transistor; the source electrode Ns37 of the thirty-seventh NMOS transistor is grounded; a source electrode Ps39 of the thirty-ninth PMOS tube is connected with a power supply VDD, and a drain electrode Pd39 is connected with a source electrode Ps40 of the forty-ninth PMOS tube; the drain Pd40 of the forty-eighth PMOS tube is respectively connected with the drain Nd38 of the thirty-eighth NMOS tube, the gate Pg41 of the forty-first PMOS tube and the gate Ng41 of the forty-first NMOS tube; the source electrode Ns38 of the thirty-eighth NMOS transistor is connected with the drain electrode Nd39 of the thirty-ninth NMOS transistor; the source electrode Ns39 of the thirty-ninth NMOS tube is grounded;
the source electrode Ps41 of the forty-first PMOS tube is connected with a power supply VDD; the source electrode Ns40 of the fortieth NMOS tube is grounded; the source electrode Ps42 of the forty-second PMOS tube is connected with a power supply VDD; the source electrode Ns41 of the forty-first NMOS transistor is grounded; a source electrode Ps44 of the forty-fourth PMOS tube is connected with a power supply VDD, and a drain electrode Pd44 is respectively connected with a drain electrode Nd42 of the forty-second NMOS tube and the first output end Q; the source Ns42 of the forty-second NMOS transistor is grounded.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102394600A (en) * | 2011-10-21 | 2012-03-28 | 中国人民解放军国防科学技术大学 | Signal event upset resistance D trigger capable of being set and reset |
| CN103825579A (en) * | 2013-12-11 | 2014-05-28 | 中国人民解放军国防科学技术大学 | Resettable D trigger resisting single event upset and single event transient |
| CN103825582A (en) * | 2013-12-11 | 2014-05-28 | 中国人民解放军国防科学技术大学 | D trigger resisting single event upset and single event transient |
| CN105897223A (en) * | 2016-03-31 | 2016-08-24 | 中国人民解放军国防科学技术大学 | D trigger resistant to single event upset |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102394600A (en) * | 2011-10-21 | 2012-03-28 | 中国人民解放军国防科学技术大学 | Signal event upset resistance D trigger capable of being set and reset |
| CN103825579A (en) * | 2013-12-11 | 2014-05-28 | 中国人民解放军国防科学技术大学 | Resettable D trigger resisting single event upset and single event transient |
| CN103825582A (en) * | 2013-12-11 | 2014-05-28 | 中国人民解放军国防科学技术大学 | D trigger resisting single event upset and single event transient |
| CN105897223A (en) * | 2016-03-31 | 2016-08-24 | 中国人民解放军国防科学技术大学 | D trigger resistant to single event upset |
Non-Patent Citations (1)
| Title |
|---|
| 基于C单元反馈回路的容SEU锁存器设计;黄正峰 等;《微电子学》;20150430;第45卷(第2期);第178-183页 * |
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