CN102394597B - D trigger resisting single event upset - Google Patents
D trigger resisting single event upset Download PDFInfo
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- CN102394597B CN102394597B CN2011103226805A CN201110322680A CN102394597B CN 102394597 B CN102394597 B CN 102394597B CN 2011103226805 A CN2011103226805 A CN 2011103226805A CN 201110322680 A CN201110322680 A CN 201110322680A CN 102394597 B CN102394597 B CN 102394597B
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Abstract
The invention discloses a D trigger resisting single event upset, and aims to improve the single event upset resistance of the D trigger. The D trigger comprises a clock circuit, a main latch, a slave latch, a first phase inverter circuit and a second phase inverter circuit. the main latch comprises 10 PMOS (P-channel Metal Oxide Semiconductor) tubes and 10 NMOS (N-Mental-Oxide-Semiconductor) tubes; the slave latch comprises 10 PMOS tubes and 10 NMOS tubes; both the main latch and the slave latch adopt bimodule redundant reinforcement; and in the main latch and the slave latch, C2MOS circuits are also improved, that is, pull-up PMOS tubes and pull-down NMOS tubes in redundant relation in each C2MOS circuit are separated. The D trigger has strong single event upset resistance, is suitable for standard cell library for a reinforced integrated circuit resisting single event upset, and is used in the fields of aviation, aerospace, and the like.
Description
Technical field
The present invention relates to a kind of D master-slave flip-flop, particularly the d type flip flop of a kind of anti-single particle overturn (signal event upset).
Background technology
In cosmic space, there are a large amount of high energy particles (proton, electronics, heavy ion) and charged particle.After integrated circuit is subject to the bombardment of these high energy particles and charged particle, in integrated circuit, can produce electronic impulse, may make the original level of IC interior node overturn, this effect is called single-particle inversion (SEU).The LET(linear energy transfer of single-particle bombardment integrated circuit) value is higher, and the electronic impulse of generation is stronger.The integrated circuit used in the Aeronautics and Astronautics field all can be subject to the threat of single-particle inversion, makes the integrated circuit job insecurity, even produces fatal mistake, therefore develops advanced integrated circuit anti-single particle overturn reinforcement technique particularly important.
The anti-single particle overturn reinforcement technique of integrated circuit can be divided into system-level reinforcing, the circuit level is reinforced and device level is reinforced.The IC reliability of system-level reinforcing is high, but chip area is large, power consumption is large, the speed of service is slow.The integrated circuit speed of service that device level is reinforced is fast, and chip area is little, low in energy consumption, but the device level reinforcing realizes that difficulty is large, and cost is high.The IC reliability that the circuit level is reinforced is high, chip area, power consumption and the speed of service are better than the integrated circuit of system-level reinforcing, and realizing that difficulty and cost are less than the integrated circuit that device level is reinforced, is very important integrated circuit anti-single particle overturn reinforcement means.
D type flip flop is to use one of maximum unit in sequential logical circuit, and its anti-single particle overturn ability has directly determined the anti-single particle overturn ability of integrated circuit.D type flip flop is carried out to the circuit level and reinforce the anti-single particle overturn ability that can under less chip area, power consumption and cost, effectively improve integrated circuit.
Traditional d type flip flop is D master-slave flip-flop, generally by the main latch with from the level series of latches, forms, and it is the effective ways of realizing that the d type flip flop anti-single particle is reinforced that the anti-single particle overturn of latch is reinforced.The people such as T.Clain are at IEEE Transaction on Nuclear Science(IEEE atomic energy science journal) on " Upset Hardened Memory Design for Submicron CMOS Technology " (the memory cell design is reinforced in upset under the submicron CMOS technology) (December in 1996 the 6th phases 43 volume of delivering, 2874th～2878 pages) latch that a kind of redundancy is reinforced proposed, this latch has increased an inverter and a feedback loop on the basis of classical latch structure, with original inverter and feedback loop redundant circuit each other.In inverter, the input of N pipe separates with the input of P pipe, connects respectively two feedback loops, C in feedback loop
2the input of the N of MOS circuit pipe and P pipe is respectively from the output of two inverters.Signal input and the signal of this latch are preserved by C
2the MOS clock circuit is controlled.The latch advantage that this redundancy is reinforced is: the trigging signal produced while bombarding a node can return to original state by the correct level of corresponding node in its redundant circuit.The deficiency of the latch that this redundancy is reinforced is: two of inputs are the C of redundancy each other
2the MOS circuit draws PMOS pipe and a pull-down NMOS pipe on sharing one, make C in feedback loop
2there is an indirect pathway between the output node of MOS circuit and redundant circuit corresponding node, when the single-particle bombardment makes this C
2the level upset of MOS circuit output node, this trigging signal can propagate into along indirect pathway the corresponding node of redundant circuit, if the LET value of single-particle bombardment is higher, two each other the circuit of redundancy level all can occur overturns, finally make the output of latch also overturn.The d type flip flop that traditional redundancy that the series of latches of being reinforced by two this kind of redundancies forms is reinforced, the LET value of bombarding when single-particle is higher, two each other the circuit of redundancy level upset also all can occur, finally make the output of the d type flip flop that traditional redundancy reinforces also overturn.The people such as R.Naseer are in the48th IEEE International Midwest Symposium on Circuits the 48th IEEE circuit of and Systems(and the international conference of system Midwest) on " The DF-DICE Storage Element for Immunity to Soft Errors " (to the DF-DICE memory cell of soft error immunity) delivered the latch that the similar redundancy of a kind of and above-mentioned latch structure is reinforced has also been proposed.Two C of this latch input
2the MOS circuit is fully independently, two each other in the circuit of redundancy corresponding node do not have indirect pathway, overcome the weak point of the latch that redundancy that the people such as T.Clain propose reinforces.But the latch that the redundancy that the people such as R.Naseer propose is reinforced has used passgate structures in feedback loop, when a node is subject to the single-particle bombardment that upset occurs, its redundant circuit feeds back to this node by correct level by transmission gate.Because the noise margin of passgate structures is lower, the signal feedback ability of feedback loop a little less than, when the LET value of single-particle bombardment is higher, feedback loop can not make this node recover correct level, has had a strong impact on this latch anti-single particle overturn ability.The d type flip flop that traditional redundancy that the series of latches of being reinforced by two this kind of redundancies forms is reinforced, when the LET value of single-particle bombardment is higher, also can be because of the passgate structures in feedback loop, can not make this node recover correct level, affect the d type flip flop anti-single particle overturn ability that this tradition redundancy is reinforced.
The Chinese patent that the patent No. is CN101499788A discloses the d type flip flop of a kind of anti-single particle overturn and single event transient pulse.This invention is the d type flip flop that a kind of structure is similar to the time sampling structure, comprises two variable connectors, two delay circuits, two shutter circuit and three inverters, has realized that the anti-single particle overturn of d type flip flop is reinforced.Owing to adopting delay circuit and shutter circuit to shield the electronic impulse that bombardment produces; when the LET value of single-particle bombardment is higher; the electronic impulse width can be greater than the time of delay of delay circuit; the output level of shutter circuit is overturn, greatly reduce the anti-single particle overturn ability of this d type flip flop.
Summary of the invention
The technical problem to be solved in the present invention is, for the not high problem of current primary particle inversion resistant d type flip flop anti-single particle overturn ability, propose a kind of primary particle inversion resistant d type flip flop, it can work and not produce single-particle inversion under the single-particle bombardment of higher LET value.
The primary particle inversion resistant d type flip flop that the present invention proposes is by clock circuit, main latch, form from latch, the first inverter circuit and the second inverter circuit.
The primary particle inversion resistant d type flip flop of the present invention has two inputs and two outputs.Two inputs are respectively that CK is that clock signal input part and D are the data-signal input; Two outputs are respectively Q and QN, Q and a pair of contrary data-signal of QN output.
Clock circuit has an input and two outputs, and input is CK, and output is C, CN.Clock circuit is a two-stage inverter, first order inverter and second level inverter, consists of; First order inverter is comprised of a PMOS pipe and a NMOS pipe, and the grid Pg1 of a PMOS pipe connects CK, the drain electrode Nd1 of drain electrode Pd1 connection the one NMOS pipe, and as an output CN of clock circuit.The grid Ng1 of the one NMOS pipe connects CK, and drain electrode Nd1 connects Pd1; Second level inverter is comprised of the 2nd PMOS pipe and the 2nd NMOS pipe, and the grid Pg2 of the 2nd PMOS pipe connects CN, the drain electrode Nd2 of drain electrode Pd2 connection the 2nd NMOS pipe, and as another output C of clock circuit.The grid Ng2 of the 2nd NMOS pipe connects CN, and drain electrode Nd2 connects Pd2.The one PMOS pipe is connected power vd D with the substrate of the 2nd PMOS pipe, and source electrode Ps1, Ps2 connect power vd D; The substrate ground connection VSS of the one NMOS pipe and the 2nd NMOS pipe, source electrode Ns1, Ns2 be ground connection VSS also.
Main latch and be the latch that redundancy is reinforced from latch.Main latch and from series connection before and after latch, and all with clock circuit, be connected.From latch, also with the first inverter circuit, with the second inverter circuit, be connected respectively.
Main latch has three inputs and an output, and three inputs are D, C, CN, and an output is MO.Main latch is comprised of ten PMOS pipes and ten NMOS pipes, and in main latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg3 of the 3rd PMOS pipe connects D, and drain electrode Pd3 connects the source electrode Ps4 of the 4th PMOS pipe, and source electrode Ps3 connects power vd D; The grid Pg4 of the 4th PMOS pipe connects C, and drain electrode Pd4 connects the drain electrode Nd3 of the 3rd NMOS pipe, and source electrode Ps4 connects Pd3; The grid Pg5 of the 5th PMOS pipe connects D, and drain electrode Pd5 connects the source electrode Ps6 of the 6th PMOS pipe, and source electrode Ps5 connects power vd D; The grid Pg6 of the 6th PMOS pipe connects C, and drain electrode Pd6 connects the drain electrode Nd5 of the 5th NMOS pipe, and source electrode Ps6 connects Pd5; The grid Pg7 of the 7th PMOS pipe connects Pd6, and drain electrode Pd7 connects the drain electrode Nd7 of the 7th NMOS pipe and, as the output MO of main latch, source electrode Ps7 connects power vd D; The grid Pg8 of the 8th PMOS pipe connects Pd4, and drain electrode Pd8 connects the drain electrode Nd8 of the 8th NMOS pipe, and source electrode Ps8 connects power vd D; The grid Pg9 of the 9th PMOS pipe connects Pd8, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS pipe, and source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects CN, and drain electrode Pd10 connects the drain electrode Nd9 of the 9th NMOS pipe, and source electrode Ps10 connects Pd9; The grid Pg11 of the 11 PMOS pipe connects Pd7, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects CN, and drain electrode Pd12 connects the drain electrode Nd11 of the 11 NMOS pipe, and source electrode Ps12 connects Pd11; The grid Ng3 of the 3rd NMOS pipe connects CN, and drain electrode Nd3 connects Pd4, and source electrode Ns3 connects the drain electrode Nd4 of the 4th NMOS pipe; The grid Ng4 of the 4th NMOS pipe connects D, and drain electrode Nd4 connects Ns3, source electrode Ns4 ground connection VSS; The grid Ng5 of the 5th NMOS pipe connects CN, and drain electrode Nd5 connects Pd6, and source electrode Ns5 connects the drain electrode Nd6 of the 6th NMOS pipe; The grid Ng6 of the 6th NMOS pipe connects D, and drain electrode Nd6 connects Ns5, source electrode Ns6 ground connection VSS; The grid Ng7 of the 7th NMOS pipe connects Pd4, and drain electrode Nd7 connects Pd7, source electrode Ns7 ground connection VSS; The grid Ng8 of the 8th NMOS pipe connects Pd6, and drain electrode Nd8 connects Pd8, source electrode Ns8 ground connection VSS; The grid Ng9 of the 9th NMOS pipe connects C, and drain electrode Nd9 connects Pd10, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe; The grid Ng10 of the tenth NMOS pipe connects Pd7, and drain electrode Nd10 connects Ns9, source electrode Ns10 ground connection VSS; The grid Ng11 of the 11 NMOS pipe connects C, and drain electrode Nd11 connects Pd12, and source electrode Ns11 connects the drain electrode Nd12 of the 12 NMOS pipe; The grid Ng12 of the 12 NMOS pipe connects Pd8, and drain electrode Nd12 connects Ns11, source electrode Ns12 ground connection VSS.
From latch, three inputs and two outputs are arranged, three inputs are MO, C, CN, and two outputs are SO, SON.From latch, ten PMOS pipes and ten NMOS pipes, consist of, from latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg13 of the 13 PMOS pipe connects MO, and drain electrode Pd13 connects the source electrode Ps14 of the 14 PMOS pipe, and source electrode Ps13 connects power vd D; The grid Pg14 of the 14 PMOS pipe connects CN, and drain electrode Pd14 connects the drain electrode Nd13 of the 13 NMOS pipe, and source electrode connects Pd13; The grid Pg15 of the 15 PMOS pipe connects MO, and drain electrode Pd15 connects the source electrode Ps16 of the 16 PMOS pipe, and source electrode Ps15 connects power vd D; The grid Pg16 of the 16 PMOS pipe connects CN, and drain electrode Pd16 connects the drain electrode Nd15 of the 15 NMOS pipe, and source electrode connects Pd15; The grid Pg17 of the 17 PMOS pipe connects Pd16, and drain electrode Pd17 connects the drain electrode Nd17 of the 17 NMOS pipe and, as the output SO from latch, source electrode Ps17 connects power vd D; The grid Pg18 of the 18 PMOS pipe connects Pd14, and drain electrode Pd18 connects the drain electrode Nd18 of the 18 NMOS pipe, and source electrode Ps18 connects power vd D; The grid Pg19 of the 19 PMOS pipe connects Pd18, and drain electrode Pd19 connects the source electrode Ps20 of the 20 PMOS pipe, and source electrode Ps19 connects power vd D; The grid Pg20 of the 20 PMOS pipe connects C, and drain electrode Pd20 connects the drain electrode Nd19 of the 19 NMOS pipe, and source electrode Ps20 connects Pd19; The grid Pg21 of the 21 PMOS pipe connects Pd17, and drain electrode Pd21 connects the source electrode Ps22 of the 22 PMOS pipe, and source electrode Ps21 connects power vd D; The grid Pg22 of the 22 PMOS pipe connects C, and drain electrode Pd22 connects the drain electrode Nd21 of the 21 NMOS pipe and, as another output SON from latch, source electrode Ps22 connects Pd21; The grid Ng13 of the 13 NMOS pipe connects C, and drain electrode Nd13 connects Pd14, and source electrode Ns13 connects the drain electrode Nd14 of the 14 NMOS pipe; The grid Ng14 of the 14 NMOS pipe connects MO, and drain electrode Nd14 connects Ns13, source electrode Ns14 ground connection VSS; The grid Ng15 of the 15 NMOS pipe connects C, and drain electrode Nd15 connects Pd16, and source electrode Ns15 connects the drain electrode Nd16 of the 16 NMOS pipe; The grid Ng16 of the 16 NMOS pipe connects MO, and drain electrode Nd16 connects Ns15, source electrode Ns16 ground connection VSS; The grid Ng17 of the 17 NMOS pipe connects Pd14, and drain electrode Nd17 connects Pd17, source electrode Ns17 ground connection VSS; The grid Ng18 of the 18 NMOS pipe connects Pd16, and drain electrode Nd18 connects Pd18, source electrode Ns18 ground connection VSS; The grid Ng19 of the 19 NMOS pipe connects CN, and drain electrode Nd19 connects Pd20, and source electrode Ns19 connects the drain electrode Nd20 of the 20 NMOS pipe; The grid Ng20 of the 20 NMOS pipe connects Pd17, and drain electrode Nd20 connects Ns19, source electrode Ns20 ground connection VSS; The grid Ng21 of the 21 NMOS pipe connects CN, and drain electrode Nd21 connects Pd22, and source electrode Ns21 connects the drain electrode Nd22 of the 22 NMOS pipe; The grid Ng22 of the 22 NMOS pipe connects Pd18, and drain electrode Nd22 connects Ns21, source electrode Ns22 ground connection VSS.
The first inverter circuit has an input and an output, and input is SO, and output is QN.The first inverter circuit is comprised of the 23 PMOS pipe and the 23 NMOS pipe.The substrate of the 23 PMOS pipe all is connected power vd D with source electrode Ps23, the equal ground connection VSS of the substrate of the 23 NMOS pipe and source electrode Ns23.The grid Pg23 of the 23 PMOS pipe connects SO, and drain electrode Pd23 connects the drain electrode Nd23 of the 23 NMOS pipe, and as the output QN of the first inverter circuit; The grid Ng23 of the 23 NMOS pipe connects SO, and drain electrode Nd23 connects Pd23.
The second inverter circuit has an input and an output, and input is SON, and output is Q.The second inverter circuit is comprised of the 24 PMOS pipe and the 24 NMOS pipe.The substrate of the 24 PMOS pipe all is connected power vd D with source electrode Ps24, the equal ground connection VSS of the substrate of the 24 NMOS pipe and source electrode Ns24.The grid Pg24 of the 24 PMOS pipe connects SON, and drain electrode Pd24 connects the drain electrode Nd24 of the 24 NMOS pipe, and as the output Q of the second inverter circuit; The grid Ng24 of the 24 NMOS pipe connects SON, and drain electrode Nd24 connects Pd24.
The primary particle inversion resistant d type flip flop course of work of the present invention is as follows:
Clock circuit receives CK, after it is cushioned, produce respectively the CN anti-phase with CK and with the C of CK homophase, and CN with C is passed to main latch and from latch.At CK, be between low period, CN is that high level, C are low level, and main latch is opened, and receives D and it is carried out to the MO of output and D homophase after buffered,, do not receive the MO of main latch output but preserve the MO that a CK trailing edge samples in preservation state from latch; At CK, be between high period, CN is that low level, C are high level, main latch is in preservation state, preserve the MO of D that previous CK rising edge samples output and D homophase, open and receive the output MO of main latch from latch, MO is carried out to buffered output and the SO of MO homophase and the SON anti-phase with MO.The first inverter circuit all will receive the output SO from latch at any time, to SO buffering output and the anti-phase QN of SO.The second inverter circuit all will receive the output SON from latch at any time, to SON buffering output and the anti-phase Q of SON.
Adopt the present invention can reach following technique effect:
The anti-single particle overturn ability of the primary particle inversion resistant d type flip flop of the present invention is better than the d type flip flop of the unguyed d type flip flop of tradition, time sampling reinforcing and the d type flip flop that traditional redundancy is reinforced.Because the present invention's d type flip flop structure unguyed to tradition transformed, all carried out the duplication redundancy reinforcing to main latch with from latch, and for main latch and from latch C
2the MOS circuit improves, and separates the C of redundancy each other
2draw PMOS pipe and pull-down NMOS pipe in the MOS circuit, further improved the anti-single particle overturn ability of the primary particle inversion resistant d type flip flop of the present invention.The primary particle inversion resistant d type flip flop of the present invention is suitable for the standard cell lib that anti-single particle overturn is reinforced integrated circuit, is applied to the fields such as Aeronautics and Astronautics.
The accompanying drawing explanation
Fig. 1 is the primary particle inversion resistant d type flip flop logical construction of the present invention schematic diagram.
Fig. 2 is clock circuit structural representation in the primary particle inversion resistant d type flip flop of the present invention.
Fig. 3 is main latch structural representation in the primary particle inversion resistant d type flip flop of the present invention.
Fig. 4 is from the latch structure schematic diagram in the primary particle inversion resistant d type flip flop of the present invention.
Fig. 5 is the first inverter circuit structure schematic diagram in the primary particle inversion resistant d type flip flop of the present invention.
Fig. 6 is the second inverter circuit structure schematic diagram in the primary particle inversion resistant d type flip flop of the present invention.
Embodiment
Fig. 1 is the primary particle inversion resistant d type flip flop logical construction of the present invention schematic diagram.The present invention is by clock circuit (as shown in Figure 2), main latch (as shown in Figure 3), form from latch (as shown in Figure 4), the first inverter circuit (as shown in Figure 5) and the second inverter circuit (as shown in Figure 6).The present invention has two inputs and two outputs.Two inputs are respectively that CK is that clock signal input part and D are the data-signal input; Two outputs are respectively Q and QN, Q and a pair of contrary data-signal of QN output.Clock circuit receives CK, and CK is carried out exporting respectively C and CN after buffered.Main latch receives D and C and CN, and main latch is latched and processes rear output MO D under the control of C and CN.Receive MO and C and CN from latch, export respectively SO, SON after under the control of C and CN, MO being latched to processing from latch.The first inverter circuit receives SO, and it is carried out exporting QN after buffered.The second inverter circuit receives SON, and it is carried out exporting Q after buffered.
As shown in Figure 2, clock circuit has an input and two outputs, and input is CK, and output is C, CN.Clock circuit is a two-stage inverter, and first order inverter is comprised of a PMOS pipe and a NMOS pipe, and the grid Pg1 of a PMOS pipe connects CK, the drain electrode Nd1 of drain electrode Pd1 connection the one NMOS pipe, and as an output CN of clock circuit.The grid Ng1 of the one NMOS pipe connects CK, and drain electrode Nd1 connects Pd1; Second level inverter is comprised of the 2nd PMOS pipe and the 2nd NMOS pipe, and the grid Pg2 of the 2nd PMOS pipe connects CN, the drain electrode Nd2 of drain electrode Pd2 connection the 2nd NMOS pipe, and as another output C of clock circuit.The grid Ng2 of the 2nd NMOS pipe connects CN, and drain electrode Nd2 connects Pd2.The one PMOS pipe is connected power vd D with the substrate of the 2nd PMOS pipe, and source electrode Ps1, Ps2 connect power vd D; The substrate ground connection VSS of the one NMOS pipe and the 2nd NMOS pipe, source electrode Ns1, Ns2 be ground connection VSS also.
As shown in Figure 3, main latch has three inputs and an output, and three inputs are D, C, CN, and an output is MO.Main latch is comprised of ten PMOS pipes and ten NMOS pipes, and in main latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg3 of the 3rd PMOS pipe connects D, and drain electrode Pd3 connects the source electrode Ps4 of the 4th PMOS pipe, and source electrode Ps3 connects power vd D; The grid Pg4 of the 4th PMOS pipe connects C, and drain electrode Pd4 connects the drain electrode Nd3 of the 3rd NMOS pipe, and source electrode Ps4 connects Pd3; The grid Pg5 of the 5th PMOS pipe connects D, and drain electrode Pd5 connects the source electrode Ps6 of the 6th PMOS pipe, and source electrode Ps5 connects power vd D; The grid Pg6 of the 6th PMOS pipe connects C, and drain electrode Pd6 connects the drain electrode Nd5 of the 5th NMOS pipe, and source electrode Ps6 connects Pd5; The grid Pg7 of the 7th PMOS pipe connects Pd6, and drain electrode Pd7 connects the drain electrode Nd7 of the 7th NMOS pipe and, as the output MO of main latch, source electrode Ps7 connects power vd D; The grid Pg8 of the 8th PMOS pipe connects Pd4, and drain electrode Pd8 connects the drain electrode Nd8 of the 8th NMOS pipe, and source electrode Ps8 connects power vd D; The grid Pg9 of the 9th PMOS pipe connects Pd8, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS pipe, and source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects CN, and drain electrode Pd10 connects the drain electrode Nd9 of the 9th NMOS pipe, and source electrode Ps10 connects Pd9; The grid Pg11 of the 11 PMOS pipe connects Pd7, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects CN, and drain electrode Pd12 connects the drain electrode Nd11 of the 11 NMOS pipe, and source electrode Ps12 connects Pd11; The grid Ng3 of the 3rd NMOS pipe connects CN, and drain electrode Nd3 connects Pd4, and source electrode Ns3 connects the drain electrode Nd4 of the 4th NMOS pipe; The grid Ng4 of the 4th NMOS pipe connects D, and drain electrode Nd4 connects Ns3, source electrode Ns4 ground connection VSS; The grid Ng5 of the 5th NMOS pipe connects CN, and drain electrode Nd5 connects Pd6, and source electrode Ns5 connects the drain electrode Nd6 of the 6th NMOS pipe; The grid Ng6 of the 6th NMOS pipe connects D, and drain electrode Nd6 connects Ns5, source electrode Ns6 ground connection VSS; The grid Ng7 of the 7th NMOS pipe connects Pd4, and drain electrode Nd7 connects Pd7, source electrode Ns7 ground connection VSS; The grid Ng8 of the 8th NMOS pipe connects Pd6, and drain electrode Nd8 connects Pd8, source electrode Ns8 ground connection VSS; The grid Ng9 of the 9th NMOS pipe connects C, and drain electrode Nd9 connects Pd10, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe; The grid Ng10 of the tenth NMOS pipe connects Pd7, and drain electrode Nd10 connects Ns9, source electrode Ns10 ground connection VSS; The grid Ng11 of the 11 NMOS pipe connects C, and drain electrode Nd11 connects Pd12, and source electrode Ns11 connects the drain electrode Nd12 of the 12 NMOS pipe; The grid Ng12 of the 12 NMOS pipe connects Pd8, and drain electrode Nd12 connects Ns11, source electrode Ns12 ground connection VSS.
As shown in Figure 4, from latch, three inputs and two outputs are arranged, three inputs are MO, C, CN, and two outputs are SO, SON.From latch, ten PMOS pipes and ten NMOS pipes, consist of, from latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg13 of the 13 PMOS pipe connects MO, and drain electrode Pd13 connects the source electrode Ps14 of the 14 PMOS pipe, and source electrode Ps13 connects power vd D; The grid Pg14 of the 14 PMOS pipe connects CN, and drain electrode Pd14 connects the drain electrode Nd13 of the 13 NMOS pipe, and source electrode connects Pd13; The grid Pg15 of the 15 PMOS pipe connects MO, and drain electrode Pd15 connects the source electrode Ps16 of the 16 PMOS pipe, and source electrode Ps15 connects power vd D; The grid Pg16 of the 16 PMOS pipe connects CN, and drain electrode Pd16 connects the drain electrode Nd15 of the 15 NMOS pipe, and source electrode connects Pd15; The grid Pg17 of the 17 PMOS pipe connects Pd16, and drain electrode Pd17 connects the drain electrode Nd17 of the 17 NMOS pipe and, as the output SO from latch, source electrode Ps17 connects power vd D; The grid Pg18 of the 18 PMOS pipe connects Pd14, and drain electrode Pd18 connects the drain electrode Nd18 of the 18 NMOS pipe, and source electrode Ps18 connects power vd D; The grid Pg19 of the 19 PMOS pipe connects Pd18, and drain electrode Pd19 connects the source electrode Ps20 of the 20 PMOS pipe, and source electrode Ps19 connects power vd D; The grid Pg20 of the 20 PMOS pipe connects C, and drain electrode Pd20 connects the drain electrode Nd19 of the 19 NMOS pipe, and source electrode Ps20 connects Pd19; The grid Pg21 of the 21 PMOS pipe connects Pd17, and drain electrode Pd21 connects the source electrode Ps22 of the 22 PMOS pipe, and source electrode Ps21 connects power vd D; The grid Pg22 of the 22 PMOS pipe connects C, and drain electrode Pd22 connects the drain electrode Nd21 of the 21 NMOS pipe and, as another output SON from latch, source electrode Ps22 connects Pd21; The grid Ng13 of the 13 NMOS pipe connects C, and drain electrode Nd13 connects Pd14, and source electrode Ns13 connects the drain electrode Nd14 of the 14 NMOS pipe; The grid Ng14 of the 14 NMOS pipe connects MO, and drain electrode Nd14 connects Ns13, source electrode Ns14 ground connection VSS; The grid Ng15 of the 15 NMOS pipe connects C, and drain electrode Nd15 connects Pd16, and source electrode Ns15 connects the drain electrode Nd16 of the 16 NMOS pipe; The grid Ng16 of the 16 NMOS pipe connects MO, and drain electrode Nd16 connects Ns15, source electrode Ns16 ground connection VSS; The grid Ng17 of the 17 NMOS pipe connects Pd14, and drain electrode Nd17 connects Pd17, source electrode Ns17 ground connection VSS; The grid Ng18 of the 18 NMOS pipe connects Pd16, and drain electrode Nd18 connects Pd18, source electrode Ns18 ground connection VSS; The grid Ng19 of the 19 NMOS pipe connects CN, and drain electrode Nd19 connects Pd20, and source electrode Ns19 connects the drain electrode Nd20 of the 20 NMOS pipe; The grid Ng20 of the 20 NMOS pipe connects Pd17, and drain electrode Nd20 connects Ns19, source electrode Ns20 ground connection VSS; The grid Ng21 of the 21 NMOS pipe connects CN, and drain electrode Nd21 connects Pd22, and source electrode Ns21 connects the drain electrode Nd22 of the 22 NMOS pipe; The grid Ng22 of the 22 NMOS pipe connects Pd18, and drain electrode Nd22 connects Ns21, source electrode Ns22 ground connection VSS.
As shown in Figure 5, the first inverter circuit has an input and an output, and input is SO, and output is QN.The first inverter circuit is comprised of the 23 PMOS pipe and the 23 NMOS pipe.The substrate of the 23 PMOS pipe all is connected power vd D with source electrode Ps23, the equal ground connection VSS of the substrate of the 23 NMOS pipe and source electrode Ns23.The grid Pg23 of the 23 PMOS pipe connects SO, and drain electrode Pd23 connects the drain electrode Nd23 of the 23 NMOS pipe, and as the output QN of the first inverter circuit; The grid Ng23 of the 23 NMOS pipe connects SO, and drain electrode Nd23 connects Pd23.
As shown in Figure 6, the second inverter circuit has an input and an output, and input is SON, and output is Q.The second inverter circuit is comprised of the 24 PMOS pipe and the 24 NMOS pipe.The substrate of the 24 PMOS pipe all is connected power vd D with source electrode Ps24, the equal ground connection VSS of the substrate of the 24 NMOS pipe and source electrode Ns24.The grid Pg24 of the 24 PMOS pipe connects SON, and drain electrode Pd24 connects the drain electrode Nd24 of the 24 NMOS pipe, and as the output Q of the second inverter circuit; The grid Ng24 of the 24 NMOS pipe connects SON, and drain electrode Nd24 connects Pd24.
The H-13 of Beijing Institute of Atomic Energy tandem accelerator can produce the LET value and be respectively 2.88MeVcm
2/ mg, 8.62MeVcm
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2four kinds of ground heavy ion irradiation test environments of/mg.The LET value that the d type flip flop that the d type flip flop that d type flip flop that will be unguyed in the tradition of normal operating conditions, traditional redundancy are reinforced, time sampling are reinforced and the primary particle inversion resistant d type flip flop of the present invention are placed in the generation of the H-13 of Beijing Institute of Atomic Energy tandem accelerator is respectively 2.88MeVcm
2/ mg, 8.62MeVcm
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2in the ground heavy ion irradiation test environment of/mg, observe each d type flip flop whether single-particle inversion occurs, obtain the minimum LET Value Data that each d type flip flop generation single-particle inversion needs.D type flip flop, the d type flip flop that traditional redundancy is reinforced, the d type flip flop of time sampling reinforcing and the minimum LET Value Data that the primary particle inversion resistant d type flip flop generation of the present invention single-particle inversion needs that the tradition that the ground heavy particle irradiation test that table 1 carries out for the use H-13 of Beijing Institute of Atomic Energy tandem accelerator obtains is unguyed.The unguyed d type flip flop of tradition is 2.88MeVcm in the LET value
2/ mg, 8.62MeVcm
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2single-particle inversion all occurs while working in the ground heavy ion irradiation test environment of/mg, and the d type flip flop that traditional redundancy is reinforced is 12.6MeVcm in the LET value
2/ mg and 17.0MeVcm
2single-particle inversion occurs while working in the ground heavy ion irradiation test environment of/mg, and the d type flip flop that time sampling is reinforced is 8.62MeVcm in the LET value
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2single-particle inversion occurs while working in the ground heavy ion irradiation test environment of/mg, and the primary particle inversion resistant d type flip flop of the present invention is only 17.0MeVcm in the LET value
2single-particle inversion occurs in the ground heavy ion irradiation test environment of/mg while working.From then on table can be found out, the minimum LET value that generation single-particle inversion of the present invention the needs d type flip flop more unguyed than tradition improves 343%, the d type flip flop of reinforcing than traditional redundancy improves 35%, the d type flip flop of reinforcing than time sampling improves 97%, therefore anti-single particle overturn ability of the present invention is better than the d type flip flop of the unguyed d type flip flop of tradition, time sampling reinforcing and the d type flip flop that traditional redundancy is reinforced, be suitable for anti-single particle overturn and reinforce the standard cell lib of integrated circuit, be applied to the fields such as Aeronautics and Astronautics.
Table 1
Claims (1)
1. a primary particle inversion resistant d type flip flop, primary particle inversion resistant d type flip flop by clock circuit, main latch, form from latch, the first inverter circuit and the second inverter circuit, has two inputs and two outputs; Two inputs are respectively that CK is that clock signal input part and D are the data-signal input; Two outputs are respectively Q and QN, Q and a pair of contrary data-signal of QN output; Clock circuit has an input and two outputs, and input is CK, and output is C, CN; Clock circuit is a two-stage inverter, first order inverter and second level inverter, consists of; First order inverter is comprised of a PMOS pipe and a NMOS pipe, and the grid Pg1 of a PMOS pipe connects CK, the drain electrode Nd1 of drain electrode Pd1 connection the one NMOS pipe, and as an output CN of clock circuit; The grid Ng1 of the one NMOS pipe connects CK, and drain electrode Nd1 connects Pd1; Second level inverter is comprised of the 2nd PMOS pipe and the 2nd NMOS pipe, and the grid Pg2 of the 2nd PMOS pipe connects CN, the drain electrode Nd2 of drain electrode Pd2 connection the 2nd NMOS pipe, and as another output C of clock circuit; The grid Ng2 of the 2nd NMOS pipe connects CN, and drain electrode Nd2 connects Pd2; The one PMOS pipe is connected power vd D with the substrate of the 2nd PMOS pipe, and source electrode Ps1, Ps2 connect power vd D; The substrate ground connection VSS of the one NMOS pipe and the 2nd NMOS pipe, source electrode Ns1, Ns2 be ground connection VSS also; The first inverter circuit has an input and an output, and input is SO, and output is QN; The first inverter circuit is comprised of the 23 PMOS pipe and the 23 NMOS pipe; The substrate of the 23 PMOS pipe all is connected power vd D with source electrode Ps23, the equal ground connection VSS of the substrate of the 23 NMOS pipe and source electrode Ns23; The grid Pg23 of the 23 PMOS pipe connects SO, and drain electrode Pd23 connects the drain electrode Nd23 of the 23 NMOS pipe, and as the output QN of the first inverter circuit; The grid Ng23 of the 23 NMOS pipe connects SO, and drain electrode Nd23 connects Pd23; The second inverter circuit has an input and an output, and input is SON, and output is Q; The second inverter circuit is comprised of the 24 PMOS pipe and the 24 NMOS pipe; The substrate of the 24 PMOS pipe all is connected power vd D with source electrode Ps24, the equal ground connection VSS of the substrate of the 24 NMOS pipe and source electrode Ns24; The grid Pg24 of the 24 PMOS pipe connects SON, and drain electrode Pd24 connects the drain electrode Nd24 of the 24 NMOS pipe, and as the output Q of the second inverter circuit; The grid Ng24 of the 24 NMOS pipe connects SON, and drain electrode Nd24 connects Pd24; Main latch and be the latch that redundancy is reinforced from latch, main latch and from series connection before and after latch, and all with clock circuit, be connected, from latch, also with the first inverter circuit, with the second inverter circuit, be connected respectively; It is characterized in that having three inputs and an output, three inputs are D, C, CN, and an output is MO; Main latch is comprised of ten PMOS pipes and ten NMOS pipes, and in main latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg3 of the 3rd PMOS pipe connects D, and drain electrode Pd3 connects the source electrode Ps4 of the 4th PMOS pipe, and source electrode Ps3 connects power vd D; The grid Pg4 of the 4th PMOS pipe connects C, and drain electrode Pd4 connects the drain electrode Nd3 of the 3rd NMOS pipe, and source electrode Ps4 connects Pd3; The grid Pg5 of the 5th PMOS pipe connects D, and drain electrode Pd5 connects the source electrode Ps6 of the 6th PMOS pipe, and source electrode Ps5 connects power vd D; The grid Pg6 of the 6th PMOS pipe connects C, and drain electrode Pd6 connects the drain electrode Nd5 of the 5th NMOS pipe, and source electrode Ps6 connects Pd5; The grid Pg7 of the 7th PMOS pipe connects Pd6, and drain electrode Pd7 connects the drain electrode Nd7 of the 7th NMOS pipe and, as the output MO of main latch, source electrode Ps7 connects power vd D; The grid Pg8 of the 8th PMOS pipe connects Pd4, and drain electrode Pd8 connects the drain electrode Nd8 of the 8th NMOS pipe, and source electrode Ps8 connects power vd D; The grid Pg9 of the 9th PMOS pipe connects Pd8, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS pipe, and source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects CN, and drain electrode Pd10 connects the drain electrode Nd9 of the 9th NMOS pipe, and source electrode Ps10 connects Pd9; The grid Pg11 of the 11 PMOS pipe connects Pd7, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects CN, and drain electrode Pd12 connects the drain electrode Nd11 of the 11 NMOS pipe, and source electrode Ps12 connects Pd11; The grid Ng3 of the 3rd NMOS pipe connects CN, and drain electrode Nd3 connects Pd4, and source electrode Ns3 connects the drain electrode Nd4 of the 4th NMOS pipe; The grid Ng4 of the 4th NMOS pipe connects D, and drain electrode Nd4 connects Ns3, source electrode Ns4 ground connection VSS; The grid Ng5 of the 5th NMOS pipe connects CN, and drain electrode Nd5 connects Pd6, and source electrode Ns5 connects the drain electrode Nd6 of the 6th NMOS pipe; The grid Ng6 of the 6th NMOS pipe connects D, and drain electrode Nd6 connects Ns5, source electrode Ns6 ground connection VSS; The grid Ng7 of the 7th NMOS pipe connects Pd4, and drain electrode Nd7 connects Pd7, source electrode Ns7 ground connection VSS; The grid Ng8 of the 8th NMOS pipe connects Pd6, and drain electrode Nd8 connects Pd8, source electrode Ns8 ground connection VSS; The grid Ng9 of the 9th NMOS pipe connects C, and drain electrode Nd9 connects Pd10, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe; The grid Ng10 of the tenth NMOS pipe connects Pd7, and drain electrode Nd10 connects Ns9, source electrode Ns10 ground connection VSS; The grid Ng11 of the 11 NMOS pipe connects C, and drain electrode Nd11 connects Pd12, and source electrode Ns11 connects the drain electrode Nd12 of the 12 NMOS pipe; The grid Ng12 of the 12 NMOS pipe connects Pd8, and drain electrode Nd12 connects Ns11, source electrode Ns12 ground connection VSS; From latch, three inputs and two outputs are arranged, three inputs are MO, C, CN, and two outputs are SO, SON; From latch, ten PMOS pipes and ten NMOS pipes, consist of, from latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg13 of the 13 PMOS pipe connects MO, and drain electrode Pd13 connects the source electrode Ps14 of the 14 PMOS pipe, and source electrode Ps13 connects power vd D; The grid Pg14 of the 14 PMOS pipe connects CN, and drain electrode Pd14 connects the drain electrode Nd13 of the 13 NMOS pipe, and source electrode connects Pd13; The grid Pg15 of the 15 PMOS pipe connects MO, and drain electrode Pd15 connects the source electrode Ps16 of the 16 PMOS pipe, and source electrode Ps15 connects power vd D; The grid Pg16 of the 16 PMOS pipe connects CN, and drain electrode Pd16 connects the drain electrode Nd15 of the 15 NMOS pipe, and source electrode connects Pd15; The grid Pg17 of the 17 PMOS pipe connects Pd16, and drain electrode Pd17 connects the drain electrode Nd17 of the 17 NMOS pipe and, as the output SO from latch, source electrode Ps17 connects power vd D; The grid Pg18 of the 18 PMOS pipe connects Pd14, and drain electrode Pd18 connects the drain electrode Nd18 of the 18 NMOS pipe, and source electrode Ps18 connects power vd D; The grid Pg19 of the 19 PMOS pipe connects Pd18, and drain electrode Pd19 connects the source electrode Ps20 of the 20 PMOS pipe, and source electrode Ps19 connects power vd D; The grid Pg20 of the 20 PMOS pipe connects C, and drain electrode Pd20 connects the drain electrode Nd19 of the 19 NMOS pipe, and source electrode Ps20 connects Pd19; The grid Pg21 of the 21 PMOS pipe connects Pd17, and drain electrode Pd21 connects the source electrode Ps22 of the 22 PMOS pipe, and source electrode Ps21 connects power vd D; The grid Pg22 of the 22 PMOS pipe connects C, and drain electrode Pd22 connects the drain electrode Nd21 of the 21 NMOS pipe and, as another output SON from latch, source electrode Ps22 connects Pd21; The grid Ng13 of the 13 NMOS pipe connects C, and drain electrode Nd13 connects Pd14, and source electrode Ns13 connects the drain electrode Nd14 of the 14 NMOS pipe; The grid Ng14 of the 14 NMOS pipe connects MO, and drain electrode Nd14 connects Ns13, source electrode Ns14 ground connection VSS; The grid Ng15 of the 15 NMOS pipe connects C, and drain electrode Nd15 connects Pd16, and source electrode Ns15 connects the drain electrode Nd16 of the 16 NMOS pipe; The grid Ng16 of the 16 NMOS pipe connects MO, and drain electrode Nd16 connects Ns15, source electrode Ns16 ground connection VSS; The grid Ng17 of the 17 NMOS pipe connects Pd14, and drain electrode Nd17 connects Pd17, source electrode Ns17 ground connection VSS; The grid Ng18 of the 18 NMOS pipe connects Pd16, and drain electrode Nd18 connects Pd18, source electrode Ns18 ground connection VSS; The grid Ng19 of the 19 NMOS pipe connects CN, and drain electrode Nd19 connects Pd20, and source electrode Ns19 connects the drain electrode Nd20 of the 20 NMOS pipe; The grid Ng20 of the 20 NMOS pipe connects Pd17, and drain electrode Nd20 connects Ns19, source electrode Ns20 ground connection VSS; The grid Ng21 of the 21 NMOS pipe connects CN, and drain electrode Nd21 connects Pd22, and source electrode Ns21 connects the drain electrode Nd22 of the 22 NMOS pipe; The grid Ng22 of the 22 NMOS pipe connects Pd18, and drain electrode Nd22 connects Ns21, source electrode Ns22 ground connection VSS.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104617923A (en) * | 2015-02-06 | 2015-05-13 | 中国人民解放军国防科学技术大学 | High-speed low-power-consumption multi-threshold-value D-type trigger |
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| CN103825583B (en) * | 2013-12-11 | 2016-08-17 | 中国人民解放军国防科学技术大学 | Anti-single particle upset can synchronous reset d type flip flop with single-ion transient state |
| CN105391430B (en) * | 2015-12-14 | 2024-06-07 | 深圳市超聚微电子科技有限公司 | Multiplexing two data input master-slave type D trigger |
| CN110311660B (en) * | 2019-07-03 | 2023-02-24 | 西安微电子技术研究所 | Self-adaptive single event upset resistant D trigger |
| CN110855270B (en) * | 2019-09-04 | 2022-09-23 | 合肥工业大学 | Cross-layer dual-mode redundancy sensitive amplifier type trigger with low overhead |
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| JP2001189423A (en) * | 1999-12-28 | 2001-07-10 | Sanyo Electric Co Ltd | Semiconductor interpreted circuit |
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