CN102361441B - Single event upset resistant settable scanning structure D trigger - Google Patents
Single event upset resistant settable scanning structure D trigger Download PDFInfo
- Publication number
- CN102361441B CN102361441B CN 201110323794 CN201110323794A CN102361441B CN 102361441 B CN102361441 B CN 102361441B CN 201110323794 CN201110323794 CN 201110323794 CN 201110323794 A CN201110323794 A CN 201110323794A CN 102361441 B CN102361441 B CN 102361441B
- Authority
- CN
- China
- Prior art keywords
- connects
- drain electrode
- grid
- source electrode
- nmos pipe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a single event upset resistant settable scanning structure D trigger, and aims to improve the single event upset resistance of the single event upset resistant settable scanning structure D trigger. The trigger consists of a clock circuit, a scanning control buffer circuit, a master latch, a slave latch and an output buffer circuit; the master latch consists of eighteen P-channel metal oxide semiconductor (PMOS) tubes and eighteen N-channel metal oxide semiconductor (NMOS) tubes; the slave latch consists of twelve PMOS tubes and twelve NMOS tubes; both the master latch and the slave latch are subjected to dual-mode redundancy reinforcement; and C2MOS circuits in the master latch and the slave latch are improved, namely separated into pull-up circuits and pull-down circuits in mutually redundant C2MOS circuits. The single event upset resistant synchronously-settable scanning structure D trigger has strong single event upset resistance, is suitable for a standard cell library of a single event upset resistant reinforcing integrated circuit, and is applied in the fields of aviation, spaceflight and the like.
Description
Technical field
The present invention relates to a kind of D master-slave flip-flop with set structure and Scan Architecture, particularly the setable Scan Architecture d type flip flop of a kind of anti-single particle overturn (signal event upset).
Background technology
In cosmic space, there are a large amount of high energy particles (proton, electronics, heavy ion) and charged particle.After integrated circuit is subject to the bombardment of these high energy particles and charged particle, in integrated circuit, can produce electronic impulse, may make the original level of IC interior node overturn, this effect is called single-particle inversion (SEU).The LET(linear energy transfer of single-particle bombardment integrated circuit) value is higher, and the electronic impulse of generation is stronger.The integrated circuit used in the Aeronautics and Astronautics field all can be subject to the threat of single-particle inversion, makes the integrated circuit job insecurity, even produces fatal mistake, therefore develops advanced integrated circuit anti-single particle overturn reinforcement technique particularly important.
The anti-single particle overturn reinforcement technique of integrated circuit can be divided into system-level reinforcing, the circuit level is reinforced and device level is reinforced.The IC reliability of system-level reinforcing is high, but chip area is large, power consumption is large, the speed of service is slow.The integrated circuit speed of service that device level is reinforced is fast, and chip area is little, low in energy consumption, but the device level reinforcing realizes that difficulty is large, and cost is high.The IC reliability that the circuit level is reinforced is high, chip area, power consumption and the speed of service are better than the integrated circuit of system-level reinforcing, and realizing that difficulty and cost are less than the integrated circuit that device level is reinforced, is very important integrated circuit anti-single particle overturn reinforcement means.
D type flip flop is to use one of maximum unit in sequential logical circuit, and its anti-single particle overturn ability has directly determined the anti-single particle overturn ability of integrated circuit.D type flip flop is carried out to the circuit level and reinforce the anti-single particle overturn ability that can under less chip area, power consumption and cost, effectively improve integrated circuit.
Traditional d type flip flop is D master-slave flip-flop, generally by the main latch with from the level series of latches, forms, and it is the effective ways of realizing that the d type flip flop anti-single particle is reinforced that the anti-single particle overturn of latch is reinforced.The people such as T.Clain are at IEEE Transaction on Nuclear Science(IEEE atomic energy science journal) on " Upset Hardened Memory Design for Submicron CMOS Technology " (the memory cell design is reinforced in upset under the submicron CMOS technology) (December in 1996 the 6th phases 43 volume of delivering, 2874th～2878 pages) latch that a kind of redundancy is reinforced proposed, this latch has increased an inverter and a feedback loop on the basis of classical latch structure, with original inverter and feedback loop redundant circuit each other.In inverter, the input of N pipe separates with the input of P pipe, connects respectively two feedback loops, C in feedback loop
2the input of the N of MOS circuit pipe and P pipe is respectively from the output of two inverters.Signal input and the signal of this latch are preserved by C
2the MOS clock circuit is controlled.The latch advantage that this redundancy is reinforced is: the trigging signal produced while bombarding a node can return to original state by the correct level of corresponding node in its redundant circuit.The deficiency of the latch that this redundancy is reinforced is: two of inputs are the C of redundancy each other
2the MOS circuit draws PMOS pipe and a pull-down NMOS pipe on sharing one, make C in feedback loop
2there is an indirect pathway between the output node of MOS circuit and redundant circuit corresponding node, when the single-particle bombardment makes this C
2the level upset of MOS circuit output node, this trigging signal can propagate into along indirect pathway the corresponding node of redundant circuit, if the LET value of single-particle bombardment is higher, two each other the circuit of redundancy level all can occur overturns, finally make the output of latch also overturn.The d type flip flop that traditional redundancy that the series of latches of being reinforced by two this kind of redundancies forms is reinforced, the LET value of bombarding when single-particle is higher, two each other the circuit of redundancy level upset also all can occur, finally make the output of the d type flip flop that traditional redundancy reinforces also overturn.The people such as R.Naseer are in the 48th IEEE International Midwest Symposium on Circuits the 48th IEEE circuit of and Systems(and the international conference of system Midwest) on " The DF-DICE Storage Element for Immunity to Soft Errors " (to the DF-DICE memory cell of soft error immunity) delivered the latch that the similar redundancy of a kind of and above-mentioned latch structure is reinforced has also been proposed.Two C of this latch input
2the MOS circuit is fully independently, two each other in the circuit of redundancy corresponding node do not have indirect pathway, overcome the weak point of the latch that redundancy that the people such as T.Clain propose reinforces.But the latch that the redundancy that the people such as R.Naseer propose is reinforced has used passgate structures in feedback loop, when a node is subject to the single-particle bombardment that upset occurs, its redundant circuit feeds back to this node by correct level by transmission gate.Because the noise margin of passgate structures is lower, the signal feedback ability of feedback loop a little less than, when the LET value of single-particle bombardment is higher, feedback loop can not make this node recover correct level, has had a strong impact on this latch anti-single particle overturn ability.The d type flip flop that traditional redundancy that the series of latches of being reinforced by two this kind of redundancies forms is reinforced, when the LET value of single-particle bombardment is higher, also can be because of the passgate structures in feedback loop, can not make this node recover correct level, affect the d type flip flop anti-single particle overturn ability that this tradition redundancy is reinforced.
The Chinese patent that the patent No. is CN101499788A discloses the d type flip flop of a kind of anti-single particle overturn and single event transient pulse.This invention is the d type flip flop that a kind of structure is similar to the time sampling structure, comprises two variable connectors, two delay circuits, two shutter circuit and three inverters, has realized that the anti-single particle overturn of d type flip flop is reinforced.Owing to adopting delay circuit and shutter circuit to shield the electronic impulse that bombardment produces; when the LET value of single-particle bombardment is higher; the electronic impulse width can be greater than the time of delay of delay circuit; the output level of shutter circuit is overturn, greatly reduce the anti-single particle overturn ability of this d type flip flop.
Common D master-slave flip-flop is unfavorable at test phase, circuit being detected, and makes test job become very loaded down with trivial details, complicated.Add scanning circuit on common D master-slave flip-flop architecture basics, can effectively simplify circuit test work, at test phase, can control by sweep signal the input of D master-slave flip-flop and then control circuit state.
Some integrated circuit needs the state of d type flip flop in the control integration circuit, forces d type flip flop output high level and the data of wherein storage are set to logical one.Increase setting circuit and asserts signal input on the original architecture basics of d type flip flop, can realize the set structure of d type flip flop, and control the set function of d type flip flop by asserts signal.But at present setable Scan Architecture d type flip flop anti-single particle overturn ability is all not high, is unfavorable for using in the integrated circuit (IC) chip in the fields such as Aeronautics and Astronautics.
Summary of the invention
The technical problem to be solved in the present invention is, the setable not high problem of Scan Architecture d type flip flop anti-single particle overturn ability for current anti-single particle overturn, propose the setable Scan Architecture d type flip flop of a kind of anti-single particle overturn, it can work and not produce single-particle inversion under the single-particle bombardment of higher LET value.
The setable Scan Architecture d type flip flop of the anti-single particle overturn that the present invention proposes is by clock circuit, scan control buffer circuit, main latch, form from latch, output buffer.
The setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention has five inputs and two outputs.Five inputs are respectively that CK is that clock signal input part, D are that data-signal input, SE are that scan control signal input and SI are that scan data input terminal and SN are the asserts signal input; Two outputs are respectively Q and QN, Q and a pair of contrary data-signal of QN output.
Clock circuit has an input and two outputs, and input is CK, and output is C, CN.Clock circuit is a two-stage inverter, first order inverter and second level inverter, consists of; First order inverter is comprised of a PMOS pipe and a NMOS pipe, and the grid Pg1 of a PMOS pipe connects CK, the drain electrode Nd1 of drain electrode Pd1 connection the one NMOS pipe, and as an output CN of clock circuit.The grid Ng1 of the one NMOS pipe connects CK, and drain electrode Nd1 connects Pd1; Second level inverter is comprised of the 2nd PMOS pipe and the 2nd NMOS pipe, and the grid Pg2 of the 2nd PMOS pipe connects CN, the drain electrode Nd2 of drain electrode Pd2 connection the 2nd NMOS pipe, and as another output C of clock circuit.The grid Ng2 of the 2nd NMOS pipe connects CN, and drain electrode Nd2 connects Pd2.The one PMOS pipe is connected power vd D with the substrate of the 2nd PMOS pipe, and source electrode Ps1, Ps2 connect power vd D; The substrate ground connection VSS of the one NMOS pipe and the 2nd NMOS pipe, source electrode Ns1, Ns2 be ground connection VSS also.
The scan control buffer circuit has an input and an output, and input is SE, and output is SEN.The scan control buffer circuit is comprised of the 3rd PMOS pipe and the 3rd NMOS pipe.The substrate of the 3rd PMOS pipe all is connected power vd D with source electrode Ps3, the equal ground connection VSS of the substrate of the 3rd NMOS pipe and source electrode Ns3.The grid Pg3 of the 3rd PMOS pipe connects SE, and drain electrode Pd3 connects the drain electrode Nd3 of the 3rd NMOS pipe, and as the output SEN of scan control buffer circuit; The grid Ng3 of the 3rd NMOS pipe connects SE, and drain electrode Nd3 connects Pd3.
Main latch and be the latch that redundancy is reinforced from latch, and also comprise Scan Architecture in main latch.Main latch and from series connection before and after latch, and all with clock circuit, be connected.Main latch is connected with the scan control buffer circuit again, from latch, also with output buffer, is connected.
Main latch has seven inputs and an output, and seven inputs are D, C, CN, SE, SEN, SI, SN, and an output is MO.Main latch is comprised of 18 PMOS pipes and 18 NMOS pipes, and in main latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg4 of the 4th PMOS pipe connects SI, and drain electrode Pd4 connects the source electrode Ps5 of the 5th PMOS pipe, and source electrode Ps4 connects power vd D; The grid Pg5 of the 5th PMOS pipe connects SEN, and drain electrode Pd5 connects the source electrode Ps8 of the 8th PMOS pipe, and source electrode Ps5 connects Pd4; The grid Pg6 of the 6th PMOS pipe connects SE, and drain electrode Pd6 connects the source electrode Ps7 of the 7th PMOS pipe, and source electrode Ps6 connects power vd D; The grid Pg7 of the 7th PMOS pipe connects D, and drain electrode Pd7 connects Ps8, and source electrode Ps7 connects Pd6; The grid Pg8 of the 8th PMOS pipe connects C, and drain electrode Pd8 connects the drain electrode Nd4 of the 4th NMOS pipe, and source electrode Ps8 connects Pd5; The grid Pg9 of the 9th PMOS pipe connects SI, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS pipe, and source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects SEN, and drain electrode Pd10 connects the source electrode Ps13 of the 13 PMOS pipe, and source electrode Ps10 connects Pd9; The grid Pg11 of the 11 PMOS pipe connects SE, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects D, and drain electrode Pd12 connects Ps13, and source electrode Ps12 connects Pd11; The grid Pg13 of the 13 PMOS pipe connects C, and drain electrode Pd13 connects the drain electrode Nd9 of the 9th NMOS pipe, and source electrode Ps13 connects Pd10; The grid Pg14 of the 14 PMOS pipe connects Pd8, and drain electrode Pd14 connects the drain electrode Nd14 of the 14 NMOS pipe and, as the output MO of main latch, source electrode Ps14 connects power vd D; The grid Pg15 of the 15 PMOS pipe connects SN, and drain electrode Pd15 connects Pd14, and source electrode Ps15 connects power vd D; The grid Pg16 of the 16 PMOS pipe connects Pd13, and drain electrode Pd16 connects the drain electrode Nd16 of the 16 NMOS pipe, and source electrode Ps16 connects power vd D; The grid Pg17 of the 17 PMOS pipe connects SN, and drain electrode Pd17 connects Pd16, and source electrode Ps17 connects power vd D; The grid Pg18 of the 18 PMOS pipe connects Pd16, and drain electrode Pd18 connects the source electrode Ps19 of the 19 PMOS pipe, and source electrode Ps18 connects power vd D; The grid Pg19 of the 19 PMOS pipe connects CN, and drain electrode Pd19 connects the drain electrode Nd18 of the 18 NMOS pipe, and source electrode Ps19 connects Pd18; The grid Pg20 of the 20 PMOS pipe connects Pd14, and drain electrode Pd20 connects the source electrode Ps21 of the 21 PMOS pipe, and source electrode Ps20 connects power vd D; The grid Pg21 of the 21 PMOS pipe connects CN, and drain electrode Pd21 connects the drain electrode Nd20 of the 20 NMOS pipe, and source electrode Ps21 connects Pd20; The grid Ng4 of the 4th NMOS pipe connects CN, and drain electrode Nd4 connects Pd8, and source electrode Ns4 connects the drain electrode Nd5 of the 5th NMOS pipe; The grid Ng5 of the 5th NMOS pipe connects SE, and drain electrode Nd5 connects Ns4, and source electrode Ns5 connects the drain electrode Nd6 of the 6th NMOS pipe; The grid Ng6 of the 6th NMOS pipe connects SI, and drain electrode Nd6 connects Ns5, source electrode Ns6 ground connection VSS; The grid Ng7 of the 7th NMOS pipe connects D, and drain electrode Nd7 connects Ns4, and source electrode Ns7 connects the drain electrode Nd8 of the 8th NMOS pipe; The grid Ng8 of the 8th NMOS pipe connects SEN, and drain electrode Nd8 connects Ns7, source electrode Ns8 ground connection VSS; The grid Ng9 of the 9th NMOS pipe connects CN, and drain electrode Nd9 connects Pd13, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe; The grid Ng10 of the tenth NMOS pipe connects SE, and drain electrode Nd10 connects Ns9, and source electrode Ns10 connects the drain electrode Nd11 of the 11 NMOS pipe; The grid Ng11 of the 11 NMOS pipe connects SI, and drain electrode Nd11 connects Ns10, source electrode Ns11 ground connection VSS; The grid Ng12 of the 12 NMOS pipe connects D, and drain electrode Nd12 connects Ns9, and source electrode Ns12 connects the drain electrode Nd13 of the 13 NMOS pipe; The grid Ng13 of the 13 NMOS pipe connects SEN, and drain electrode Nd13 connects Ns12, source electrode Ns13 ground connection VSS; The grid Ng14 of the 14 NMOS pipe connects Pd13, and drain electrode Nd14 connects Pd14, and source electrode Ns14 connects the drain electrode Nd15 of the 15 NMOS pipe; The grid Ng15 of the 15 NMOS pipe connects SN, and drain electrode Nd15 connects Ns14, source electrode Ns15 ground connection VSS; The grid Ng16 of the 16 NMOS pipe connects Pd8, and drain electrode Nd16 connects Pd16, and source electrode Ns16 connects the drain electrode Nd17 of the 17 NMOS pipe; The grid Ng17 of the 17 NMOS pipe connects SN, and drain electrode Nd17 connects Ns16, source electrode Ns17 ground connection VSS; The grid Ng18 of the 18 NMOS pipe connects C, and drain electrode Nd18 connects Pd19, and source electrode Ns18 connects the drain electrode Nd19 of the 19 NMOS pipe; The grid Ng19 of the 19 NMOS pipe connects Pd14, and drain electrode Nd19 connects Ns18, source electrode Ns19 ground connection VSS; The grid Ng20 of the 20 NMOS pipe connects C, and drain electrode Nd20 connects Pd21, and source electrode Ns20 connects the drain electrode Nd21 of the 21 NMOS pipe; The grid Ng21 of the 21 NMOS pipe connects Pd16, and drain electrode Nd21 connects Ns20, source electrode Ns21 ground connection VSS.The 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe and the 5th NMOS pipe, the 6th NMOS pipe, the 8th NMOS pipe form the Scan Architecture in main latch.
From latch, four inputs and an output are arranged, four inputs are MO, C, CN, SN, and output is SO.From latch, 12 PMOS pipes and 12 NMOS pipes, consist of, from latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg22 of the 22 PMOS pipe connects MO, and drain electrode Pd22 connects the source electrode Ps23 of the 23 PMOS pipe, and source electrode Ps22 connects power vd D; The grid Pg23 of the 23 PMOS pipe connects CN, and drain electrode Pd23 connects the drain electrode Nd22 of the 22 NMOS pipe, and source electrode Ps23 connects Pd22; The grid Pg24 of the 24 PMOS pipe connects MO, and drain electrode Pd24 connects the source electrode Ps25 of the 25 PMOS pipe, and source electrode Ps24 connects power vd D; The grid Pg25 of the 25 PMOS pipe connects CN, and drain electrode Pd25 connects the drain electrode Nd24 of the 24 NMOS pipe, and source electrode Ps25 connects Pd24; The grid Pg26 of the 26 PMOS pipe connects Pd25, and drain electrode Pd26 connects the drain electrode Nd26 of the 26 NMOS pipe and, as the output SO from latch, source electrode Ps26 connects power vd D; The grid Pg27 of the 27 PMOS pipe connects SN, and drain electrode Pd27 connects Pd26, and source electrode Ps27 connects power vd D; The grid Pg28 of the 28 PMOS pipe connects Pd23, and drain electrode Pd28 connects the drain electrode Nd28 of the 28 NMOS pipe, and source electrode Ps28 connects power vd D; The grid Pg29 of the 29 PMOS pipe connects SN, and drain electrode Pd29 connects Pd28, and source electrode Ps29 connects power vd D; The grid Pg30 of the 30 PMOS pipe connects Pd28, and drain electrode Pd30 connects the source electrode Ps31 of the 31 PMOS pipe, and source electrode Ps30 connects power vd D; The grid Pg31 of the 31 PMOS pipe connects C, and drain electrode Pd31 connects the drain electrode Nd30 of the 30 NMOS pipe, and source electrode Ps31 connects Pd30; The grid Pg32 of the 32 PMOS pipe connects Pd26, and drain electrode Pd32 connects the source electrode Ps33 of the 33 PMOS pipe, and source electrode Ps32 connects power vd D; The grid Pg33 of the 33 PMOS pipe connects C, and drain electrode Pd33 connects the drain electrode Nd32 of the 32 NMOS pipe, and source electrode Ps33 connects Pd32; The grid Ng22 of the 22 NMOS pipe connects C, and drain electrode Nd22 connects Pd23, and source electrode Ns22 connects the drain electrode Nd23 of the 23 NMOS pipe; The grid Ng23 of the 23 NMOS pipe connects MO, and drain electrode Nd23 connects Ns22, source electrode Ns23 ground connection VSS; The grid Ng24 of the 24 NMOS pipe connects C, and drain electrode Nd24 connects Pd25, and source electrode Ns24 connects the drain electrode Nd25 of the 25 NMOS pipe; The grid Ng25 of the 25 NMOS pipe connects MO, and drain electrode Nd25 connects Ns24, source electrode Ns25 ground connection VSS; The grid Ng26 of the 26 NMOS pipe connects Pd23, and drain electrode Nd26 connects Pd26, and source electrode Ns26 connects the drain electrode Nd27 of the 27 NMOS pipe; The grid Ng27 of the 27 NMOS pipe connects SN, and drain electrode Nd27 connects Ns26, source electrode Ns27 ground connection VSS; The grid Ng28 of the 28 NMOS pipe connects Pd25, and drain electrode Nd28 connects Pd28, and source electrode Ns28 connects the drain electrode Nd29 of the 29 NMOS pipe; The grid Ng29 of the 29 NMOS pipe connects SN, and drain electrode Nd29 connects Ns28, source electrode Ns29 ground connection VSS; The grid Ng30 of the 30 NMOS pipe connects CN, and drain electrode Nd30 connects Pd31, and source electrode Ns30 connects the drain electrode Nd31 of the 31 NMOS pipe; The grid Ng31 of the 31 NMOS pipe connects Pd26, and drain electrode Nd31 connects Ns30, source electrode Ns31 ground connection VSS; The grid Ng32 of the 32 NMOS pipe connects CN, and drain electrode Nd32 connects Pd33, and source electrode Ns32 connects the drain electrode Nd33 of the 33 NMOS pipe; The grid Ng33 of the 33 NMOS pipe connects Pd28, and drain electrode Nd33 connects Ns32, source electrode Ns33 ground connection VSS.
Output buffer has an input and two outputs, and an input is SO, and two outputs are QN, Q.Output buffer is comprised of three PMOS pipes and three NMOS pipes, and in output buffer, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg34 of the 34 PMOS pipe connects SO, and drain electrode Pd34 connects the drain electrode Nd34 of the 34 NMOS pipe, and source electrode Ps34 connects power vd D; The grid Pg35 of the 35 PMOS pipe connects SO, and drain electrode Pd35 connects the drain electrode Nd35 of the 35 NMOS pipe and, as an output QN of output buffer, source electrode Ps35 connects power vd D; The grid Pg36 of the 36 PMOS pipe connects Pd34, and drain electrode Pd36 connects the drain electrode Nd36 of the 36 NMOS pipe and, as an output Q of output buffer, source electrode Ps36 connects power vd D; The grid Ng34 of the 34 NMOS pipe connects SO, and drain electrode Nd34 connects Pd34, source electrode Ns34 ground connection VSS; The grid Ng35 of the 35 NMOS pipe connects SO, and drain electrode Nd35 connects Pd35, source electrode Ns35 ground connection VSS; The grid Ng36 of the 36 NMOS pipe connects Pd34, and drain electrode Nd36 connects Pd36, source electrode Ns36 ground connection VSS.
The setable Scan Architecture d type flip flop course of work of anti-single particle overturn of the present invention is as follows:
The setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention also can enter SM set mode the time marquis in scanning mode, and scanning mode and SM set mode can exist simultaneously.The setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention can carry out set at any time, and set function is that the asserts signal input is controlled by SN.
When SN is that low level, SE are while being any level, the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention is all in SM set mode, be main latch and from latch all by latching logic " 1 " by force, output Q and the QN of output buffer are respectively high level and low level.
When SN is that high level, SE are while being low level, the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention is in normal operating conditions, be that the clock circuit receives CK, after CK is cushioned, produce respectively the CN anti-phase with CK and with the C of CK homophase, and CN with C is passed to main latch and from latch.At CK, be between low period, CN is that high level, C are low level, and main latch is opened, and receives D and it is carried out to the MO of output and D homophase after buffered,, do not receive the MO of main latch output but preserve the MO that a CK trailing edge samples in preservation state from latch; At CK, be between high period, CN is that low level, C are high level, main latch is in preservation state, preserve the MO of D that previous CK rising edge samples output and D homophase, open and receive the output MO of main latch from latch, MO is carried out to buffered output and the SO of MO homophase and the SON anti-phase with MO.Output buffer all will receive the output SO from latch at any time, to SO buffering output and the anti-phase QN of SO and with the Q of SO homophase.
When SN is that high level, SE are while being high level, the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention is in scanning mode, be that the clock circuit receives CK, after CK is cushioned, produce respectively the CN anti-phase with CK and with the C of CK homophase, and CN with C is passed to main latch and from latch.At CK, be between low period, CN is that high level, C are low level, and main latch is opened, and receives SI and it is carried out to the MO of output and SI homophase after buffered,, do not receive the MO of main latch output but preserve the MO that a CK trailing edge samples in preservation state from latch; At CK, be between high period, CN is that low level, C are high level, main latch is in preservation state, preserve the MO of SI that previous CK rising edge samples output and SI homophase, open and receive the output MO of main latch from latch, MO is carried out to buffered output and the SO of MO homophase and the SON anti-phase with MO.Output buffer all will receive the output SO from latch at any time, to SO buffering output and the anti-phase QN of SO and with the Q of SO homophase.
Adopt the present invention can reach following technique effect:
The anti-single particle overturn ability of the Scan Architecture d type flip flop that anti-single particle overturn of the present invention is setable is better than unguyed setable Scan Architecture d type flip flop, the time sampling of tradition and reinforces setable Scan Architecture d type flip flop and traditional redundancy is reinforced setable Scan Architecture d type flip flop.Because the present invention is transformed the unguyed setable Scan Architecture d type flip flop structure of tradition, all carried out the duplication redundancy reinforcing to main latch with from latch, and for main latch and from latch C
2the MOS circuit structure improves, and separates the C of redundancy each other
2pull-up circuit in the MOS circuit and pull-down circuit, further improved the anti-single particle overturn ability of the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention.The setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention is suitable for the standard cell lib that anti-single particle overturn is reinforced integrated circuit, is applied to the fields such as Aeronautics and Astronautics.
The accompanying drawing explanation
Fig. 1 is the setable Scan Architecture d type flip flop logical construction schematic diagram of anti-single particle overturn of the present invention.
Fig. 2 is clock circuit structural representation in the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention.
Fig. 3 is scan control buffer circuit structural representation in the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention.
Fig. 4 is main latch structural representation in the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention.
Fig. 5 is from the latch structure schematic diagram in the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention.
Fig. 6 is output buffer structural representation in the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention.
Embodiment
Fig. 1 is the setable Scan Architecture d type flip flop logical construction schematic diagram of anti-single particle overturn of the present invention.The present invention is by clock circuit (as shown in Figure 2), scan control buffer circuit (as shown in Figure 3), main latch (as shown in Figure 4), form from latch (as shown in Figure 5), output buffer (as shown in Figure 6).The present invention has five inputs and two outputs.Five inputs are respectively that CK is that clock signal input part, D are that data-signal input, SE are that scan control signal input and SI are that scan data input terminal and SN are the asserts signal input; Two outputs are respectively Q and QN, Q and a pair of contrary data-signal of QN output.Clock circuit receives CK, and CK is carried out exporting respectively C and CN after buffered.Main latch receives D, C, CN, SE, SEN, SI and SN, main latch under the control of C, CN, SE, SEN, SN to D or SI latched etc. process after output MO.Receive MO and C, CN and SN from latch, from latch, under the control of C, CN and SN, export respectively SO after to processing such as MO are latched.Output buffer receives SO, and it is carried out exporting Q and QN after buffered.SN is high level, SE while being low level, and the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention is in normal operating conditions; SN is high level, SE while being high level, and the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention is in the scanning work state; When SN is low level, the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention enters SM set mode.
As shown in Figure 2, clock circuit has an input and two outputs, and input is CK, and output is C, CN.Clock circuit is a two-stage inverter, and first order inverter is comprised of a PMOS pipe and a NMOS pipe, and the grid Pg1 of a PMOS pipe connects CK, the drain electrode Nd1 of drain electrode Pd1 connection the one NMOS pipe, and as an output CN of clock circuit.The grid Ng1 of the one NMOS pipe connects CK, and drain electrode Nd1 connects Pd1; Second level inverter is comprised of the 2nd PMOS pipe and the 2nd NMOS pipe, and the grid Pg2 of the 2nd PMOS pipe connects CN, the drain electrode Nd2 of drain electrode Pd2 connection the 2nd NMOS pipe, and as another output C of clock circuit.The grid Ng2 of the 2nd NMOS pipe connects CN, and drain electrode Nd2 connects Pd2.The one PMOS pipe is connected power vd D with the substrate of the 2nd PMOS pipe, and source electrode Ps1, Ps2 connect power vd D; The substrate ground connection VSS of the one NMOS pipe and the 2nd NMOS pipe, source electrode Ns1, Ns2 be ground connection VSS also.
As shown in Figure 3, the scan control buffer circuit has an input and an output, and input is SE, and output is SEN.The scan control buffer circuit is comprised of the 3rd PMOS pipe and the 3rd NMOS pipe.The substrate of the 3rd PMOS pipe all is connected power vd D with source electrode Ps3, the equal ground connection VSS of the substrate of the 3rd NMOS pipe and source electrode Ns3.The grid Pg3 of the 3rd PMOS pipe connects SE, and drain electrode Pd3 connects the drain electrode Nd3 of the 3rd NMOS pipe, and as the output SEN of scan control buffer circuit; The grid Ng3 of the 3rd NMOS pipe connects SE, and drain electrode Nd3 connects Pd3.
As shown in Figure 4, main latch has seven inputs and an output, and seven inputs are D, C, CN, SE, SEN, SI, SN, and an output is MO.Main latch is comprised of 18 PMOS pipes and 18 NMOS pipes, and in main latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg4 of the 4th PMOS pipe connects SI, and drain electrode Pd4 connects the source electrode Ps5 of the 5th PMOS pipe, and source electrode Ps4 connects power vd D; The grid Pg5 of the 5th PMOS pipe connects SEN, and drain electrode Pd5 connects the source electrode Ps8 of the 8th PMOS pipe, and source electrode Ps5 connects Pd4; The grid Pg6 of the 6th PMOS pipe connects SE, and drain electrode Pd6 connects the source electrode Ps7 of the 7th PMOS pipe, and source electrode Ps6 connects power vd D; The grid Pg7 of the 7th PMOS pipe connects D, and drain electrode Pd7 connects Ps8, and source electrode Ps7 connects Pd6; The grid Pg8 of the 8th PMOS pipe connects C, and drain electrode Pd8 connects the drain electrode Nd4 of the 4th NMOS pipe, and source electrode Ps8 connects Pd5; The grid Pg9 of the 9th PMOS pipe connects SI, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS pipe, and source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects SEN, and drain electrode Pd10 connects the source electrode Ps13 of the 13 PMOS pipe, and source electrode Ps10 connects Pd9; The grid Pg11 of the 11 PMOS pipe connects SE, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects D, and drain electrode Pd12 connects Ps13, and source electrode Ps12 connects Pd11; The grid Pg13 of the 13 PMOS pipe connects C, and drain electrode Pd13 connects the drain electrode Nd9 of the 9th NMOS pipe, and source electrode Ps13 connects Pd10; The grid Pg14 of the 14 PMOS pipe connects Pd8, and drain electrode Pd14 connects the drain electrode Nd14 of the 14 NMOS pipe and, as the output MO of main latch, source electrode Ps14 connects power vd D; The grid Pg15 of the 15 PMOS pipe connects SN, and drain electrode Pd15 connects Pd14, and source electrode Ps15 connects power vd D; The grid Pg16 of the 16 PMOS pipe connects Pd13, and drain electrode Pd16 connects the drain electrode Nd16 of the 16 NMOS pipe, and source electrode Ps16 connects power vd D; The grid Pg17 of the 17 PMOS pipe connects SN, and drain electrode Pd17 connects Pd16, and source electrode Ps17 connects power vd D; The grid Pg18 of the 18 PMOS pipe connects Pd16, and drain electrode Pd18 connects the source electrode Ps19 of the 19 PMOS pipe, and source electrode Ps18 connects power vd D; The grid Pg19 of the 19 PMOS pipe connects CN, and drain electrode Pd19 connects the drain electrode Nd18 of the 18 NMOS pipe, and source electrode Ps19 connects Pd18; The grid Pg20 of the 20 PMOS pipe connects Pd14, and drain electrode Pd20 connects the source electrode Ps21 of the 21 PMOS pipe, and source electrode Ps20 connects power vd D; The grid Pg21 of the 21 PMOS pipe connects CN, and drain electrode Pd21 connects the drain electrode Nd20 of the 20 NMOS pipe, and source electrode Ps21 connects Pd20; The grid Ng4 of the 4th NMOS pipe connects CN, and drain electrode Nd4 connects Pd8, and source electrode Ns4 connects the drain electrode Nd5 of the 5th NMOS pipe; The grid Ng5 of the 5th NMOS pipe connects SE, and drain electrode Nd5 connects Ns4, and source electrode Ns5 connects the drain electrode Nd6 of the 6th NMOS pipe; The grid Ng6 of the 6th NMOS pipe connects SI, and drain electrode Nd6 connects Ns5, source electrode Ns6 ground connection VSS; The grid Ng7 of the 7th NMOS pipe connects D, and drain electrode Nd7 connects Ns4, and source electrode Ns7 connects the drain electrode Nd8 of the 8th NMOS pipe; The grid Ng8 of the 8th NMOS pipe connects SEN, and drain electrode Nd8 connects Ns7, source electrode Ns8 ground connection VSS; The grid Ng9 of the 9th NMOS pipe connects CN, and drain electrode Nd9 connects Pd13, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe; The grid Ng10 of the tenth NMOS pipe connects SE, and drain electrode Nd10 connects Ns9, and source electrode Ns10 connects the drain electrode Nd11 of the 11 NMOS pipe; The grid Ng11 of the 11 NMOS pipe connects SI, and drain electrode Nd11 connects Ns10, source electrode Ns11 ground connection VSS; The grid Ng12 of the 12 NMOS pipe connects D, and drain electrode Nd12 connects Ns9, and source electrode Ns12 connects the drain electrode Nd13 of the 13 NMOS pipe; The grid Ng13 of the 13 NMOS pipe connects SEN, and drain electrode Nd13 connects Ns12, source electrode Ns13 ground connection VSS; The grid Ng14 of the 14 NMOS pipe connects Pd13, and drain electrode Nd14 connects Pd14, and source electrode Ns14 connects the drain electrode Nd15 of the 15 NMOS pipe; The grid Ng15 of the 15 NMOS pipe connects SN, and drain electrode Nd15 connects Ns14, source electrode Ns15 ground connection VSS; The grid Ng16 of the 16 NMOS pipe connects Pd8, and drain electrode Nd16 connects Pd16, and source electrode Ns16 connects the drain electrode Nd17 of the 17 NMOS pipe; The grid Ng17 of the 17 NMOS pipe connects SN, and drain electrode Nd17 connects Ns16, source electrode Ns17 ground connection VSS; The grid Ng18 of the 18 NMOS pipe connects C, and drain electrode Nd18 connects Pd19, and source electrode Ns18 connects the drain electrode Nd19 of the 19 NMOS pipe; The grid Ng19 of the 19 NMOS pipe connects Pd14, and drain electrode Nd19 connects Ns18, source electrode Ns19 ground connection VSS; The grid Ng20 of the 20 NMOS pipe connects C, and drain electrode Nd20 connects Pd21, and source electrode Ns20 connects the drain electrode Nd21 of the 21 NMOS pipe; The grid Ng21 of the 21 NMOS pipe connects Pd16, and drain electrode Nd21 connects Ns20, source electrode Ns21 ground connection VSS.The 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe and the 5th NMOS pipe, the 6th NMOS pipe, the 8th NMOS pipe form the Scan Architecture in main latch.
As shown in Figure 5, from latch, four inputs and an output are arranged, four inputs are MO, C, CN, SN, and output is SO.From latch, 12 PMOS pipes and 12 NMOS pipes, consist of, from latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg22 of the 22 PMOS pipe connects MO, and drain electrode Pd22 connects the source electrode Ps23 of the 23 PMOS pipe, and source electrode Ps22 connects power vd D; The grid Pg23 of the 23 PMOS pipe connects CN, and drain electrode Pd23 connects the drain electrode Nd22 of the 22 NMOS pipe, and source electrode Ps23 connects Pd22; The grid Pg24 of the 24 PMOS pipe connects MO, and drain electrode Pd24 connects the source electrode Ps25 of the 25 PMOS pipe, and source electrode Ps24 connects power vd D; The grid Pg25 of the 25 PMOS pipe connects CN, and drain electrode Pd25 connects the drain electrode Nd24 of the 24 NMOS pipe, and source electrode Ps25 connects Pd24; The grid Pg26 of the 26 PMOS pipe connects Pd25, and drain electrode Pd26 connects the drain electrode Nd26 of the 26 NMOS pipe and, as the output SO from latch, source electrode Ps26 connects power vd D; The grid Pg27 of the 27 PMOS pipe connects SN, and drain electrode Pd27 connects Pd26, and source electrode Ps27 connects power vd D; The grid Pg28 of the 28 PMOS pipe connects Pd23, and drain electrode Pd28 connects the drain electrode Nd28 of the 28 NMOS pipe, and source electrode Ps28 connects power vd D; The grid Pg29 of the 29 PMOS pipe connects SN, and drain electrode Pd29 connects Pd28, and source electrode Ps29 connects power vd D; The grid Pg30 of the 30 PMOS pipe connects Pd28, and drain electrode Pd30 connects the source electrode Ps31 of the 31 PMOS pipe, and source electrode Ps30 connects power vd D; The grid Pg31 of the 31 PMOS pipe connects C, and drain electrode Pd31 connects the drain electrode Nd30 of the 30 NMOS pipe, and source electrode Ps31 connects Pd30; The grid Pg32 of the 32 PMOS pipe connects Pd26, and drain electrode Pd32 connects the source electrode Ps33 of the 33 PMOS pipe, and source electrode Ps32 connects power vd D; The grid Pg33 of the 33 PMOS pipe connects C, and drain electrode Pd33 connects the drain electrode Nd32 of the 32 NMOS pipe, and source electrode Ps33 connects Pd32; The grid Ng22 of the 22 NMOS pipe connects C, and drain electrode Nd22 connects Pd23, and source electrode Ns22 connects the drain electrode Nd23 of the 23 NMOS pipe; The grid Ng23 of the 23 NMOS pipe connects MO, and drain electrode Nd23 connects Ns22, source electrode Ns23 ground connection VSS; The grid Ng24 of the 24 NMOS pipe connects C, and drain electrode Nd24 connects Pd25, and source electrode Ns24 connects the drain electrode Nd25 of the 25 NMOS pipe; The grid Ng25 of the 25 NMOS pipe connects MO, and drain electrode Nd25 connects Ns24, source electrode Ns25 ground connection VSS; The grid Ng26 of the 26 NMOS pipe connects Pd23, and drain electrode Nd26 connects Pd26, and source electrode Ns26 connects the drain electrode Nd27 of the 27 NMOS pipe; The grid Ng27 of the 27 NMOS pipe connects SN, and drain electrode Nd27 connects Ns26, source electrode Ns27 ground connection VSS; The grid Ng28 of the 28 NMOS pipe connects Pd25, and drain electrode Nd28 connects Pd28, and source electrode Ns28 connects the drain electrode Nd29 of the 29 NMOS pipe; The grid Ng29 of the 29 NMOS pipe connects SN, and drain electrode Nd29 connects Ns28, source electrode Ns29 ground connection VSS; The grid Ng30 of the 30 NMOS pipe connects CN, and drain electrode Nd30 connects Pd31, and source electrode Ns30 connects the drain electrode Nd31 of the 31 NMOS pipe; The grid Ng31 of the 31 NMOS pipe connects Pd26, and drain electrode Nd31 connects Ns30, source electrode Ns31 ground connection VSS; The grid Ng32 of the 32 NMOS pipe connects CN, and drain electrode Nd32 connects Pd33, and source electrode Ns32 connects the drain electrode Nd33 of the 33 NMOS pipe; The grid Ng33 of the 33 NMOS pipe connects Pd28, and drain electrode Nd33 connects Ns32, source electrode Ns33 ground connection VSS.
As shown in Figure 6, output buffer has an input and two outputs, and an input is SO, and two outputs are QN, Q.Output buffer comprises three PMOS pipes and three NMOS pipes, and in output buffer, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg34 of the 34 PMOS pipe connects SO, and drain electrode Pd34 connects the drain electrode Nd34 of the 34 NMOS pipe, and source electrode Ps34 connects power vd D; The grid Pg35 of the 35 PMOS pipe connects SO, and drain electrode Pd35 connects the drain electrode Nd35 of the 35 NMOS pipe and, as an output QN of output buffer, source electrode Ps35 connects power vd D; The grid Pg36 of the 36 PMOS pipe connects Pd34, and drain electrode Pd36 connects the drain electrode Nd36 of the 36 NMOS pipe and, as an output Q of output buffer, source electrode Ps36 connects power vd D; The grid Ng34 of the 34 NMOS pipe connects SO, and drain electrode Nd34 connects Pd34, source electrode Ns34 ground connection VSS; The grid Ng35 of the 35 NMOS pipe connects SO, and drain electrode Nd35 connects Pd35, source electrode Ns35 ground connection VSS; The grid Ng36 of the 36 NMOS pipe connects Pd34, and drain electrode Nd36 connects Pd36, source electrode Ns36 ground connection VSS.
The H-13 of Beijing Institute of Atomic Energy tandem accelerator can produce the LET value and be respectively 2.88MeVcm
2/ mg, 8.62MeVcm
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2four kinds of ground heavy ion irradiation test environments of/mg.To reinforce setable Scan Architecture d type flip flop, time sampling in unguyed setable Scan Architecture d type flip flop, the traditional redundancy of the tradition of normal operating conditions reinforces setable Scan Architecture d type flip flop and the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and is placed in the LET value that the H-13 of Beijing Institute of Atomic Energy tandem accelerator produces and is respectively 2.88MeVcm
2/ mg, 8.62MeVcm
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2in the ground heavy ion irradiation test environment of/mg, observe each d type flip flop whether single-particle inversion occurs, obtain the minimum LET Value Data that each d type flip flop generation single-particle inversion needs.Unguyed setable Scan Architecture d type flip flop, the traditional redundancy of tradition that table 1 obtains for the ground heavy particle irradiation test of using the H-13 of Beijing Institute of Atomic Energy tandem accelerator and carrying out reinforced setable Scan Architecture d type flip flop, time sampling and reinforced the minimum LET Value Data that setable Scan Architecture d type flip flop and the setable Scan Architecture d type flip flop generation single-particle inversion of anti-single particle overturn of the present invention need.The unguyed setable Scan Architecture d type flip flop of tradition is 2.88MeVcm in the LET value
2/ mg, 8.62MeVcm
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2single-particle inversion all occurs in the ground heavy ion irradiation test environment of/mg while working, it is 12.6MeVcm in the LET value that traditional redundancy is reinforced setable Scan Architecture d type flip flop
2/ mg and 17.0MeVcm
2single-particle inversion occurs in the ground heavy ion irradiation test environment of/mg while working, it is 8.62MeVcm in the LET value that setable Scan Architecture d type flip flop is reinforced in time sampling
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2single-particle inversion occurs while working in the ground heavy ion irradiation test environment of/mg, and the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention is only 17.0MeVcm in the LET value
2single-particle inversion occurs in the ground heavy ion irradiation test environment of/mg while working.From then on table can be found out, the minimum LET value that generation single-particle inversion of the present invention needs improves 343% than the unguyed setable Scan Architecture d type flip flop of tradition, reinforce setable Scan Architecture d type flip flop than traditional redundancy and improve 35%, reinforce setable Scan Architecture d type flip flop than time sampling and improve 97%, therefore anti-single particle overturn ability of the present invention is better than the unguyed setable Scan Architecture d type flip flop of tradition, setable Scan Architecture d type flip flop is reinforced in time sampling and traditional redundancy is reinforced setable Scan Architecture d type flip flop, be suitable for anti-single particle overturn and reinforce the standard cell lib of integrated circuit, be applied to aviation, the fields such as space flight.
Table 1
Claims (1)
1. the Scan Architecture d type flip flop that anti-single particle overturn is setable, the setable Scan Architecture d type flip flop of anti-single particle overturn is by clock circuit, scan control buffer circuit, main latch, form from latch, output buffer, five inputs and two outputs are arranged, and five inputs are respectively that CK is that clock signal input part, D are that data-signal input, SE are that scan control signal input and SI are that scan data input terminal and SN are the asserts signal input; Two outputs are respectively Q and QN, Q and a pair of contrary data-signal of QN output; Clock circuit has an input and two outputs, and input is CK, and output is C, CN; Clock circuit is a two-stage phase inverter, first order phase inverter and second level phase inverter, consists of; First order phase inverter is comprised of a PMOS pipe and a NMOS pipe, and the grid Pg1 of a PMOS pipe connects CK, the drain electrode Nd1 of drain electrode Pd1 connection the one NMOS pipe, and as an output CN of clock circuit; The grid Ng1 of the one NMOS pipe connects CK, and drain electrode Nd1 connects Pd1; Second level phase inverter is comprised of the 2nd PMOS pipe and the 2nd NMOS pipe, and the grid Pg2 of the 2nd PMOS pipe connects CN, the drain electrode Nd2 of drain electrode Pd2 connection the 2nd NMOS pipe, and as another output C of clock circuit; The grid Ng2 of the 2nd NMOS pipe connects CN, and drain electrode Nd2 connects Pd2; The one PMOS pipe is connected power vd D with the substrate of the 2nd PMOS pipe, and source electrode Ps1, Ps2 connect power vd D; The substrate ground connection VSS of the one NMOS pipe and the 2nd NMOS pipe, source electrode Ns1, Ns2 be ground connection VSS also; The scan control buffer circuit has an input and an output, and input is SE, and output is SEN; The scan control buffer circuit is comprised of the 3rd PMOS pipe and the 3rd NMOS pipe; The substrate of the 3rd PMOS pipe all is connected power vd D with source electrode Ps3, the equal ground connection VSS of the substrate of the 3rd NMOS pipe and source electrode Ns3; The grid Pg3 of the 3rd PMOS pipe connects SE, and drain electrode Pd3 connects the drain electrode Nd3 of the 3rd NMOS pipe, and as the output SEN of scan control buffer circuit; The grid Ng3 of the 3rd NMOS pipe connects SE, and drain electrode Nd3 connects Pd3; Output buffer has an input and two outputs, and an input is SO, and two outputs are QN, Q; Output buffer is comprised of three PMOS pipes and three NMOS pipes, and in output buffer, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg34 of the 34 PMOS pipe connects SO, and drain electrode Pd34 connects the drain electrode Nd34 of the 34 NMOS pipe, and source electrode Ps34 connects power vd D; The grid Pg35 of the 35 PMOS pipe connects SO, and drain electrode Pd35 connects the drain electrode Nd35 of the 35 NMOS pipe and, as an output QN of output buffer, source electrode Ps35 connects power vd D; The grid Pg36 of the 36 PMOS pipe connects Pd34, and drain electrode Pd36 connects the drain electrode Nd36 of the 36 NMOS pipe and, as an output Q of output buffer, source electrode Ps36 connects power vd D; The grid Ng34 of the 34 NMOS pipe connects SO, and drain electrode Nd34 connects Pd34, source electrode Ns34 ground connection VSS; The grid Ng35 of the 35 NMOS pipe connects SO, and drain electrode Nd35 connects Pd35, source electrode Ns35 ground connection VSS; The grid Ng36 of the 36 NMOS pipe connects Pd34, and drain electrode Nd36 connects Pd36, source electrode Ns36 ground connection VSS; Main latch and be the latch that redundancy is reinforced from latch, and also comprise Scan Architecture in main latch, main latch and from series connection before and after latch, and all with clock circuit, be connected, main latch is connected with the scan control buffer circuit again, from latch, also with output buffer, is connected; It is characterized in that main latch has seven inputs and an output, seven inputs are D, C, CN, SE, SEN, SI, SN, and an output is MO; Main latch is comprised of 18 PMOS pipes and 18 NMOS pipes, and in main latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg4 of the 4th PMOS pipe connects SI, and drain electrode Pd4 connects the source electrode Ps5 of the 5th PMOS pipe, and source electrode Ps4 connects power vd D; The grid Pg5 of the 5th PMOS pipe connects SEN, and drain electrode Pd5 connects the source electrode Ps8 of the 8th PMOS pipe, and source electrode Ps5 connects Pd4; The grid Pg6 of the 6th PMOS pipe connects SE, and drain electrode Pd6 connects the source electrode Ps7 of the 7th PMOS pipe, and source electrode Ps6 connects power vd D; The grid Pg7 of the 7th PMOS pipe connects D, and drain electrode Pd7 connects Ps8, and source electrode Ps7 connects Pd6; The grid Pg8 of the 8th PMOS pipe connects C, and drain electrode Pd8 connects the drain electrode Nd4 of the 4th NMOS pipe, and source electrode Ps8 connects Pd5; The grid Pg9 of the 9th PMOS pipe connects SI, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS pipe, and source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects SEN, and drain electrode Pd10 connects the source electrode Ps13 of the 13 PMOS pipe, and source electrode Ps10 connects Pd9; The grid Pg11 of the 11 PMOS pipe connects SE, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects D, and drain electrode Pd12 connects Ps13, and source electrode Ps12 connects Pd11; The grid Pg13 of the 13 PMOS pipe connects C, and drain electrode Pd13 connects the drain electrode Nd9 of the 9th NMOS pipe, and source electrode Ps13 connects Pd10; The grid Pg14 of the 14 PMOS pipe connects Pd8, and drain electrode Pd14 connects the drain electrode Nd14 of the 14 NMOS pipe and, as the output MO of main latch, source electrode Ps14 connects power vd D; The grid Pg15 of the 15 PMOS pipe connects SN, and drain electrode Pd15 connects Pd14, and source electrode Ps15 connects power vd D; The grid Pg16 of the 16 PMOS pipe connects Pd13, and drain electrode Pd16 connects the drain electrode Nd16 of the 16 NMOS pipe, and source electrode Ps16 connects power vd D; The grid Pg17 of the 17 PMOS pipe connects SN, and drain electrode Pd17 connects Pd16, and source electrode Ps17 connects power vd D; The grid Pg18 of the 18 PMOS pipe connects Pd16, and drain electrode Pd18 connects the source electrode Ps19 of the 19 PMOS pipe, and source electrode Ps18 connects power vd D; The grid Pg19 of the 19 PMOS pipe connects CN, and drain electrode Pd19 connects the drain electrode Nd18 of the 18 NMOS pipe, and source electrode Ps19 connects Pd18; The grid Pg20 of the 20 PMOS pipe connects Pd14, and drain electrode Pd20 connects the source electrode Ps21 of the 21 PMOS pipe, and source electrode Ps20 connects power vd D; The grid Pg21 of the 21 PMOS pipe connects CN, and drain electrode Pd21 connects the drain electrode Nd20 of the 20 NMOS pipe, and source electrode Ps21 connects Pd20; The grid Ng4 of the 4th NMOS pipe connects CN, and drain electrode Nd4 connects Pd8, and source electrode Ns4 connects the drain electrode Nd5 of the 5th NMOS pipe; The grid Ng5 of the 5th NMOS pipe connects SE, and drain electrode Nd5 connects Ns4, and source electrode Ns5 connects the drain electrode Nd6 of the 6th NMOS pipe; The grid Ng6 of the 6th NMOS pipe connects SI, and drain electrode Nd6 connects Ns5, source electrode Ns6 ground connection VSS; The grid Ng7 of the 7th NMOS pipe connects D, and drain electrode Nd7 connects Ns4, and source electrode Ns7 connects the drain electrode Nd8 of the 8th NMOS pipe; The grid Ng8 of the 8th NMOS pipe connects SEN, and drain electrode Nd8 connects Ns7, source electrode Ns8 ground connection VSS; The grid Ng9 of the 9th NMOS pipe connects CN, and drain electrode Nd9 connects Pd13, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe; The grid Ng10 of the tenth NMOS pipe connects SE, and drain electrode Nd10 connects Ns9, and source electrode Ns10 connects the drain electrode Nd11 of the 11 NMOS pipe; The grid Ng11 of the 11 NMOS pipe connects SI, and drain electrode Nd11 connects Ns10, source electrode Ns11 ground connection VSS; The grid Ng12 of the 12 NMOS pipe connects D, and drain electrode Nd12 connects Ns9, and source electrode Ns12 connects the drain electrode Nd13 of the 13 NMOS pipe; The grid Ng13 of the 13 NMOS pipe connects SEN, and drain electrode Nd13 connects Ns12, source electrode Ns13 ground connection VSS; The grid Ng14 of the 14 NMOS pipe connects Pd13, and drain electrode Nd14 connects Pd14, and source electrode Ns14 connects the drain electrode Nd15 of the 15 NMOS pipe; The grid Ng15 of the 15 NMOS pipe connects SN, and drain electrode Nd15 connects Ns14, source electrode Ns15 ground connection VSS; The grid Ng16 of the 16 NMOS pipe connects Pd8, and drain electrode Nd16 connects Pd16, and source electrode Ns16 connects the drain electrode Nd17 of the 17 NMOS pipe; The grid Ng17 of the 17 NMOS pipe connects SN, and drain electrode Nd17 connects Ns16, source electrode Ns17 ground connection VSS; The grid Ng18 of the 18 NMOS pipe connects C, and drain electrode Nd18 connects Pd19, and source electrode Ns18 connects the drain electrode Nd19 of the 19 NMOS pipe; The grid Ng19 of the 19 NMOS pipe connects Pd14, and drain electrode Nd19 connects Ns18, source electrode Ns19 ground connection VSS; The grid Ng20 of the 20 NMOS pipe connects C, and drain electrode Nd20 connects Pd21, and source electrode Ns20 connects the drain electrode Nd21 of the 21 NMOS pipe; The grid Ng21 of the 21 NMOS pipe connects Pd16, and drain electrode Nd21 connects Ns20, source electrode Ns21 ground connection VSS; The 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe and the 5th NMOS pipe, the 6th NMOS pipe, the 8th NMOS pipe form the Scan Architecture in main latch; From latch, four inputs and an output are arranged, four inputs are MO, C, CN, SN, and output is SO; From latch, 12 PMOS pipes and 12 NMOS pipes, consist of, from latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg22 of the 22 PMOS pipe connects MO, and drain electrode Pd22 connects the source electrode Ps23 of the 23 PMOS pipe, and source electrode Ps22 connects power vd D; The grid Pg23 of the 23 PMOS pipe connects CN, and drain electrode Pd23 connects the drain electrode Nd22 of the 22 NMOS pipe, and source electrode Ps23 connects Pd22; The grid Pg24 of the 24 PMOS pipe connects MO, and drain electrode Pd24 connects the source electrode Ps25 of the 25 PMOS pipe, and source electrode Ps24 connects power vd D; The grid Pg25 of the 25 PMOS pipe connects CN, and drain electrode Pd25 connects the drain electrode Nd24 of the 24 NMOS pipe, and source electrode Ps25 connects Pd24; The grid Pg26 of the 26 PMOS pipe connects Pd25, and drain electrode Pd26 connects the drain electrode Nd26 of the 26 NMOS pipe and, as the output SO from latch, source electrode Ps26 connects power vd D; The grid Pg27 of the 27 PMOS pipe connects SN, and drain electrode Pd27 connects Pd26, and source electrode Ps27 connects power vd D; The grid Pg28 of the 28 PMOS pipe connects Pd23, and drain electrode Pd28 connects the drain electrode Nd28 of the 28 NMOS pipe, and source electrode Ps28 connects power vd D; The grid Pg29 of the 29 PMOS pipe connects SN, and drain electrode Pd29 connects Pd28, and source electrode Ps29 connects power vd D; The grid Pg30 of the 30 PMOS pipe connects Pd28, and drain electrode Pd30 connects the source electrode Ps31 of the 31 PMOS pipe, and source electrode Ps30 connects power vd D; The grid Pg31 of the 31 PMOS pipe connects C, and drain electrode Pd31 connects the drain electrode Nd30 of the 30 NMOS pipe, and source electrode Ps31 connects Pd30; The grid Pg32 of the 32 PMOS pipe connects Pd26, and drain electrode Pd32 connects the source electrode Ps33 of the 33 PMOS pipe, and source electrode Ps32 connects power vd D; The grid Pg33 of the 33 PMOS pipe connects C, and drain electrode Pd33 connects the drain electrode Nd32 of the 32 NMOS pipe, and source electrode Ps33 connects Pd32; The grid Ng22 of the 22 NMOS pipe connects C, and drain electrode Nd22 connects Pd23, and source electrode Ns22 connects the drain electrode Nd23 of the 23 NMOS pipe; The grid Ng23 of the 23 NMOS pipe connects MO, and drain electrode Nd23 connects Ns22, source electrode Ns23 ground connection VSS; The grid Ng24 of the 24 NMOS pipe connects C, and drain electrode Nd24 connects Pd25, and source electrode Ns24 connects the drain electrode Nd25 of the 25 NMOS pipe; The grid Ng25 of the 25 NMOS pipe connects MO, and drain electrode Nd25 connects Ns24, source electrode Ns25 ground connection VSS; The grid Ng26 of the 26 NMOS pipe connects Pd23, and drain electrode Nd26 connects Pd26, and source electrode Ns26 connects the drain electrode Nd27 of the 27 NMOS pipe; The grid Ng27 of the 27 NMOS pipe connects SN, and drain electrode Nd27 connects Ns26, source electrode Ns27 ground connection VSS; The grid Ng28 of the 28 NMOS pipe connects Pd25, and drain electrode Nd28 connects Pd28, and source electrode Ns28 connects the drain electrode Nd29 of the 29 NMOS pipe; The grid Ng29 of the 29 NMOS pipe connects SN, and drain electrode Nd29 connects Ns28, source electrode Ns29 ground connection VSS; The grid Ng30 of the 30 NMOS pipe connects CN, and drain electrode Nd30 connects Pd31, and source electrode Ns30 connects the drain electrode Nd31 of the 31 NMOS pipe; The grid Ng31 of the 31 NMOS pipe connects Pd26, and drain electrode Nd31 connects Ns30, source electrode Ns31 ground connection VSS; The grid Ng32 of the 32 NMOS pipe connects CN, and drain electrode Nd32 connects Pd33, and source electrode Ns32 connects the drain electrode Nd33 of the 33 NMOS pipe; The grid Ng33 of the 33 NMOS pipe connects Pd28, and drain electrode Nd33 connects Ns32, source electrode Ns33 ground connection VSS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110323794 CN102361441B (en) | 2011-10-21 | 2011-10-21 | Single event upset resistant settable scanning structure D trigger |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110323794 CN102361441B (en) | 2011-10-21 | 2011-10-21 | Single event upset resistant settable scanning structure D trigger |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102361441A CN102361441A (en) | 2012-02-22 |
| CN102361441B true CN102361441B (en) | 2013-01-02 |
Family
ID=45586702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110323794 Active CN102361441B (en) | 2011-10-21 | 2011-10-21 | Single event upset resistant settable scanning structure D trigger |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102361441B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103825583B (en) * | 2013-12-11 | 2016-08-17 | 中国人民解放军国防科学技术大学 | Anti-single particle upset can synchronous reset d type flip flop with single-ion transient state |
| CN103746678B (en) * | 2014-01-10 | 2016-08-17 | 电子科技大学 | SET ruggedized construction based on protection door replacement circuit |
| CN106603041B (en) * | 2016-11-17 | 2019-07-19 | 电子科技大学 | A kind of trigger based on IGBT latch-up |
| CN110838834B (en) * | 2019-11-11 | 2021-07-23 | 西安电子科技大学 | Reinforced improved QUATRO D trigger of anti single event upset |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2107679A3 (en) * | 2004-02-04 | 2010-01-20 | Japan Aerospace Exploration Agency | Single-event-effect tolerant SOI-based logic device |
| CN101499788A (en) * | 2009-02-19 | 2009-08-05 | 上海交通大学 | Single particle upset and single particle transient pulse resisiting D trigger |
-
2011
- 2011-10-21 CN CN 201110323794 patent/CN102361441B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN102361441A (en) | 2012-02-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102394595B (en) | Settable and resettable D trigger resisting single event upset | |
| CN102394602B (en) | Single event upset-resisting scanning structure D trigger capable of setting and resetting | |
| CN102361442B (en) | Single-event-upset resistant resettable D trigger | |
| CN102394598B (en) | Single event upset resistant synchronously resettable D flip-flop | |
| CN105790734B (en) | Primary particle inversion resistant triplication redundancy d type flip flop of the band from error correction and detection | |
| CN102361440B (en) | Single-event-upset resistant scan structure D trigger capable of being reset synchronously | |
| CN102394597B (en) | D trigger resisting single event upset | |
| CN103825582B (en) | The d type flip flop of anti-single particle upset and single-ion transient state | |
| CN102361441B (en) | Single event upset resistant settable scanning structure D trigger | |
| CN105897222B (en) | The setable Scan Architecture d type flip flop with reset of primary particle inversion resistant high speed | |
| CN102361443B (en) | Single-event-upset resistant resettable scan structure D trigger | |
| CN102394596B (en) | Signal event upset resistance D trigger capable of being set | |
| CN102394600B (en) | Signal particle upset resistance D trigger capable of being set and reset | |
| CN102394599B (en) | Single event upset resistant settable and resettable scan structure D flip-flop | |
| CN103825579B (en) | Anti-single particle upset and the resetted d type flip flop of single-ion transient state | |
| CN103825581B (en) | Anti-single particle upset and the setable d type flip flop of single-ion transient state | |
| CN103825584B (en) | Setable and the reset d type flip flop of anti-single particle upset and single-ion transient state | |
| CN106788380A (en) | A kind of primary particle inversion resistant asynchronous set d type flip flop | |
| CN106712743A (en) | Synchronous reset D trigger for preventing single event upset | |
| CN102394601B (en) | D trigger provided with scanning structure and resisting single event upset | |
| CN103825586B (en) | Anti-single particle upset and the put reset Scan Architecture d type flip flop of single-ion transient state | |
| CN103825580A (en) | Settable scanning structure D trigger resisting single event upset and single event transient | |
| CN103825583B (en) | Anti-single particle upset can synchronous reset d type flip flop with single-ion transient state | |
| CN103856197B (en) | The Scan Architecture d type flip flop of anti-single particle upset and single-ion transient state | |
| CN103825577B (en) | Anti-single particle upset and reducible Scan Architecture d type flip flop of single-ion transient state |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |