CN103825580A

CN103825580A - Settable scanning structure D trigger resisting single event upset and single event transient

Info

Publication number: CN103825580A
Application number: CN201310671682.4A
Authority: CN
Inventors: 郭阳; 喻鑫; 韦静; 梁斌; 池雅庆; 陈书明; 胡春媚; 孙永节; 陈建军; 刘宗林
Original assignee: National University of Defense Technology
Current assignee: National University of Defense Technology
Priority date: 2013-12-11
Filing date: 2013-12-11
Publication date: 2014-05-28
Anticipated expiration: 2033-12-11
Also published as: CN103825580B

Abstract

The invention discloses a settable scanning structure D trigger resisting single event upset and single event transient, so as to solve the problem of poor ability to resist single event upset and single event transient of the settable scanning structure D trigger. According to the invention, the settable scanning structure D trigger is composed of a buffer circuit, a scanning control buffer circuit, a set buffer circuit, a clock circuit, a master latch, a slave latch and an output buffer circuit; the master latch and the slave latch are redundant reinforcement latches; the master latch and the slave latch are connected in series, and are connected with the clock circuit and the set buffer circuit; the master latch is connected with the buffer circuit and the scanning control buffer circuit; and the slave latch is connected with the output buffer circuit. Mutually redundant C2MOS circuits in the master latch and the slave latch are separated, which improves the ability to resist single event upset. Through the buffer circuit, an error is avoided under a long-duration single event transient, and the ability to resist single event transient is further improved through a dual mode redundant pathway.

Description

The setable Scan Architecture d type flip flop of anti-single particle overturn and single-ion transient state

Technical field

The present invention relates to the D master-slave flip-flop of a kind of set structure and Scan Architecture, be particularly related to a kind of anti-single particle overturn (Single Event Upset, and the setable Scan Architecture d type flip flop of anti-single particle transient state (Single Event Transient, SET) SEU).

Background technology

In cosmic space, there are a large amount of high energy particles (proton, electronics, heavy ion etc.), sequence circuit in integrated circuit is subject to after these high-energy particle bombardments, the state of its maintenance likely overturns, this effect is called single-particle inversion effect, the LET(linear energy transfer of single-particle bombardment integrated circuit) value is higher, more easily produces single-particle inversion effect.Combinational circuit in integrated circuit is subject to after these high-energy particle bombardments, likely produce instantaneous electric pulse, this effect is called single-ion transient state effect, and the LET value of single-particle bombardment integrated circuit is higher, the instantaneous electric pulse duration producing is longer, and electric pulse is more easily gathered by sequence circuit.The upset if the state of sequence circuit makes a mistake, or single-ion transient state effect produce instantaneous electric pulse gathered by sequence circuit mistake, all can cause integrated circuit job insecurity even to produce fatal mistake, this is particularly serious in space flight, military field.Therefore, thus to integrated circuit reinforce reduce single-particle inversion effect and single-ion transient state effect more and more important.

D type flip flop is in integrated circuit, to use one of maximum timing unit, the anti-single particle overturn of the ability of its anti-single particle overturn and single-ion transient state to whole integrated circuit and the ability of single-ion transient state play a crucial role, and d type flip flop is carried out to corresponding reinforcing and can make the anti-single particle overturn of integrated circuit and single-ion transient state ability be improved.

Traditional d type flip flop is D master-slave flip-flop, generally forms by main latch with from level series of latches.Common lock storage is replaced with to DICE(Dual Interlocked Storage Cell, double interlocking memory cell) etc. redundancy ruggedized construction can realize primary particle inversion resistant d type flip flop.Transform on this basis input/output port, can realize anti-single particle overturn and single-ion transient state simultaneously.The people such as M.J.Myjak are at The47 ^ththe 47th IEEE Circuits and Systems Midwest international conference of IEEE International Midwest Symposium on Circuits and Systems() on " Enhanced Fault-Tolerant CMOS Memory Elements " (the strengthening fault-tolerant cmos memory cell) of delivering (2004, the I-453～I-456 page) on a kind of improved DICE circuit has been proposed, this circuit adopts DICE circuit to carry out anti-single particle overturn reinforcing, and bidirectional data line is divided into two write data lines and two read data lines, by the duplication redundancy of data wire, make at any time the single event transient pulse that propagates into DICE circuit by a certain data wire be difficult to cause the upset of whole circuit state, thereby realize the reinforcing for single-ion transient state.But there is positive feedback loop in the duplication redundancy of data wire, under compared with the single event transient pulse of long duration, can produce latch information upset, anti-single particle transient state ability is not high.

D.G.Mavis etc. are in the international Reliability Physics meeting of IEEE Reliability Physics Symposium() on time sampling d type flip flop circuit has been proposed in " Soft error rate mitigation techniques for modern microcircuits " (reducing the technology of modern microcircuit soft error rate) (2002 the 216th page-225 pages) of delivering.This circuit has been introduced delay and voting circuit in the feedback loop of latch data, thereby has possessed certain anti-single particle overturn and single-ion transient state ability.But voting circuit itself does not possess the ability of anti-single particle transient state, meeting output error data under single event transient pulse, anti-single particle transient state ability is not high.

Application number is the d type flip flop that 200910046337.5 Chinese patent discloses a kind of anti-single particle overturn and single event transient pulse.This invention is the d type flip flop that a kind of structure is similar to time sampling structure, comprises two variable connectors, two delay circuits, two shutter circuit and three inverters, has realized the reinforcing of anti-single particle overturn and the single-ion transient state of d type flip flop.This patent has the ability of anti-single particle transient state, but because the output Q of the 3rd reverser connects the input VIN0 of second variable connector, formed positive feedback loop, under compared with the single event transient pulse of long duration, can produce latch information upset, anti-single particle transient state ability is not high.

Common D master-slave flip-flop is unfavorable at test phase, circuit being detected, and makes test job become very loaded down with trivial details, complicated.On common D master-slave flip-flop architecture basics, add Scan Architecture, can effectively simplify circuit test work, can be by the input of sweep signal control D master-slave flip-flop at test phase, and then control circuit state.

Some integrated circuit needs the state of d type flip flop in control integration circuit, forces d type flip flop output low level and the data of wherein storage are set to logical one.On the original architecture basics of Scan Architecture d type flip flop, increase setting circuit and asserts signal input, can realize the set structure of d type flip flop, and control the set function of d type flip flop by asserts signal.But at present setable Scan Architecture d type flip flop anti-single particle overturn and anti-single particle transient state ability are not high, are unfavorable for using in the integrated circuit (IC) chip in the fields such as Aeronautics and Astronautics.

Application number is that 201110323794.1 Chinese patent discloses a kind of primary particle inversion resistant setable Scan Architecture d type flip flop, as shown in Figure 1, this invention is by clock circuit, main latch, form from latch, scan control buffer circuit, output buffer, can be under the single-particle bombardment compared with high LET value normal work and do not produce single-particle inversion.Because this invention does not adopt buffer circuit in clock circuit, before main latch, so do not possess the ability of anti-single particle transient state, and main latch, do not adopt duplication redundancy from latch, in the time that the LET value of single-particle bombardment is higher, the some node upsets on circuit can cause whole circuit to overturn.

Summary of the invention

The technical problem to be solved in the present invention is, for current setable Scan Architecture d type flip flop anti-single particle overturn ability and the not high problem of anti-single particle transient state, to propose the setable Scan Architecture d type flip flop of a kind of anti-single particle overturn and single-ion transient state.

Concretism of the present invention is: carry out duplication redundancy reinforcing to main latch with from latch, and can anti-single particle overturn; In clock circuit, in setting circuit and before main latch, add buffer circuit, can anti-single particle transient state; Cut off the positive feedback loop that may be caused by single event transient pulse from latch, can under compared with the single event transient pulse of long duration, not overturn.

The setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state is by buffer circuit, scan control buffer circuit, set buffer circuit, clock circuit, main latch, form from latch, the first output buffer, the second output buffer.Main latch and from latch be redundancy reinforce latch.Main latch and from series connection before and after latch, and be all connected with clock circuit, set buffer circuit.Main latch is also connected with buffer circuit, scan control buffer circuit, is also connected with the first output buffer, the second output buffer from latch.

The setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and anti-single particle transient state has five inputs and two outputs.Five inputs are respectively clock signal input terminal CK, data-signal input D, scan control signal input SE, scan data input terminal SI and asserts signal input SN; Output is Q and QN.

Clock circuit has an input and four outputs, and input is CK, and output is c1, c2, cn1, cn2.Clock circuit is made up of 12 PMOS and ten four NMOSs.The grid Pg53 of the 53 PMOS pipe connects CK, and drain electrode Pd53 connects the drain electrode Nd53 of the 53 NMOS pipe; The grid Pg54 of the 54 PMOS pipe connects the drain electrode Pd53 of the 53 PMOS pipe, and drain electrode Pd54 connects the drain electrode Nd54 of the 54 NMOS pipe, and source electrode Ps54 connects power vd D; The grid Pg55 of the 55 PMOS pipe connects the drain electrode Pd54 of the 54 PMOS pipe, and drain electrode Pd55 connects the drain electrode Nd55 of the 55 NMOS pipe, and source electrode Ps55 connects power vd D; The grid Pg56 of the 56 PMOS pipe connects the drain electrode Pd55 of the 55 PMOS pipe, and drain electrode Pd56 connects the drain electrode Nd56 of the 56 NMOS pipe, and source electrode Ps56 connects power vd D; The grid Pg57 of the 57 PMOS pipe connects CK, and drain electrode Pd57 connects the source electrode Ps58 of the 58 PMOS pipe, and source electrode Ps57 connects VDD; The grid Pg58 of the 58 PMOS pipe connects the drain electrode Pd56 of the 56 PMOS pipe, and drain electrode Pd58 connects the drain electrode Nd57 of the 57 NMOS pipe, and as an output cn1 of clock circuit, source electrode Ps58 connects Pd57; The grid Pg59 of the 59 PMOS pipe connects CK, and drain electrode Pd59 connects the source electrode Ps60 of the 60 PMOS pipe, and source electrode Ps59 connects VDD; The grid Pg60 of the 60 PMOS pipe connects the drain electrode Pd56 of the 56 PMOS pipe, and drain electrode Pd60 connects the drain electrode Nd59 of the 59 NMOS pipe an output cn2 as clock circuit, and source electrode Ps60 connects Pd59; The grid Pg61 of the 61 PMOS pipe is as an output c1 of clock circuit, and drain electrode Pd61 connects the drain electrode Pd58 of the 58 PMOS pipe, and connects output cn1, and source electrode Ps61 connects VDD; The grid Pg62 of the 62 PMOS pipe connects the grid Ng62 of the 62 NMOS pipe an output c2 as clock circuit, drain electrode Pd62 connects the drain electrode Nd62 of the 62 NMOS pipe an output cn2 as clock circuit, and source electrode Ps62 connects VDD; The grid Pg63 of the 63 PMOS pipe connects output cn1, and drain electrode Pd63 connects output c1, and source electrode Ps63 connects VDD; The grid Pg64 of the 64 PMOS pipe connects output cn2, and drain electrode Pd64 connects output c2, and source electrode Ps64 connects VDD; The grid Ng53 of the 53 NMOS pipe connects CK, and drain electrode Nd53 connects the drain electrode Pd53 of the 53 PMOS pipe; The grid Ng54 of the 54 NMOS pipe connects the drain electrode Nd53 of the 53 NMOS pipe, and drain electrode Nd54 connects the drain electrode Pd54 of the 54 PMOS pipe, and source electrode Ns54 connects VSS; The grid Ng55 of the 55 NMOS pipe connects the drain electrode Nd54 of the 54 NMOS pipe, and drain electrode Nd55 connects the drain electrode Pd55 of the 55 PMOS pipe, and source electrode Ns55 connects VSS; The grid Ng56 of the 56 NMOS pipe connects the drain electrode Nd55 of the 55 NMOS pipe, and drain electrode Nd56 connects the drain electrode Pd56 of the 56 PMOS pipe, and source electrode Ns56 connects VSS; The grid Ng57 of the 57 NMOS pipe connects the drain electrode Nd56 of the 56 NMOS pipe, and source electrode Ns57 connects the drain electrode Nd58 of the 58 NMOS pipe, and drain electrode connects cn1; The grid Ng58 of the 58 NMOS pipe connects CK, and drain electrode Nd58 connects the source electrode Nd57 of the 57 NMOS pipe, and source electrode Ns58 connects VSS; The grid Ng59 of the 59 NMOS pipe connects the drain electrode Nd56 of the 56 NMOS pipe, and source electrode Ns59 connects the drain electrode Nd60 of the 60 NMOS pipe, and drain electrode connects cn2; The grid Ng60 of the 60 NMOS pipe connects CK, and drain electrode Nd60 connects the source electrode Nd59 of the 59 NMOS pipe, and source electrode Ns60 connects VSS; The grid Ng61 of the 61 NMOS pipe connects output c1, and drain electrode Nd61 connects output cn2, and source electrode Ns61 connects the drain electrode Nd65 of the 65 NMOS pipe; The grid Ng62 of the 62 NMOS pipe connects output c2, and drain electrode Nd62 connects output cn2, and source electrode Ns62 connects the drain electrode Nd66 of the 66 NMOS pipe; The grid Ng63 of the 63 NMOS pipe connects output cn1, and drain electrode Nd63 connects output c1, and source electrode Ns63 connects VSS; The grid Ng64 of the 64 NMOS pipe connects output cn2, and drain electrode Nd64 connects output c2, and source electrode Ns64 connects VSS; The drain electrode Nd65 of the 65 NMOS pipe connects the source electrode Ns61 of the 61 NMOS pipe, and grid Ng65 connects output c1, and source electrode Ns65 connects VSS; The drain electrode Nd66 of the 66 NMOS pipe connects the source electrode Ns62 of the 62 NMOS pipe, and grid Ng66 connects output c1, and source electrode Ns66 connects VSS.

Buffer circuit has an input and an output, and input is D, and output is D1.Buffer circuit is made up of eight PMOS pipes and eight NMOS pipes, and in buffer circuit, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg1 of the one PMOS pipe connects input D and is connected with the grid Ng1 of a NMOS pipe, and drain electrode Pd1 connects the drain electrode Ng1 of a NMOS pipe, and source electrode Ps1 connects VDD; The grid Pg2 of the 2nd PMOS pipe connects the drain electrode Pd1 of a PMOS pipe, and drain electrode Pd2 connects the drain electrode Nd2 of the 2nd NMOS pipe, and source electrode Ps2 connects VDD; The grid Pg3 of the 3rd PMOS pipe connects the drain electrode Pd2 of the 2nd PMOS pipe, and drain electrode Pd3 connects the drain electrode Nd3 of the 3rd NMOS pipe, and source electrode Ps3 connects VDD; The grid Pg4 of the 4th PMOS pipe connects the drain electrode Pd3 of the 3rd PMOS pipe, and drain electrode Pd4 connects the drain electrode Nd4 of the 4th NMOS pipe, and source electrode Ps4 connects VDD; The grid Pg5 of the 5th PMOS pipe connects the drain electrode Pd4 of the 4th PMOS pipe, and drain electrode Pd5 connects the drain electrode Nd5 of the 5th NMOS pipe, and source electrode Ps5 connects VDD; The grid Pg6 of the 6th PMOS pipe connects the drain electrode Pd5 of the 5th PMOS pipe, and drain electrode Pd6 connects the drain electrode Nd6 of the 6th NMOS pipe, and source electrode Ps6 connects VDD; The grid Pg7 of the 7th PMOS pipe connects the drain electrode Pd6 of the 6th PMOS pipe, and drain electrode Pd7 connects the drain electrode Nd7 of the 7th NMOS pipe, and source electrode Ps7 connects VDD; The grid Pg8 of the 8th PMOS pipe connects the drain electrode Pd7 of the 7th PMOS pipe, and drain electrode Pd8 connects the drain electrode Nd8 of the 8th NMOS pipe the output D1 as buffer, and source electrode Ps8 connects VDD; The grid Ng1 of the one NMOS pipe connects Pg1, and drain electrode Nd1 connects Pd1, and source electrode Ns1 connects VSS; The grid Ng2 of the 2nd NMOS pipe connects the drain electrode Nd1 of a NMOS pipe, and drain electrode Nd2 connects Pd2, and source electrode Ns2 connects VSS; The grid Ng3 of the 3rd NMOS pipe connects the drain electrode Nd2 of the 2nd NMOS pipe, and drain electrode Nd3 connects Pd3, and source electrode Ns3 connects VSS; The grid Ng4 of the 4th NMOS pipe connects the drain electrode Nd3 of the 3rd NMOS pipe, and drain electrode Nd4 connects Pd4, and source electrode Ns4 connects VSS; The grid Ng5 of the 5th NMOS pipe connects the drain electrode Nd4 of the 4th NMOS pipe, and drain electrode Nd5 connects Pd5, and source electrode Ns5 connects VSS; The grid Ng6 of the 6th NMOS pipe connects the drain electrode Nd5 of the 5th NMOS pipe, and drain electrode Nd6 connects Pd6, and source electrode Ns6 connects VSS; The grid Ng7 of the 7th NMOS pipe connects the drain electrode Nd6 of the 6th NMOS pipe, and drain electrode Nd7 connects Pd7, and source electrode Ns7 connects VSS; The grid Ng8 of the 8th NMOS pipe connects the drain electrode Nd7 of the 7th NMOS pipe, and drain electrode Nd8 connects Pd8, and source electrode Ns8 connects VSS.

Scan control buffer circuit has an input and an output, and input is SE, and output is SEN.Scan control buffer circuit is made up of the 39 PMOS pipe and the 39 NMOS pipe.The substrate of the 39 PMOS pipe is all connected power vd D with source electrode Ps39, the equal ground connection VSS of the substrate of the 39 NMOS pipe and source electrode Ns39.The grid Pg39 of the 39 PMOS pipe connects SE, and drain electrode Pd39 connects the drain electrode Nd39 of the 39 NMOS pipe, and as the output SEN of scan control circuit; The grid Ng39 of the 39 NMOS pipe connects SE, and drain electrode Nd39 connects Pd39.

Set buffer circuit has an input and two outputs, and input is SN, and output is SN01, SN02.Set buffer circuit is made up of ten NMOS pipes and ten PMOS pipes, and in set buffer circuit, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg41 of the 41 PMOS pipe connects SN, and drain electrode Pd41 connects the drain electrode Nd41 of the 41 NMOS pipe, and source electrode Ps41 connects power vd D; The grid Pg42 of the 42 PMOS pipe connects the drain electrode Pd41 of the 41 PMOS pipe, and drain electrode Pd42 connects the drain electrode Nd42 of the 42 NMOS pipe, and source electrode Ps42 connects power vd D; The grid Pg43 of the 43 PMOS pipe connects the drain electrode Pd42 of the 42 PMOS pipe, and drain electrode Pd43 connects the drain electrode Nd43 of the 43 NMOS pipe, and source electrode Ps43 connects power vd D; The grid Pg44 of the 44 PMOS pipe connects the drain electrode Pd43 of the 43 PMOS pipe, and drain electrode Pd44 connects the drain electrode Nd44 of the 44 NMOS pipe, and source electrode Ps44 connects power vd D; The grid Pg45 of the 45 PMOS pipe connects SN, and drain electrode Pd45 connects the source electrode Ps46 of the 46 PMOS pipe, and source electrode Ps45 connects VDD; The grid Pg46 of the 46 PMOS pipe connects the drain electrode Pd44 of the 44 PMOS pipe, and drain electrode Pd46 connects the drain electrode Nd45 of the 45 NMOS pipe; The grid Pg47 of the 47 PMOS pipe connects SN, and drain electrode Pd47 connects the source electrode Ps48 of the 48 PMOS pipe, and source electrode Ps47 connects VDD; The grid Pg48 of the 48 PMOS pipe connects the drain electrode Pd44 of the 44 PMOS pipe, and drain electrode Pd48 connects the drain electrode Nd47 of the 47 NMOS pipe, and source electrode Ps48 connects the drain electrode Pd47 of the 47 PMOS pipe; The grid Pg49 of the 49 PMOS pipe connects the drain electrode Pd46 of the 46 PMOS pipe, and source electrode Ps49 connects power vd D, and drain electrode Pd49 connects the drain electrode Nd49 of the 49 NMOS pipe an output SN01 as set buffer circuit; The grid Pg50 of the 50 PMOS pipe connects the drain electrode Pd48 of the 48 PMOS pipe, and source electrode Ps50 connects power vd D, and drain electrode Pd50 connects the drain electrode Nd50 of the 50 NMOS pipe another output SN02 as set buffer circuit; The grid Ng41 of the 41 NMOS pipe connects SN, and drain electrode Nd41 connects the drain electrode Pd41 of the 41 PMOS pipe, and source electrode Ns41 connects VSS; The grid Ng42 of the 42 NMOS pipe connects the drain electrode Nd41 of the 41 NMOS pipe, and drain electrode Nd42 connects the drain electrode Pd42 of the 42 PMOS pipe, and source electrode Ns42 connects VSS; The grid Ng43 of the 43 NMOS pipe connects the drain electrode Nd42 of the 42 NMOS pipe, and drain electrode Nd43 connects the drain electrode Pd43 of the 43 PMOS pipe, and source electrode Ns43 connects VSS; The grid Ng44 of the 44 NMOS pipe connects the drain electrode Nd43 of the 43 NMOS pipe, and drain electrode Nd44 connects the drain electrode Pd44 of the 44 PMOS pipe, and source electrode Ns44 connects VSS; The grid Ng45 of the 45 NMOS pipe connects the drain electrode Nd44 of the 44 NMOS pipe, and source electrode Ns45 connects the drain electrode Nd46 of the 46 NMOS pipe, and drain electrode Nd45 connects the 49 NMOS tube grid Ng49; The grid Ng46 of the 46 NMOS pipe connects SN, and drain electrode Nd46 connects the source electrode Nd45 of the 45 NMOS pipe, and source electrode Ns46 connects VSS; The grid Ng47 of the 47 NMOS pipe connects the drain electrode Nd44 of the 44 NMOS pipe, and source electrode Ns47 connects the drain electrode Nd48 of the 48 NMOS pipe, and drain electrode Nd47 connects the 50 NMOS tube grid Ng50; The grid Ng48 of the 48 NMOS pipe connects SN, and drain electrode Nd48 connects the source electrode Nd47 of the 47 NMOS pipe, and source electrode Ns48 connects VSS.The grid Ng49 of the 49 NMOS pipe connects the drain electrode Nd45 of the 45 NMOS pipe, and source electrode Ns49 connects ground VSS, and drain electrode Nd49 connects the drain electrode Pd49 of the 49 PMOS pipe and connects output SN01; The grid Ng50 of the 50 NMOS pipe connects the 47 NMOS pipe drain electrode Nd47, and drain electrode Nd50 connects the drain electrode Nd50 of the 50 PMOS pipe and connects output SN02, and source electrode Ns50 connects VSS.

Main latch has 11 inputs and two outputs, and input is D, D1, SI, SE, SEN, SN01, SN02, c1, c2, cn1, cn2; Output is m1, m1r.Main latch is made up of 18 PMOS pipes and 18 NMOS pipes, and in main latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg9 of the 9th PMOS pipe connects SI, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS pipe, and source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects SEN, and drain electrode Pd10 connects the source electrode Ps13 of the 13 PMOS pipe, and source electrode Ps10 connects Pd9; The grid Pg11 of the 11 PMOS pipe connects SE, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects D, and drain electrode Pd12 connects Ps13, and source electrode Ps12 connects Pd11; The grid Pg8 of the 13 PMOS pipe connects c1, and drain electrode Pd13 connects the drain electrode Nd9 of the 9th NMOS pipe, and source electrode Ps13 connects Pd10; The grid Pg14 of the 14 PMOS pipe connects SI, and drain electrode Pd14 connects the source electrode Ps15 of the 15 PMOS pipe, and source electrode Ps14 connects power vd D; The grid Pg15 of the 15 PMOS pipe connects SEN, and drain electrode Pd15 connects the source electrode Ps18 of the 18 PMOS pipe, and source electrode Ps15 connects Pd14; The grid Pg16 of the 16 PMOS pipe connects SE, and drain electrode Pd16 connects the source electrode Ps17 of the 17 PMOS pipe, and source electrode Ps16 connects power vd D; The grid Pg17 of the 17 PMOS pipe connects D1, and drain electrode Pd17 connects the source electrode Ps18 of the 18 PMOS pipe, and source electrode Ps17 connects Pd16; The grid Pg18 of the 18 PMOS pipe connects c2, and drain electrode Pd18 connects the drain electrode Nd14 of the 14 NMOS pipe, and source electrode Ps18 connects Pd15; The grid Pg19 of the 19 PMOS pipe connects the drain electrode Pd13 of the 13 PMOS pipe, and drain electrode Pd19 connects the drain electrode Nd19 of the 19 NMOS pipe, and as an output m1 of main latch, source electrode Ps19 connects power vd D; The grid Pg20 of the 20 PMOS pipe connects SN01, and drain electrode Pd20 connects the drain electrode Nd19 of the 19 NMOS pipe, and connects output m1, and source electrode Ps20 connects power vd D; The grid Pg21 of the 21 PMOS pipe connects the drain electrode Pd18 of the 18 PMOS pipe, and drain electrode Pd21 connects the drain electrode Nd21 of the 21 NMOS pipe, and as an output m1r of main latch, source electrode Ps21 connects power vd D; The grid Pg22 of the 22 PMOS pipe connects SN02, and drain electrode Pd22 connects the drain electrode Nd21 of the 21 NMOS pipe, and connects output m1r, and source electrode Ps22 connects power vd D; The grid Pg23 of the 23 PMOS pipe connects Pd22, and drain electrode Pd23 connects the source electrode Ps24 of the 24 PMOS pipe, and source electrode Ps23 connects power vd D; The grid Pg24 of the 24 PMOS pipe connects cn1, and drain electrode Pd24 connects the drain electrode Nd23 of the 23 NMOS pipe, and source electrode Ps24 connects Pd23; The grid Pg25 of the 25 PMOS pipe connects Pd20, and drain electrode Pd25 connects the source electrode Ps26 of the 26 PMOS pipe, and source electrode Ps25 connects power vd D; The grid Pg26 of the 26 PMOS pipe connects cn2, and drain electrode Pd26 connects the drain electrode Nd25 of the 25 NMOS pipe and is connected with Pd18, and source electrode Ps26 connects Pd25; The grid Ng9 of the 9th NMOS pipe connects cn1, and drain electrode Nd9 connects Pd13, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe; The grid Ng10 of the tenth NMOS pipe connects SE, and drain electrode Nd10 connects Ns9, and source electrode Ns10 connects the drain electrode Nd11 of the 11 NMOS pipe; The grid Ng11 of the 11 NMOS pipe connects SI, and drain electrode Nd11 connects Ns10, source electrode Ns11 ground connection VSS; The grid Ng12 of the 12 NMOS pipe connects D, and drain electrode Nd12 connects Ns9, and source electrode Ns12 connects the drain electrode Nd13 of the 13 NMOS pipe; The grid Ng13 of the 13 NMOS pipe connects SEN, and drain electrode Nd13 connects Ns12, source electrode Ns13 ground connection VSS; The grid Ng14 of the 14 NMOS pipe connects cn2, and drain electrode Nd14 connects Pd18, and source electrode Ns14 connects the drain electrode Nd15 of the 15 NMOS pipe; The grid Ng15 of the 15 NMOS pipe connects SE, and drain electrode Nd15 connects Ns14, and source electrode Ns15 connects the drain electrode Nd16 of the 16 NMOS pipe; The grid Ng16 of the 16 NMOS pipe connects SI, and drain electrode Nd16 connects Ns15, source electrode Ns16 ground connection VSS; The grid Ng17 of the 17 NMOS pipe connects D1, and drain electrode Nd17 connects Ns14, and source electrode Ns17 connects the drain electrode Nd18 of the 18 NMOS pipe; The grid Ng18 of the 18 NMOS pipe connects SEN, and drain electrode Nd18 connects Ns17, source electrode Ns18 ground connection VSS; The grid Ng19 of the 19 NMOS pipe connects Pd18, and drain electrode Nd19 connects Pd20, and source electrode Ns19 meets the 20 NMOS pipe drain electrode Nd20; The grid Ng20 of the 20 NMOS pipe connects SN02, and drain electrode Nd20 connects Ns19, source electrode Ns20 ground connection VSS; The grid Ng21 of the 21 NMOS pipe connects Pd18, and drain electrode Nd21 connects Pd22, and source electrode Ns21 meets the drain electrode Nd22 of the 22 NMOS pipe; The grid Ng22 of the 22 NMOS pipe connects SN01, and drain electrode Nd22 connects Ns21, source electrode Ns22 ground connection VSS; The grid Ng23 of the 23 NMOS pipe connects c1, and drain electrode Nd23 connects Pd24, and source electrode Ns23 connects the drain electrode Nd24 of the 24 NMOS pipe; The grid Ng24 of the 24 NMOS pipe connects Pd20, and drain electrode Nd24 connects Ns23, source electrode Ns24 ground connection VSS; The grid Ng25 of the 25 NMOS pipe connects c2, and drain electrode Nd25 connects Pd26, and source electrode Ns25 connects the drain electrode Nd26 of the 26 NMOS pipe; The grid Ng26 of the 26 NMOS pipe connects Pd22, and drain electrode Nd26 connects Ns25, source electrode Ns26 ground connection VSS.Scan Architecture in the 9th PMOS pipe, the tenth PMOS pipe, the 11 PMOS pipe and the tenth NMOS pipe, the 11 NMOS pipe, the 13 NMOS pipe composition main latch.Set structure in the 20 PMOS pipe and the 20 NMOS pipe composition main latch.

Have eight inputs and two outputs from latch, input is SN01, SN02, c1, c2, cn1, cn2, m1, m1r; Output is s1, s1r.Be made up of 12 PMOS pipes and 12 NMOS pipes from latch, from latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg27 of the 27 PMOS pipe connects m1r, and drain electrode Pd27 connects the source electrode Ps28 of the 28 PMOS pipe, and source electrode Ps27 connects power vd D; The grid Pg28 of the 28 PMOS pipe connects cn1, and drain electrode Pd28 connects the drain electrode Nd27 of the 27 NMOS pipe, and source electrode Ps28 connects Pd27; The grid Pg29 of the 29 PMOS pipe connects m1, and drain electrode Pd29 connects the source electrode Ps30 of the 30 PMOS pipe, and source electrode Ps29 connects power vd D; The grid Pg30 of the 30 PMOS pipe connects cn2, and drain electrode Pd30 connects the drain electrode Nd29 of the 29 NMOS pipe, and source electrode Ps30 connects Pd29; The grid Pg31 of the 31 PMOS pipe connects the drain electrode Pd28 of the 28 PMOS pipe, and drain electrode Pd31 connects the drain electrode Nd31 of the 31 NMOS pipe and as an output s1 from latch, source electrode Ps31 connects power vd D; The grid Pg32 of the 32 PMOS pipe connects SN01, and drain electrode Pd32 connects the drain electrode Nd31 of the 31 NMOS pipe, and connects output s1, and source electrode Ps32 connects power vd D; The grid Pg33 of the 33 PMOS pipe connects the drain electrode Pd30 of the 30 PMOS pipe, and drain electrode Pd33 connects the drain electrode Nd33 of the 33 NMOS pipe, and as an output s1r from latch, source electrode Ps33 connects power vd D; The grid Pg34 of the 34 PMOS pipe connects SN02, and drain electrode Pd34 connects the drain electrode Nd33 of the 33 NMOS pipe, and connects output s1r, and source electrode Ps34 connects power vd D; The grid Pg35 of the 35 PMOS pipe connects Pd34, and drain electrode Pd35 connects the source electrode Ps36 of the 36 PMOS pipe, and source electrode Ps35 connects power vd D; The grid Pg36 of the 36 PMOS pipe connects cn1, and drain electrode Pd36 connects the drain electrode Nd35 of the 35 NMOS pipe, and source electrode Ps36 connects Pd35; The grid Pg37 of the 37 PMOS pipe connects Pd32, and drain electrode Pd37 connects the source electrode Ps38 of the 38 PMOS pipe, and source electrode Ps37 connects power vd D; The grid Pg38 of the 38 PMOS pipe connects cn2, and drain electrode Pd38 connects the drain electrode Nd37 of the 37 NMOS pipe, and source electrode Ps38 connects Pd37; The grid Ng27 of the 27 NMOS pipe connects c, and drain electrode Nd27 connects Pd28, and source electrode Ns27 connects the drain electrode Nd28 of the 28 NMOS pipe; The grid Ng28 of the 28 NMOS pipe connects m1, and drain electrode Nd28 connects Ns27, source electrode Ns28 ground connection VSS; The grid Ng29 of the 29 NMOS pipe connects c2, and drain electrode Nd29 connects Pd30, and source electrode Ns29 connects the drain electrode Nd30 of the 30 NMOS pipe; The grid Ng30 of the 30 NMOS pipe connects m1r, and drain electrode Nd30 connects Ns29, source electrode Ns30 ground connection VSS; The grid Ng31 of the 31 NMOS pipe connects Pd30, and drain electrode Nd31 connects Pd32, and source electrode Ns31 connects the drain electrode Nd32 of the 32 NMOS pipe; The grid Ng32 of the 32 NMOS pipe connects SN02, and drain electrode Nd32 connects Ns31, source electrode Ns32 ground connection VSS; The grid Ng33 of the 33 NMOS pipe connects Pd28, and drain electrode Nd33 connects Pd34, and source electrode Ns33 meets the drain electrode Nd34 of the 34 NMOS pipe; The grid Ng34 of the 34 NMOS pipe connects SN01, and drain electrode Nd34 connects Ns33, source electrode Ns34 ground connection VSS; The grid Ng35 of the 35 NMOS pipe connects c1, and drain electrode Nd35 connects Pd36, and source electrode Ns35 connects the drain electrode Nd36 of the 36 NMOS pipe; The grid Ng36 of the 36 NMOS pipe connects Pd32, and drain electrode Nd36 connects Ns35, source electrode Ns36 ground connection VSS; The grid Ng37 of the 37 NMOS pipe connects c2, and drain electrode Nd37 connects Pd38, and source electrode Ns37 connects the drain electrode Nd38 of the 38 NMOS pipe; The grid Ng38 of the 38 NMOS pipe connects Pd34, and drain electrode Nd38 connects Ns37, source electrode Ns38 ground connection VSS.The 32 PMOS pipe and the set structure of the 32 NMOS pipe composition from latch.

The first output buffer has two inputs and an output, and input connects s1 and s1r, and output is Q.Output buffer is made up of two PMOS pipes and two NMOS pipes.The substrate of all PMOS pipes of output buffer connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg51 of the 51 PMOS pipe meets input s1r, and drain electrode Pd51 connects the drain electrode Nd51 of the 51 NMOS pipe, and source electrode Ps51 meets power vd D; The grid Pg52 of the 52 PMOS pipe meets Pd51, and drain electrode Pd52 connects the drain electrode Nd52 of the 52 NMOS pipe, and as the output Q of output buffer; Source electrode Ps52 meets power vd D; The grid Ng51 of the 51 NMOS pipe meets input s1, and drain electrode Nd51 connects Pd51, source electrode Ns51 ground connection VSS; The grid Ng52 of the 52 NMOS pipe meets Nd51, and drain electrode Nd52 connects Pd52, source electrode Ns52 ground connection VSS.

The second output buffer has two inputs and an output, and input connects s1 and s1r, and output is QN.Output buffer is made up of a PMOS pipe and a NMOS pipe.The substrate of PMOS pipe connects power vd D, the substrate ground connection VSS of NMOS pipe.The grid Pg40 of the 40 PMOS pipe meets input s1, and drain electrode Pd40 connects the drain electrode Nd40 of the 40 NMOS pipe, and as the output QN of buffer circuit, source electrode Ps40 meets power vd D; The grid Ng40 of the 40 NMOS pipe meets input s1r, and drain electrode Nd40 connects Pd40, and connects output QN, source electrode Ns40 ground connection VSS.

The setable Scan Architecture d type flip flop course of work of anti-single particle overturn of the present invention and single-ion transient state is as follows:

The setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state also can enter SM set mode the time marquis in scanning mode, and scanning mode and SM set mode can exist simultaneously.The setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention can carry out set at any time, and set function is the control of asserts signal input by SN.

When SN is that low level, SE are while being any level, the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state is all in SM set mode, be main latch and from latch all by latching logic " 1 " by force, output Q and the QN of output buffer are respectively high level and low level.

When SN is that high level, SE are while being low level, the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state is in normal operating conditions, be that clock circuit receives CK, after CK is cushioned, produce respectively with anti-phase cn1, the cn2 of CK and with c1, the c2 of CK homophase, and cn1, cn2 with c1, c2 are passed to main latch and from latch.Buffer circuits receives D, D being postponed to the D1 of rear output and D homophase, is between low period at CK, and cn1, cn2 are high level, c1, c2 are low level, main latch is opened, and receives D and D1, and in D and D1 may with single event transient pulse carry out filtering, then by m1, the m1r of latch output and D, D1 homophase,, do not receive m1, the m1r of main latch output, but preserve m1, the m1r that a CK trailing edge samples in preservation state from latch; Be between high period at CK, cn1, cn2 are that low level, c1, c2 are high level, main latch is in preservation state, preserve D, D1 that previous CK rising edge samples output and D, D1 homophase, open and receive output m1, the m1r of main latch from latch, and m1, m1r are carried out to s1, the s1r of buffered output and m1, m1r homophase.Output buffer all will receive output s1, the s1r from latch at any time, to s1, s1r buffering output and the anti-phase QN of s1, s1r and with the Q of s1, s1r homophase.

When SN is that high level, SE are while being high level, the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state is in scanning mode, be that clock circuit receives CK, after CK is cushioned, produce respectively with anti-phase cn1, the cn2 of CK and with c1, the c2 of CK homophase, and cn1, cn2 with c1, c2 are passed to main latch and from latch.Be between low period at CK, cn1, cn2 are high level, c1, c2 are low level, main latch is opened, the m1, the m1r that receive SI and it is carried out to output and SI homophase after buffered,, do not receive m1, the m1r of main latch output but preserve m1, the m1r that a CK trailing edge samples in preservation state from latch; Be between high period at CK, cn1, cn2 are that low level, c1, c2 are high level, main latch is in preservation state, preserve m1, the m1r of SI that previous CK rising edge samples output and SI homophase, open and receive output m1, the m1r of main latch from latch, m1, m1r are carried out to s1, the s1r of buffered output and m1, m1r homophase.Output buffer all will receive output s1, the s1r from latch at any time, to s1, s1r buffering output and the anti-phase QN of s1, s1r and with the Q of s1, s1r homophase.

Scan control buffer circuit carries out input signal to export the SEN anti-phase with SE after buffered, and is sent into main latch, scans the control of behavior.

After set buffer circuit postpones input signal by the C of duplication redundancy ²in MOS structure filtering SN may with single event transient pulse, and by output with the SN01 of SN homophase and SN02 sends into main latch and from latch, carry out the control of set behavior.

Adopt the present invention can reach following technique effect:

The anti-single particle overturn of the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and anti-single particle transient state and anti-single particle transient state ability are better than that setable Scan Architecture d type flip flop is reinforced in tradition unguyed setable Scan Architecture d type flip flop, time sampling and traditional duplication redundancy is reinforced setable Scan Architecture d type flip flop.The present invention transforms the unguyed setable Scan Architecture d type flip flop structure of tradition, has all carried out duplication redundancy reinforcing to main latch with from latch, and for main latch and from latch C ²mOS circuit improves, and separates the C of redundancy each other ²on in MOS circuit, draw PMOS pipe and pull-down NMOS pipe, improved the primary particle inversion resistant ability of the present invention.In clock circuit He before main latch, add buffer circuit, the present invention is not made a mistake under long-term single event transient pulse; By well-designed duplication redundancy path, cut off the positive feedback loop that may be caused by single event transient pulse from latch, further increase the ability of anti-single particle transient state.The setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state is suitable for the standard cell lib of anti-single particle overturn and anti-single particle transient state reinforcing integrated circuit, is applied to the fields such as Aeronautics and Astronautics.

Accompanying drawing explanation

Fig. 1 is that application number is 201110323794.1 the setable Scan Architecture d type flip flop overall logic structural representation of anti-single particle overturn

Fig. 2 is the setable Scan Architecture d type flip flop overall logic structural representation of anti-single particle overturn of the present invention and single-ion transient state.

Fig. 3 be anti-single particle overturn of the present invention and single-ion transient state setable Scan Architecture d type flip flop in clock circuit structural representation.

Fig. 4 is buffer circuit structural representation in the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state.

Fig. 5 is scan control buffer circuit structural representation in the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state.

Fig. 6 is the mid-bit buffering electrical block diagram of the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state.

Fig. 7 is main latch structural representation in the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state.

Fig. 8 is from latch structure schematic diagram in the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state.

Fig. 9 is the first output buffer structural representation in the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state.

Figure 10 is the second output buffer structural representation in the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state.

Embodiment

Fig. 2 is the setable Scan Architecture d type flip flop logical construction schematic diagram of anti-single particle overturn of the present invention and single-ion transient state.The present invention is by clock circuit (as shown in Figure 3), buffer circuit (as shown in Figure 4), scan control buffer circuit (as shown in Figure 5), set buffer circuit (as shown in Figure 6), main latch (as shown in Figure 7), form from latch (as shown in Figure 8), the first output buffer (as shown in Figure 9) and the second buffer circuit (shown in Figure 10).The setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and anti-single particle transient state has five inputs and two outputs.Four inputs are respectively clock signal input terminal CK, data-signal input D, scan control signal input SE, scan data input terminal SI and asserts signal input SN; Output is respectively Q and QN.Clock circuit receives CK, and CK is carried out exporting respectively c1, c2 and cn1, cn2 after buffered.Buffer circuit receives D, and D is carried out exporting respectively D1 after buffered.Scan control buffer circuit receives SE, and SE is carried out exporting respectively SEN after buffered.Set buffer circuit receives SN, and SN is carried out exporting SN01, SN02 after buffered.Main latch receives D, D1, SI, SE, SEN, c1, c2, cn1, cn2, SN01, SN02, and main latch is at SE, SEN, c1, c2, cn1, cn2, SN01, output m1, m1r after under the control of SN02, D, D1 or SI being carried out latch etc. and processed.Receive m1, m1r and c1, c2, cn1, cn2, SN01, SN02 from latch, m1, m1r are carried out under the control of c1, c2, cn1, cn2, SN01, SN02 from latch exporting respectively s1, s1r after the processing such as latch.Output buffer receives s1, s1r, and it is carried out exporting Q and QN after buffered.SN is high level, SE while being low level, and the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state is in normal operating conditions; SN is high level, SE while being high level, and the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state is in scanning work state; When SN is low level, the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state enters SM set mode.

As shown in Figure 3, clock circuit has an input and four outputs, and input is CK, and output is c1, c2, cn1, cn2.Clock circuit is made up of 12 PMOS and ten four NMOSs.The grid Pg53 of the 53 PMOS pipe connects CK, and drain electrode Pd53 connects the drain electrode Nd53 of the 53 NMOS pipe; The grid Pg54 of the 54 PMOS pipe connects the drain electrode Pd53 of the 53 PMOS pipe, and drain electrode Pd54 connects the drain electrode Nd54 of the 54 NMOS pipe, and source electrode Ps54 connects power vd D; The grid Pg55 of the 55 PMOS pipe connects the drain electrode Pd54 of the 54 PMOS pipe, and drain electrode Pd55 connects the drain electrode Nd55 of the 55 NMOS pipe, and source electrode Ps55 connects power vd D; The grid Pg56 of the 56 PMOS pipe connects the drain electrode Pd55 of the 55 PMOS pipe, and drain electrode Pd56 connects the drain electrode Nd56 of the 56 NMOS pipe, and source electrode Ps56 connects power vd D; The grid Pg57 of the 57 PMOS pipe connects CK, and drain electrode Pd57 connects the source electrode Ps58 of the 58 PMOS pipe, and source electrode Ps57 connects VDD; The grid Pg58 of the 58 PMOS pipe connects the drain electrode Pd56 of the 56 PMOS pipe, and drain electrode Pd58 connects the drain electrode Nd57 of the 57 NMOS pipe, and as an output cn1 of clock circuit, source electrode Ps58 connects Pd57; The grid Pg59 of the 59 PMOS pipe connects CK, and drain electrode Pd59 connects the source electrode Ps60 of the 60 PMOS pipe, and source electrode Ps59 connects VDD; The grid Pg60 of the 60 PMOS pipe connects the drain electrode Pd56 of the 56 PMOS pipe, and drain electrode Pd60 connects the drain electrode Nd59 of the 59 NMOS pipe an output cn2 as clock circuit, and source electrode Ps60 connects Pd59; The grid Pg61 of the 61 PMOS pipe is as an output c1 of clock circuit, and drain electrode Pd61 connects the drain electrode Pd58 of the 58 PMOS pipe, and connects output cn1, and source electrode Ps61 connects VDD; The grid Pg62 of the 62 PMOS pipe connects the grid Ng62 of the 62 NMOS pipe an output c2 as clock circuit, drain electrode Pd62 connects the drain electrode Nd62 of the 62 NMOS pipe an output cn2 as clock circuit, and source electrode Ps62 connects VDD; The grid Pg63 of the 63 PMOS pipe connects output cn1, and drain electrode Pd63 connects output c1, and source electrode Ps63 connects VDD; The grid Pg64 of the 64 PMOS pipe connects output cn2, and drain electrode Pd64 connects output c2, and source electrode Ps64 connects VDD; The grid Ng53 of the 53 NMOS pipe connects CK, and drain electrode Nd53 connects the drain electrode Pd53 of the 53 PMOS pipe; The grid Ng54 of the 54 NMOS pipe connects the drain electrode Nd53 of the 53 NMOS pipe, and drain electrode Nd54 connects the drain electrode Pd54 of the 54 PMOS pipe, and source electrode Ns54 connects VSS; The grid Ng55 of the 55 NMOS pipe connects the drain electrode Nd54 of the 54 NMOS pipe, and drain electrode Nd55 connects the drain electrode Pd55 of the 55 PMOS pipe, and source electrode Ns55 connects VSS; The grid Ng56 of the 56 NMOS pipe connects the drain electrode Nd55 of the 55 NMOS pipe, and drain electrode Nd56 connects the drain electrode Pd56 of the 56 PMOS pipe, and source electrode Ns56 connects VSS; The grid Ng57 of the 57 NMOS pipe connects the drain electrode Nd56 of the 56 NMOS pipe, and source electrode Ns57 connects the drain electrode Nd58 of the 58 NMOS pipe, and drain electrode connects cn1; The grid Ng58 of the 58 NMOS pipe connects CK, and drain electrode Nd58 connects the source electrode Nd57 of the 57 NMOS pipe, and source electrode Ns58 connects VSS; The grid Ng59 of the 59 NMOS pipe connects the drain electrode Nd56 of the 56 NMOS pipe, and source electrode Ns59 connects the drain electrode Nd60 of the 60 NMOS pipe, and drain electrode connects cn2; The grid Ng60 of the 60 NMOS pipe connects CK, and drain electrode Nd60 connects the source electrode Nd59 of the 59 NMOS pipe, and source electrode Ns60 connects VSS; The grid Ng61 of the 61 NMOS pipe connects output c1, and drain electrode Nd61 connects output cn2, and source electrode Ns61 connects the drain electrode Nd65 of the 65 NMOS pipe; The grid Ng62 of the 62 NMOS pipe connects output c2, and drain electrode Nd62 connects output cn2, and source electrode Ns62 connects the drain electrode Nd66 of the 66 NMOS pipe; The grid Ng63 of the 63 NMOS pipe connects output cn1, and drain electrode Nd63 connects output c1, and source electrode Ns63 connects VSS; The grid Ng64 of the 64 NMOS pipe connects output cn2, and drain electrode Nd64 connects output c2, and source electrode Ns64 connects VSS; The drain electrode Nd65 of the 65 NMOS pipe connects the source electrode Ns61 of the 61 NMOS pipe, and grid Ng65 connects output c1, and source electrode Ns65 connects VSS; The drain electrode Nd66 of the 66 NMOS pipe connects the source electrode Ns62 of the 62 NMOS pipe, and grid Ng66 connects output c1, and source electrode Ns66 connects VSS.

As shown in Figure 4, buffer circuit has an input and an output, and input is D, and output is D1.Buffer circuit is made up of eight PMOS pipes and eight NMOS pipes, and in buffer circuit, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg1 of the one PMOS pipe connects input D and is connected with the grid Ng1 of a NMOS pipe, and drain electrode Pd1 connects the drain electrode Ng1 of a NMOS pipe, and source electrode Ps1 connects VDD; The grid Pg2 of the 2nd PMOS pipe connects the drain electrode Pd1 of a PMOS pipe, and drain electrode Pd2 connects the drain electrode Nd2 of the 2nd NMOS pipe, and source electrode Ps2 connects VDD; The grid Pg3 of the 3rd PMOS pipe connects the drain electrode Pd2 of the 2nd PMOS pipe, and drain electrode Pd3 connects the drain electrode Nd3 of the 3rd NMOS pipe, and source electrode Ps3 connects VDD; The grid Pg4 of the 4th PMOS pipe connects the drain electrode Pd3 of the 3rd PMOS pipe, and drain electrode Pd4 connects the drain electrode Nd4 of the 4th NMOS pipe, and source electrode Ps4 connects VDD; The grid Pg5 of the 5th PMOS pipe connects the drain electrode Pd4 of the 4th PMOS pipe, and drain electrode Pd5 connects the drain electrode Nd5 of the 5th NMOS pipe, and source electrode Ps5 connects VDD; The grid Pg6 of the 6th PMOS pipe connects the drain electrode Pd5 of the 5th PMOS pipe, and drain electrode Pd6 connects the drain electrode Nd6 of the 6th NMOS pipe, and source electrode Ps6 connects VDD; The grid Pg7 of the 7th PMOS pipe connects the drain electrode Pd6 of the 6th PMOS pipe, and drain electrode Pd7 connects the drain electrode Nd7 of the 7th NMOS pipe, and source electrode Ps7 connects VDD; The grid Pg8 of the 8th PMOS pipe connects the drain electrode Pd7 of the 7th PMOS pipe, and drain electrode Pd8 connects the drain electrode Nd8 of the 8th NMOS pipe the output D1 as buffer, and source electrode Ps8 connects VDD; The grid Ng1 of the one NMOS pipe connects Pg1, and drain electrode Nd1 connects Pd1, and source electrode Ns1 connects VSS; The grid Ng2 of the 2nd NMOS pipe connects the drain electrode Nd1 of a NMOS pipe, and drain electrode Nd2 connects Pd2, and source electrode Ns2 connects VSS; The grid Ng3 of the 3rd NMOS pipe connects the drain electrode Nd2 of the 2nd NMOS pipe, and drain electrode Nd3 connects Pd3, and source electrode Ns3 connects VSS; The grid Ng4 of the 4th NMOS pipe connects the drain electrode Nd3 of the 3rd NMOS pipe, and drain electrode Nd4 connects Pd4, and source electrode Ns4 connects VSS; The grid Ng5 of the 5th NMOS pipe connects the drain electrode Nd4 of the 4th NMOS pipe, and drain electrode Nd5 connects Pd5, and source electrode Ns5 connects VSS; The grid Ng6 of the 6th NMOS pipe connects the drain electrode Nd5 of the 5th NMOS pipe, and drain electrode Nd6 connects Pd6, and source electrode Ns6 connects VSS; The grid Ng7 of the 7th NMOS pipe connects the drain electrode Nd6 of the 6th NMOS pipe, and drain electrode Nd7 connects Pd7, and source electrode Ns7 connects VSS; The grid Ng8 of the 8th NMOS pipe connects the drain electrode Nd7 of the 7th NMOS pipe, and drain electrode Nd8 connects Pd8, and source electrode Ns8 connects VSS.

As shown in Figure 5, scan control buffer circuit has an input and an output, and input is SE, and output is SEN.Scan control buffer circuit is made up of the 39 PMOS pipe and the 39 NMOS pipe.The substrate of the 39 PMOS pipe is all connected power vd D with source electrode Ps39, the equal ground connection VSS of the substrate of the 39 NMOS pipe and source electrode Ns39.The grid Pg39 of the 39 PMOS pipe connects SE, and drain electrode Pd39 connects the drain electrode Nd39 of the 39 NMOS pipe, and as the output SEN of scan control circuit; The grid Ng39 of the 39 NMOS pipe connects SE, and drain electrode Nd39 connects Pd39.

As shown in Figure 6, set buffer circuit has an input and two outputs, and input is SN, and output is SN01, SN02.Set buffer circuit is made up of ten NMOS pipes and ten PMOS pipes, and in set buffer circuit, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg41 of the 41 PMOS pipe connects SN, and drain electrode Pd41 connects the drain electrode Nd41 of the 41 NMOS pipe, and source electrode Ps41 connects power vd D; The grid Pg42 of the 42 PMOS pipe connects the drain electrode Pd41 of the 41 PMOS pipe, and drain electrode Pd42 connects the drain electrode Nd42 of the 42 NMOS pipe, and source electrode Ps42 connects power vd D; The grid Pg43 of the 43 PMOS pipe connects the drain electrode Pd42 of the 42 PMOS pipe, and drain electrode Pd43 connects the drain electrode Nd43 of the 43 NMOS pipe, and source electrode Ps43 connects power vd D; The grid Pg44 of the 44 PMOS pipe connects the drain electrode Pd43 of the 43 PMOS pipe, and drain electrode Pd44 connects the drain electrode Nd44 of the 44 NMOS pipe, and source electrode Ps44 connects power vd D; The grid Pg45 of the 45 PMOS pipe connects SN, and drain electrode Pd45 connects the source electrode Ps46 of the 46 PMOS pipe, and source electrode Ps45 connects VDD; The grid Pg46 of the 46 PMOS pipe connects the drain electrode Pd44 of the 44 PMOS pipe, and drain electrode Pd46 connects the drain electrode Nd45 of the 45 NMOS pipe; The grid Pg47 of the 47 PMOS pipe connects SN, and drain electrode Pd47 connects the source electrode Ps48 of the 48 PMOS pipe, and source electrode Ps47 connects VDD; The grid Pg48 of the 48 PMOS pipe connects the drain electrode Pd44 of the 44 PMOS pipe, and drain electrode Pd48 connects the drain electrode Nd47 of the 47 NMOS pipe, and source electrode Ps48 connects the drain electrode Pd47 of the 47 PMOS pipe; The grid Pg49 of the 49 PMOS pipe connects the drain electrode Pd46 of the 46 PMOS pipe, and source electrode Ps49 connects power vd D, and drain electrode Pd49 connects the drain electrode Nd49 of the 49 NMOS pipe an output SN01 as set buffer circuit; The grid Pg50 of the 50 PMOS pipe connects the drain electrode Pd48 of the 48 PMOS pipe, and source electrode Ps50 connects power vd D, and drain electrode Pd50 connects the drain electrode Nd50 of the 50 NMOS pipe another output SN02 as set buffer circuit; The grid Ng41 of the 41 NMOS pipe connects SN, and drain electrode Nd41 connects the drain electrode Pd41 of the 41 PMOS pipe, and source electrode Ns41 connects VSS; The grid Ng42 of the 42 NMOS pipe connects the drain electrode Nd41 of the 41 NMOS pipe, and drain electrode Nd42 connects the drain electrode Pd42 of the 42 PMOS pipe, and source electrode Ns42 connects VSS; The grid Ng43 of the 43 NMOS pipe connects the drain electrode Nd42 of the 42 NMOS pipe, and drain electrode Nd43 connects the drain electrode Pd43 of the 43 PMOS pipe, and source electrode Ns43 connects VSS; The grid Ng44 of the 44 NMOS pipe connects the drain electrode Nd43 of the 43 NMOS pipe, and drain electrode Nd44 connects the drain electrode Pd44 of the 44 PMOS pipe, and source electrode Ns44 connects VSS; The grid Ng45 of the 45 NMOS pipe connects the drain electrode Nd44 of the 44 NMOS pipe, and source electrode Ns45 connects the drain electrode Nd46 of the 46 NMOS pipe, and drain electrode Nd45 connects the 49 NMOS tube grid Ng49; The grid Ng46 of the 46 NMOS pipe connects SN, and drain electrode Nd46 connects the source electrode Nd45 of the 45 NMOS pipe, and source electrode Ns46 connects VSS; The grid Ng47 of the 47 NMOS pipe connects the drain electrode Nd44 of the 44 NMOS pipe, and source electrode Ns47 connects the drain electrode Nd48 of the 48 NMOS pipe, and drain electrode Nd47 connects the 50 NMOS tube grid Ng50; The grid Ng48 of the 48 NMOS pipe connects SN, and drain electrode Nd48 connects the source electrode Nd47 of the 47 NMOS pipe, and source electrode Ns48 connects VSS.The grid Ng49 of the 49 NMOS pipe connects the drain electrode Nd45 of the 45 NMOS pipe, and source electrode Ns49 connects ground VSS, and drain electrode Nd49 connects the drain electrode Pd49 of the 49 PMOS pipe and connects output SN01; The grid Ng50 of the 50 NMOS pipe connects the 47 NMOS pipe drain electrode Nd47, and drain electrode Nd50 connects the drain electrode Nd50 of the 50 PMOS pipe and connects output SN02, and source electrode Ns50 connects VSS.

As shown in Figure 7, main latch has 11 inputs and two outputs, and input is D, D1, SI, SE, SEN, SN01, SN02, c1, c2, cn1, cn2; Output is m1, m1r.Main latch is made up of 18 PMOS pipes and 18 NMOS pipes, and in main latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg9 of the 9th PMOS pipe connects SI, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS pipe, and source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects SEN, and drain electrode Pd10 connects the source electrode Ps13 of the 13 PMOS pipe, and source electrode Ps10 connects Pd9; The grid Pg11 of the 11 PMOS pipe connects SE, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects D, and drain electrode Pd12 connects Ps13, and source electrode Ps12 connects Pd11; The grid Pg8 of the 13 PMOS pipe connects c1, and drain electrode Pd13 connects the drain electrode Nd9 of the 9th NMOS pipe, and source electrode Ps13 connects Pd10; The grid Pg14 of the 14 PMOS pipe connects SI, and drain electrode Pd14 connects the source electrode Ps15 of the 15 PMOS pipe, and source electrode Ps14 connects power vd D; The grid Pg15 of the 15 PMOS pipe connects SEN, and drain electrode Pd15 connects the source electrode Ps18 of the 18 PMOS pipe, and source electrode Ps15 connects Pd14; The grid Pg16 of the 16 PMOS pipe connects SE, and drain electrode Pd16 connects the source electrode Ps17 of the 17 PMOS pipe, and source electrode Ps16 connects power vd D; The grid Pg17 of the 17 PMOS pipe connects D1, and drain electrode Pd17 connects the source electrode Ps18 of the 18 PMOS pipe, and source electrode Ps17 connects Pd16; The grid Pg18 of the 18 PMOS pipe connects c2, and drain electrode Pd18 connects the drain electrode Nd14 of the 14 NMOS pipe, and source electrode Ps18 connects Pd15; The grid Pg19 of the 19 PMOS pipe connects the drain electrode Pd13 of the 13 PMOS pipe, and drain electrode Pd19 connects the drain electrode Nd19 of the 19 NMOS pipe, and as an output m1 of main latch, source electrode Ps19 connects power vd D; The grid Pg20 of the 20 PMOS pipe connects SN01, and drain electrode Pd20 connects the drain electrode Nd19 of the 19 NMOS pipe, and connects output m1, and source electrode Ps20 connects power vd D; The grid Pg21 of the 21 PMOS pipe connects the drain electrode Pd18 of the 18 PMOS pipe, and drain electrode Pd21 connects the drain electrode Nd21 of the 21 NMOS pipe, and as an output m1r of main latch, source electrode Ps21 connects power vd D; The grid Pg22 of the 22 PMOS pipe connects SN02, and drain electrode Pd22 connects the drain electrode Nd21 of the 21 NMOS pipe, and connects output m1r, and source electrode Ps22 connects power vd D; The grid Pg23 of the 23 PMOS pipe connects Pd22, and drain electrode Pd23 connects the source electrode Ps24 of the 24 PMOS pipe, and source electrode Ps23 connects power vd D; The grid Pg24 of the 24 PMOS pipe connects cn1, and drain electrode Pd24 connects the drain electrode Nd23 of the 23 NMOS pipe, and source electrode Ps24 connects Pd23; The grid Pg25 of the 25 PMOS pipe connects Pd20, and drain electrode Pd25 connects the source electrode Ps26 of the 26 PMOS pipe, and source electrode Ps25 connects power vd D; The grid Pg26 of the 26 PMOS pipe connects cn2, and drain electrode Pd26 connects the drain electrode Nd25 of the 25 NMOS pipe and is connected with Pd18, and source electrode Ps26 connects Pd25; The grid Ng9 of the 9th NMOS pipe connects cn1, and drain electrode Nd9 connects Pd13, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe; The grid Ng10 of the tenth NMOS pipe connects SE, and drain electrode Nd10 connects Ns9, and source electrode Ns10 connects the drain electrode Nd11 of the 11 NMOS pipe; The grid Ng11 of the 11 NMOS pipe connects SI, and drain electrode Nd11 connects Ns10, source electrode Ns11 ground connection VSS; The grid Ng12 of the 12 NMOS pipe connects D, and drain electrode Nd12 connects Ns9, and source electrode Ns12 connects the drain electrode Nd13 of the 13 NMOS pipe; The grid Ng13 of the 13 NMOS pipe connects SEN, and drain electrode Nd13 connects Ns12, source electrode Ns13 ground connection VSS; The grid Ng14 of the 14 NMOS pipe connects cn2, and drain electrode Nd14 connects Pd18, and source electrode Ns14 connects the drain electrode Nd15 of the 15 NMOS pipe; The grid Ng15 of the 15 NMOS pipe connects SE, and drain electrode Nd15 connects Ns14, and source electrode Ns15 connects the drain electrode Nd16 of the 16 NMOS pipe; The grid Ng16 of the 16 NMOS pipe connects SI, and drain electrode Nd16 connects Ns15, source electrode Ns16 ground connection VSS; The grid Ng17 of the 17 NMOS pipe connects D1, and drain electrode Nd17 connects Ns14, and source electrode Ns17 connects the drain electrode Nd18 of the 18 NMOS pipe; The grid Ng18 of the 18 NMOS pipe connects SEN, and drain electrode Nd18 connects Ns17, source electrode Ns18 ground connection VSS; The grid Ng19 of the 19 NMOS pipe connects Pd18, and drain electrode Nd19 connects Pd20, and source electrode Ns19 meets the 20 NMOS pipe drain electrode Nd20; The grid Ng20 of the 20 NMOS pipe connects SN02, and drain electrode Nd20 connects Ns19, source electrode Ns20 ground connection VSS; The grid Ng21 of the 21 NMOS pipe connects Pd18, and drain electrode Nd21 connects Pd22, and source electrode Ns21 meets the drain electrode Nd22 of the 22 NMOS pipe; The grid Ng22 of the 22 NMOS pipe connects SN01, and drain electrode Nd22 connects Ns21, source electrode Ns22 ground connection VSS; The grid Ng23 of the 23 NMOS pipe connects c1, and drain electrode Nd23 connects Pd24, and source electrode Ns23 connects the drain electrode Nd24 of the 24 NMOS pipe; The grid Ng24 of the 24 NMOS pipe connects Pd20, and drain electrode Nd24 connects Ns23, source electrode Ns24 ground connection VSS; The grid Ng25 of the 25 NMOS pipe connects c2, and drain electrode Nd25 connects Pd26, and source electrode Ns25 connects the drain electrode Nd26 of the 26 NMOS pipe; The grid Ng26 of the 26 NMOS pipe connects Pd22, and drain electrode Nd26 connects Ns25, source electrode Ns26 ground connection VSS.Scan Architecture in the 9th PMOS pipe, the tenth PMOS pipe, the 11 PMOS pipe and the tenth NMOS pipe, the 11 NMOS pipe, the 13 NMOS pipe composition main latch.Set structure in the 20 PMOS pipe and the 20 NMOS pipe composition main latch.

As shown in Figure 8, have eight inputs and two outputs from latch, input is SN01, SN02, c1, c2, cn1, cn2, m1, m1r; Output is s1, s1r.Be made up of 12 PMOS pipes and 12 NMOS pipes from latch, from latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg27 of the 27 PMOS pipe connects m1r, and drain electrode Pd27 connects the source electrode Ps28 of the 28 PMOS pipe, and source electrode Ps27 connects power vd D; The grid Pg28 of the 28 PMOS pipe connects cn1, and drain electrode Pd28 connects the drain electrode Nd27 of the 27 NMOS pipe, and source electrode Ps28 connects Pd27; The grid Pg29 of the 29 PMOS pipe connects m1, and drain electrode Pd29 connects the source electrode Ps30 of the 30 PMOS pipe, and source electrode Ps29 connects power vd D; The grid Pg30 of the 30 PMOS pipe connects cn2, and drain electrode Pd30 connects the drain electrode Nd29 of the 29 NMOS pipe, and source electrode Ps30 connects Pd29; The grid Pg31 of the 31 PMOS pipe connects the drain electrode Pd28 of the 28 PMOS pipe, and drain electrode Pd31 connects the drain electrode Nd31 of the 31 NMOS pipe and as an output s1 from latch, source electrode Ps31 connects power vd D; The grid Pg32 of the 32 PMOS pipe connects SN01, and drain electrode Pd32 connects the drain electrode Nd31 of the 31 NMOS pipe, and connects output s1, and source electrode Ps32 connects power vd D; The grid Pg33 of the 33 PMOS pipe connects the drain electrode Pd30 of the 30 PMOS pipe, and drain electrode Pd33 connects the drain electrode Nd33 of the 33 NMOS pipe, and as an output s1r from latch, source electrode Ps33 connects power vd D; The grid Pg34 of the 34 PMOS pipe connects SN02, and drain electrode Pd34 connects the drain electrode Nd33 of the 33 NMOS pipe, and connects output s1r, and source electrode Ps34 connects power vd D; The grid Pg35 of the 35 PMOS pipe connects Pd34, and drain electrode Pd35 connects the source electrode Ps36 of the 36 PMOS pipe, and source electrode Ps35 connects power vd D; The grid Pg36 of the 36 PMOS pipe connects cn1, and drain electrode Pd36 connects the drain electrode Nd35 of the 35 NMOS pipe, and source electrode Ps36 connects Pd35; The grid Pg37 of the 37 PMOS pipe connects Pd32, and drain electrode Pd37 connects the source electrode Ps38 of the 38 PMOS pipe, and source electrode Ps37 connects power vd D; The grid Pg38 of the 38 PMOS pipe connects cn2, and drain electrode Pd38 connects the drain electrode Nd37 of the 37 NMOS pipe, and source electrode Ps38 connects Pd37; The grid Ng27 of the 27 NMOS pipe connects c, and drain electrode Nd27 connects Pd28, and source electrode Ns27 connects the drain electrode Nd28 of the 28 NMOS pipe; The grid Ng28 of the 28 NMOS pipe connects m1, and drain electrode Nd28 connects Ns27, source electrode Ns28 ground connection VSS; The grid Ng29 of the 29 NMOS pipe connects c2, and drain electrode Nd29 connects Pd30, and source electrode Ns29 connects the drain electrode Nd30 of the 30 NMOS pipe; The grid Ng30 of the 30 NMOS pipe connects m1r, and drain electrode Nd30 connects Ns29, source electrode Ns30 ground connection VSS; The grid Ng31 of the 31 NMOS pipe connects Pd30, and drain electrode Nd31 connects Pd32, and source electrode Ns31 connects the drain electrode Nd32 of the 32 NMOS pipe; The grid Ng32 of the 32 NMOS pipe connects SN02, and drain electrode Nd32 connects Ns31, source electrode Ns32 ground connection VSS; The grid Ng33 of the 33 NMOS pipe connects Pd28, and drain electrode Nd33 connects Pd34, and source electrode Ns33 meets the drain electrode Nd34 of the 34 NMOS pipe; The grid Ng34 of the 34 NMOS pipe connects SN01, and drain electrode Nd34 connects Ns33, source electrode Ns34 ground connection VSS; The grid Ng35 of the 35 NMOS pipe connects c1, and drain electrode Nd35 connects Pd36, and source electrode Ns35 connects the drain electrode Nd36 of the 36 NMOS pipe; The grid Ng36 of the 36 NMOS pipe connects Pd32, and drain electrode Nd36 connects Ns35, source electrode Ns36 ground connection VSS; The grid Ng37 of the 37 NMOS pipe connects c2, and drain electrode Nd37 connects Pd38, and source electrode Ns37 connects the drain electrode Nd38 of the 38 NMOS pipe; The grid Ng38 of the 38 NMOS pipe connects Pd34, and drain electrode Nd38 connects Ns37, source electrode Ns38 ground connection VSS.The 32 PMOS pipe and the set structure of the 32 NMOS pipe composition from latch.

As shown in Figure 9, the first output buffer has two inputs and an output, and input connects s1 and s1r, and output is Q.Output buffer is made up of two PMOS pipes and two NMOS pipes.The substrate of all PMOS pipes of output buffer connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg51 of the 51 PMOS pipe meets input s1r, and drain electrode Pd51 connects the drain electrode Nd51 of the 51 NMOS pipe, and source electrode Ps51 meets power vd D; The grid Pg52 of the 52 PMOS pipe meets Pd51, and drain electrode Pd52 connects the drain electrode Nd52 of the 52 NMOS pipe, and as the output Q of output buffer; Source electrode Ps52 meets power vd D; The grid Ng51 of the 51 NMOS pipe meets input s1, and drain electrode Nd51 connects Pd51, source electrode Ns51 ground connection VSS; The grid Ng52 of the 52 NMOS pipe meets Nd51, and drain electrode Nd52 connects Pd52, source electrode Ns52 ground connection VSS.

As shown in figure 10, the second output buffer has two inputs and an output, and input connects s1 and s1r, and output is QN.Output buffer is made up of a PMOS pipe and a NMOS pipe.The substrate of PMOS pipe connects power vd D, the substrate ground connection VSS of NMOS pipe.The grid Pg40 of the 40 PMOS pipe meets input s1, and drain electrode Pd40 connects the drain electrode Nd40 of the 40 NMOS pipe, and as the output QN of buffer circuit, source electrode Ps40 meets power vd D; The grid Ng40 of the 40 NMOS pipe meets input s1r, and drain electrode Nd40 connects Pd40, and connects output QN, source electrode Ns40 ground connection VSS;

The H-13 of Beijing Institute of Atomic Energy tandem accelerator can produce LET value and be respectively 2.88MeVcm ²/ mg, 8.62MeVcm ²/ mg, 12.6MeVcm ²/ mg and 17.0MeVcm ²four kinds of ground heavy ion irradiation test environments of/mg.By setable Scan Architecture the d type flip flop unguyed tradition in normal operating conditions, the setable Scan Architecture d type flip flop that tradition duplication redundancy is reinforced, the setable Scan Architecture d type flip flop that time sampling is reinforced, application number is that the primary particle inversion resistant setable Scan Architecture d type flip flop that proposes of 201110323794.1 Chinese patent and the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state are connected respectively the output of 1000 grades of identical reverser chains the clock frequency work with 40MHz, the input of 1000 grades of reverser chains connects low level.The LET value that foregoing circuit is placed in to the generation of the H-13 of Beijing Institute of Atomic Energy tandem accelerator is respectively 2.88MeVcm ²/ mg, 8.62MeVcm ²/ mg, 12.6MeVcm ²/ mg and 21.3MeVcm ²in the ground heavy ion irradiation test environment of/mg, add up the make a mistake number of times of output of each setable Scan Architecture d type flip flop in the heavy ion irradiation process of each LET.The total fluence of heavy ion irradiation of every kind of LET is 10 ⁷ion/cm ².Table 1 is that the ground heavy particle irradiation that uses the H-13 of Beijing Institute of Atomic Energy tandem accelerator to carry out is tested the unguyed setable Scan Architecture d type flip flop of tradition obtaining, the setable Scan Architecture d type flip flop that tradition duplication redundancy is reinforced, the setable Scan Architecture d type flip flop that time sampling is reinforced, application number is that the primary particle inversion resistant setable Scan Architecture d type flip flop that proposes of 201110323794.1 Chinese patent and the setable Scan Architecture d type flip flop of anti-single particle overturn of the present invention and single-ion transient state are respectively 2.88MeVcm in LET value ²/ mg, 8.62MeVcm ²/ mg, 12.6MeVcm ²/ mg and 21.3MeVcm ²the number of times of exporting makes a mistake in the ground heavy ion irradiation process of/mg.The total fluence of heavy ion irradiation of every kind of LET is 10 ⁷ion/cm ².Can find out from the statistics of table 1, anti-single particle overturn of the present invention and single-ion transient state ability are better than the unguyed setable Scan Architecture d type flip flop of tradition, the setable Scan Architecture d type flip flop that time sampling is reinforced, the primary particle inversion resistant setable Scan Architecture d type flip flop of Chinese patent proposition and the setable Scan Architecture d type flip flop of traditional duplication redundancy reinforcing that application number is 201110323794.1, be suitable for anti-single particle overturn and single-ion transient state and reinforce the standard cell lib of integrated circuit, be applied to the fields such as Aeronautics and Astronautics.

Table 1

Claims

1. the setable Scan Architecture d type flip flop of anti-single particle overturn and single-ion transient state, comprise clock circuit, scan control buffer circuit, main latch, from latch, output buffer, the setable Scan Architecture d type flip flop that it is characterized in that anti-single particle overturn and single-ion transient state also comprises buffer circuit, set buffer circuit, and output buffer has 2; Main latch and from latch be redundancy reinforce latch; Main latch and from series connection before and after latch, and be all connected with clock circuit, set buffer circuit; Main latch is also connected with buffer circuit, scan control buffer circuit, is also connected with the first output buffer, the second output buffer from latch; There are five inputs and two outputs; Five inputs are respectively clock signal input terminal CK, data-signal input D, scan control signal input SE, scan data input terminal SI and asserts signal input SN; Output is Q and QN.

2. the setable Scan Architecture d type flip flop of anti-single particle overturn as claimed in claim 1 and single-ion transient state, it is characterized in that described clock circuit clock circuit has an input and four outputs, input is CK, and output is c1, c2, cn1, cn2; Clock circuit is made up of 12 PMOS and ten four NMOSs; The grid Pg53 of the 53 PMOS pipe connects CK, and drain electrode Pd53 connects the drain electrode Nd53 of the 53 NMOS pipe; The grid Pg54 of the 54 PMOS pipe connects the drain electrode Pd53 of the 53 PMOS pipe, and drain electrode Pd54 connects the drain electrode Nd54 of the 54 NMOS pipe, and source electrode Ps54 connects power vd D; The grid Pg55 of the 55 PMOS pipe connects the drain electrode Pd54 of the 54 PMOS pipe, and drain electrode Pd55 connects the drain electrode Nd55 of the 55 NMOS pipe, and source electrode Ps55 connects power vd D; The grid Pg56 of the 56 PMOS pipe connects the drain electrode Pd55 of the 55 PMOS pipe, and drain electrode Pd56 connects the drain electrode Nd56 of the 56 NMOS pipe, and source electrode Ps56 connects power vd D; The grid Pg57 of the 57 PMOS pipe connects CK, and drain electrode Pd57 connects the source electrode Ps58 of the 58 PMOS pipe, and source electrode Ps57 connects VDD; The grid Pg58 of the 58 PMOS pipe connects the drain electrode Pd56 of the 56 PMOS pipe, and drain electrode Pd58 connects the drain electrode Nd57 of the 57 NMOS pipe, and as an output cn1 of clock circuit, source electrode Ps58 connects Pd57; The grid Pg59 of the 59 PMOS pipe connects CK, and drain electrode Pd59 connects the source electrode Ps60 of the 60 PMOS pipe, and source electrode Ps59 connects VDD; The grid Pg60 of the 60 PMOS pipe connects the drain electrode Pd56 of the 56 PMOS pipe, and drain electrode Pd60 connects the drain electrode Nd59 of the 59 NMOS pipe an output cn2 as clock circuit, and source electrode Ps60 connects Pd59; The grid Pg61 of the 61 PMOS pipe is as an output c1 of clock circuit, and drain electrode Pd61 connects the drain electrode Pd58 of the 58 PMOS pipe, and connects output cn1, and source electrode Ps61 connects VDD; The grid Pg62 of the 62 PMOS pipe connects the grid Ng62 of the 62 NMOS pipe an output c2 as clock circuit, drain electrode Pd62 connects the drain electrode Nd62 of the 62 NMOS pipe an output cn2 as clock circuit, and source electrode Ps62 connects VDD; The grid Pg63 of the 63 PMOS pipe connects output cn1, and drain electrode Pd63 connects output c1, and source electrode Ps63 connects VDD; The grid Pg64 of the 64 PMOS pipe connects output cn2, and drain electrode Pd64 connects output c2, and source electrode Ps64 connects VDD; The grid Ng53 of the 53 NMOS pipe connects CK, and drain electrode Nd53 connects the drain electrode Pd53 of the 53 PMOS pipe; The grid Ng54 of the 54 NMOS pipe connects the drain electrode Nd53 of the 53 NMOS pipe, and drain electrode Nd54 connects the drain electrode Pd54 of the 54 PMOS pipe, and source electrode Ns54 connects VSS; The grid Ng55 of the 55 NMOS pipe connects the drain electrode Nd54 of the 54 NMOS pipe, and drain electrode Nd55 connects the drain electrode Pd55 of the 55 PMOS pipe, and source electrode Ns55 connects VSS; The grid Ng56 of the 56 NMOS pipe connects the drain electrode Nd55 of the 55 NMOS pipe, and drain electrode Nd56 connects the drain electrode Pd56 of the 56 PMOS pipe, and source electrode Ns56 connects VSS; The grid Ng57 of the 57 NMOS pipe connects the drain electrode Nd56 of the 56 NMOS pipe, and source electrode Ns57 connects the drain electrode Nd58 of the 58 NMOS pipe, and drain electrode connects cn1; The grid Ng58 of the 58 NMOS pipe connects CK, and drain electrode Nd58 connects the source electrode Nd57 of the 57 NMOS pipe, and source electrode Ns58 connects VSS; The grid Ng59 of the 59 NMOS pipe connects the drain electrode Nd56 of the 56 NMOS pipe, and source electrode Ns59 connects the drain electrode Nd60 of the 60 NMOS pipe, and drain electrode connects cn2; The grid Ng60 of the 60 NMOS pipe connects CK, and drain electrode Nd60 connects the source electrode Nd59 of the 59 NMOS pipe, and source electrode Ns60 connects VSS; The grid Ng61 of the 61 NMOS pipe connects output c1, and drain electrode Nd61 connects output cn2, and source electrode Ns61 connects the drain electrode Nd65 of the 65 NMOS pipe; The grid Ng62 of the 62 NMOS pipe connects output c2, and drain electrode Nd62 connects output cn2, and source electrode Ns62 connects the drain electrode Nd66 of the 66 NMOS pipe; The grid Ng63 of the 63 NMOS pipe connects output cn1, and drain electrode Nd63 connects output c1, and source electrode Ns63 connects VSS; The grid Ng64 of the 64 NMOS pipe connects output cn2, and drain electrode Nd64 connects output c2, and source electrode Ns64 connects VSS; The drain electrode Nd65 of the 65 NMOS pipe connects the source electrode Ns61 of the 61 NMOS pipe, and grid Ng65 connects output c1, and source electrode Ns65 connects VSS; The drain electrode Nd66 of the 66 NMOS pipe connects the source electrode Ns62 of the 62 NMOS pipe, and grid Ng66 connects output c1, and source electrode Ns66 connects VSS.

3. the setable Scan Architecture d type flip flop of anti-single particle overturn as claimed in claim 1 and single-ion transient state, is characterized in that described buffer circuit has an input and an output, and input is D, and output is D1; Buffer circuit is made up of eight PMOS pipes and eight NMOS pipes, and in buffer circuit, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg1 of the one PMOS pipe connects input D and is connected with the grid Ng1 of a NMOS pipe, and drain electrode Pd1 connects the drain electrode Ng1 of a NMOS pipe, and source electrode Ps1 connects VDD; The grid Pg2 of the 2nd PMOS pipe connects the drain electrode Pd1 of a PMOS pipe, and drain electrode Pd2 connects the drain electrode Nd2 of the 2nd NMOS pipe, and source electrode Ps2 connects VDD; The grid Pg3 of the 3rd PMOS pipe connects the drain electrode Pd2 of the 2nd PMOS pipe, and drain electrode Pd3 connects the drain electrode Nd3 of the 3rd NMOS pipe, and source electrode Ps3 connects VDD; The grid Pg4 of the 4th PMOS pipe connects the drain electrode Pd3 of the 3rd PMOS pipe, and drain electrode Pd4 connects the drain electrode Nd4 of the 4th NMOS pipe, and source electrode Ps4 connects VDD; The grid Pg5 of the 5th PMOS pipe connects the drain electrode Pd4 of the 4th PMOS pipe, and drain electrode Pd5 connects the drain electrode Nd5 of the 5th NMOS pipe, and source electrode Ps5 connects VDD; The grid Pg6 of the 6th PMOS pipe connects the drain electrode Pd5 of the 5th PMOS pipe, and drain electrode Pd6 connects the drain electrode Nd6 of the 6th NMOS pipe, and source electrode Ps6 connects VDD; The grid Pg7 of the 7th PMOS pipe connects the drain electrode Pd6 of the 6th PMOS pipe, and drain electrode Pd7 connects the drain electrode Nd7 of the 7th NMOS pipe, and source electrode Ps7 connects VDD; The grid Pg8 of the 8th PMOS pipe connects the drain electrode Pd7 of the 7th PMOS pipe, and drain electrode Pd8 connects the drain electrode Nd8 of the 8th NMOS pipe the output D1 as buffer, and source electrode Ps8 connects VDD; The grid Ng1 of the one NMOS pipe connects Pg1, and drain electrode Nd1 connects Pd1, and source electrode Ns1 connects VSS; The grid Ng2 of the 2nd NMOS pipe connects the drain electrode Nd1 of a NMOS pipe, and drain electrode Nd2 connects Pd2, and source electrode Ns2 connects VSS; The grid Ng3 of the 3rd NMOS pipe connects the drain electrode Nd2 of the 2nd NMOS pipe, and drain electrode Nd3 connects Pd3, and source electrode Ns3 connects VSS; The grid Ng4 of the 4th NMOS pipe connects the drain electrode Nd3 of the 3rd NMOS pipe, and drain electrode Nd4 connects Pd4, and source electrode Ns4 connects VSS; The grid Ng5 of the 5th NMOS pipe connects the drain electrode Nd4 of the 4th NMOS pipe, and drain electrode Nd5 connects Pd5, and source electrode Ns5 connects VSS; The grid Ng6 of the 6th NMOS pipe connects the drain electrode Nd5 of the 5th NMOS pipe, and drain electrode Nd6 connects Pd6, and source electrode Ns6 connects VSS; The grid Ng7 of the 7th NMOS pipe connects the drain electrode Nd6 of the 6th NMOS pipe, and drain electrode Nd7 connects Pd7, and source electrode Ns7 connects VSS; The grid Ng8 of the 8th NMOS pipe connects the drain electrode Nd7 of the 7th NMOS pipe, and drain electrode Nd8 connects Pd8, and source electrode Ns8 connects VSS.

4. the setable Scan Architecture d type flip flop of anti-single particle overturn as claimed in claim 1 and single-ion transient state, is characterized in that described scan control buffer circuit has an input and an output, and input is SE, and output is SEN; Scan control buffer circuit is made up of the 39 PMOS pipe and the 39 NMOS pipe; The substrate of the 39 PMOS pipe is all connected power vd D with source electrode Ps39, the equal ground connection VSS of the substrate of the 39 NMOS pipe and source electrode Ns39; The grid Pg39 of the 39 PMOS pipe connects SE, and drain electrode Pd39 connects the drain electrode Nd39 of the 39 NMOS pipe, and as the output SEN of scan control circuit; The grid Ng39 of the 39 NMOS pipe connects SE, and drain electrode Nd39 connects Pd39.

5. the setable Scan Architecture d type flip flop of anti-single particle overturn as claimed in claim 1 and single-ion transient state, is characterized in that described set buffer circuit has an input and two outputs, and input is SN, and output is SN01, SN02; Set buffer circuit is made up of ten NMOS pipes and ten PMOS pipes, and in set buffer circuit, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg41 of the 41 PMOS pipe connects SN, and drain electrode Pd41 connects the drain electrode Nd41 of the 41 NMOS pipe, and source electrode Ps41 connects power vd D; The grid Pg42 of the 42 PMOS pipe connects the drain electrode Pd41 of the 41 PMOS pipe, and drain electrode Pd42 connects the drain electrode Nd42 of the 42 NMOS pipe, and source electrode Ps42 connects power vd D; The grid Pg43 of the 43 PMOS pipe connects the drain electrode Pd42 of the 42 PMOS pipe, and drain electrode Pd43 connects the drain electrode Nd43 of the 43 NMOS pipe, and source electrode Ps43 connects power vd D; The grid Pg44 of the 44 PMOS pipe connects the drain electrode Pd43 of the 43 PMOS pipe, and drain electrode Pd44 connects the drain electrode Nd44 of the 44 NMOS pipe, and source electrode Ps44 connects power vd D; The grid Pg45 of the 45 PMOS pipe connects SN, and drain electrode Pd45 connects the source electrode Ps46 of the 46 PMOS pipe, and source electrode Ps45 connects VDD; The grid Pg46 of the 46 PMOS pipe connects the drain electrode Pd44 of the 44 PMOS pipe, and drain electrode Pd46 connects the drain electrode Nd45 of the 45 NMOS pipe; The grid Pg47 of the 47 PMOS pipe connects SN, and drain electrode Pd47 connects the source electrode Ps48 of the 48 PMOS pipe, and source electrode Ps47 connects VDD; The grid Pg48 of the 48 PMOS pipe connects the drain electrode Pd44 of the 44 PMOS pipe, and drain electrode Pd48 connects the drain electrode Nd47 of the 47 NMOS pipe, and source electrode Ps48 connects the drain electrode Pd47 of the 47 PMOS pipe; The grid Pg49 of the 49 PMOS pipe connects the drain electrode Pd46 of the 46 PMOS pipe, and source electrode Ps49 connects power vd D, and drain electrode Pd49 connects the drain electrode Nd49 of the 49 NMOS pipe an output SN01 as set buffer circuit; The grid Pg50 of the 50 PMOS pipe connects the drain electrode Pd48 of the 48 PMOS pipe, and source electrode Ps50 connects power vd D, and drain electrode Pd50 connects the drain electrode Nd50 of the 50 NMOS pipe another output SN02 as set buffer circuit; The grid Ng41 of the 41 NMOS pipe connects SN, and drain electrode Nd41 connects the drain electrode Pd41 of the 41 PMOS pipe, and source electrode Ns41 connects VSS; The grid Ng42 of the 42 NMOS pipe connects the drain electrode Nd41 of the 41 NMOS pipe, and drain electrode Nd42 connects the drain electrode Pd42 of the 42 PMOS pipe, and source electrode Ns42 connects VSS; The grid Ng43 of the 43 NMOS pipe connects the drain electrode Nd42 of the 42 NMOS pipe, and drain electrode Nd43 connects the drain electrode Pd43 of the 43 PMOS pipe, and source electrode Ns43 connects VSS; The grid Ng44 of the 44 NMOS pipe connects the drain electrode Nd43 of the 43 NMOS pipe, and drain electrode Nd44 connects the drain electrode Pd44 of the 44 PMOS pipe, and source electrode Ns44 connects VSS; The grid Ng45 of the 45 NMOS pipe connects the drain electrode Nd44 of the 44 NMOS pipe, and source electrode Ns45 connects the drain electrode Nd46 of the 46 NMOS pipe, and drain electrode Nd45 connects the 49 NMOS tube grid Ng49; The grid Ng46 of the 46 NMOS pipe connects SN, and drain electrode Nd46 connects the source electrode Nd45 of the 45 NMOS pipe, and source electrode Ns46 connects VSS; The grid Ng47 of the 47 NMOS pipe connects the drain electrode Nd44 of the 44 NMOS pipe, and source electrode Ns47 connects the drain electrode Nd48 of the 48 NMOS pipe, and drain electrode Nd47 connects the 50 NMOS tube grid Ng50; The grid Ng48 of the 48 NMOS pipe connects SN, and drain electrode Nd48 connects the source electrode Nd47 of the 47 NMOS pipe, and source electrode Ns48 connects VSS; The grid Ng49 of the 49 NMOS pipe connects the drain electrode Nd45 of the 45 NMOS pipe, and source electrode Ns49 connects ground VSS, and drain electrode Nd49 connects the drain electrode Pd49 of the 49 PMOS pipe and connects output SN01; The grid Ng50 of the 50 NMOS pipe connects the 47 NMOS pipe drain electrode Nd47, and drain electrode Nd50 connects the drain electrode Nd50 of the 50 PMOS pipe and connects output SN02, and source electrode Ns50 connects VSS.

6. the setable Scan Architecture d type flip flop of anti-single particle overturn as claimed in claim 1 and single-ion transient state, is characterized in that described main latch has 11 inputs and two outputs, and input is D, D1, SI, SE, SEN, SN01, SN02, c1, c2, cn1, cn2; Output is m1, m1r; Main latch is made up of 18 PMOS pipes and 18 NMOS pipes, and in main latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg9 of the 9th PMOS pipe connects SI, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS pipe, and source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects SEN, and drain electrode Pd10 connects the source electrode Ps13 of the 13 PMOS pipe, and source electrode Ps10 connects Pd9; The grid Pg11 of the 11 PMOS pipe connects SE, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects D, and drain electrode Pd12 connects Ps13, and source electrode Ps12 connects Pd11; The grid Pg8 of the 13 PMOS pipe connects c1, and drain electrode Pd13 connects the drain electrode Nd9 of the 9th NMOS pipe, and source electrode Ps13 connects Pd10; The grid Pg14 of the 14 PMOS pipe connects SI, and drain electrode Pd14 connects the source electrode Ps15 of the 15 PMOS pipe, and source electrode Ps14 connects power vd D; The grid Pg15 of the 15 PMOS pipe connects SEN, and drain electrode Pd15 connects the source electrode Ps18 of the 18 PMOS pipe, and source electrode Ps15 connects Pd14; The grid Pg16 of the 16 PMOS pipe connects SE, and drain electrode Pd16 connects the source electrode Ps17 of the 17 PMOS pipe, and source electrode Ps16 connects power vd D; The grid Pg17 of the 17 PMOS pipe connects D1, and drain electrode Pd17 connects the source electrode Ps18 of the 18 PMOS pipe, and source electrode Ps17 connects Pd16; The grid Pg18 of the 18 PMOS pipe connects c2, and drain electrode Pd18 connects the drain electrode Nd14 of the 14 NMOS pipe, and source electrode Ps18 connects Pd15; The grid Pg19 of the 19 PMOS pipe connects the drain electrode Pd13 of the 13 PMOS pipe, and drain electrode Pd19 connects the drain electrode Nd19 of the 19 NMOS pipe, and as an output m1 of main latch, source electrode Ps19 connects power vd D; The grid Pg20 of the 20 PMOS pipe connects SN01, and drain electrode Pd20 connects the drain electrode Nd19 of the 19 NMOS pipe, and connects output m1, and source electrode Ps20 connects power vd D; The grid Pg21 of the 21 PMOS pipe connects the drain electrode Pd18 of the 18 PMOS pipe, and drain electrode Pd21 connects the drain electrode Nd21 of the 21 NMOS pipe, and as an output m1r of main latch, source electrode Ps21 connects power vd D; The grid Pg22 of the 22 PMOS pipe connects SN02, and drain electrode Pd22 connects the drain electrode Nd21 of the 21 NMOS pipe, and connects output m1r, and source electrode Ps22 connects power vd D; The grid Pg23 of the 23 PMOS pipe connects Pd22, and drain electrode Pd23 connects the source electrode Ps24 of the 24 PMOS pipe, and source electrode Ps23 connects power vd D; The grid Pg24 of the 24 PMOS pipe connects cn1, and drain electrode Pd24 connects the drain electrode Nd23 of the 23 NMOS pipe, and source electrode Ps24 connects Pd23; The grid Pg25 of the 25 PMOS pipe connects Pd20, and drain electrode Pd25 connects the source electrode Ps26 of the 26 PMOS pipe, and source electrode Ps25 connects power vd D; The grid Pg26 of the 26 PMOS pipe connects cn2, and drain electrode Pd26 connects the drain electrode Nd25 of the 25 NMOS pipe and is connected with Pd18, and source electrode Ps26 connects Pd25; The grid Ng9 of the 9th NMOS pipe connects cn1, and drain electrode Nd9 connects Pd13, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe; The grid Ng10 of the tenth NMOS pipe connects SE, and drain electrode Nd10 connects Ns9, and source electrode Ns10 connects the drain electrode Nd11 of the 11 NMOS pipe; The grid Ng11 of the 11 NMOS pipe connects SI, and drain electrode Nd11 connects Ns10, source electrode Ns11 ground connection VSS; The grid Ng12 of the 12 NMOS pipe connects D, and drain electrode Nd12 connects Ns9, and source electrode Ns12 connects the drain electrode Nd13 of the 13 NMOS pipe; The grid Ng13 of the 13 NMOS pipe connects SEN, and drain electrode Nd13 connects Ns12, source electrode Ns13 ground connection VSS; The grid Ng14 of the 14 NMOS pipe connects cn2, and drain electrode Nd14 connects Pd18, and source electrode Ns14 connects the drain electrode Nd15 of the 15 NMOS pipe; The grid Ng15 of the 15 NMOS pipe connects SE, and drain electrode Nd15 connects Ns14, and source electrode Ns15 connects the drain electrode Nd16 of the 16 NMOS pipe; The grid Ng16 of the 16 NMOS pipe connects SI, and drain electrode Nd16 connects Ns15, source electrode Ns16 ground connection VSS; The grid Ng17 of the 17 NMOS pipe connects D1, and drain electrode Nd17 connects Ns14, and source electrode Ns17 connects the drain electrode Nd18 of the 18 NMOS pipe; The grid Ng18 of the 18 NMOS pipe connects SEN, and drain electrode Nd18 connects Ns17, source electrode Ns18 ground connection VSS; The grid Ng19 of the 19 NMOS pipe connects Pd18, and drain electrode Nd19 connects Pd20, and source electrode Ns19 meets the 20 NMOS pipe drain electrode Nd20; The grid Ng20 of the 20 NMOS pipe connects SN02, and drain electrode Nd20 connects Ns19, source electrode Ns20 ground connection VSS; The grid Ng21 of the 21 NMOS pipe connects Pd18, and drain electrode Nd21 connects Pd22, and source electrode Ns21 meets the drain electrode Nd22 of the 22 NMOS pipe; The grid Ng22 of the 22 NMOS pipe connects SN01, and drain electrode Nd22 connects Ns21, source electrode Ns22 ground connection VSS; The grid Ng23 of the 23 NMOS pipe connects c1, and drain electrode Nd23 connects Pd24, and source electrode Ns23 connects the drain electrode Nd24 of the 24 NMOS pipe; The grid Ng24 of the 24 NMOS pipe connects Pd20, and drain electrode Nd24 connects Ns23, source electrode Ns24 ground connection VSS; The grid Ng25 of the 25 NMOS pipe connects c2, and drain electrode Nd25 connects Pd26, and source electrode Ns25 connects the drain electrode Nd26 of the 26 NMOS pipe; The grid Ng26 of the 26 NMOS pipe connects Pd22, and drain electrode Nd26 connects Ns25, source electrode Ns26 ground connection VSS; Scan Architecture in the 9th PMOS pipe, the tenth PMOS pipe, the 11 PMOS pipe and the tenth NMOS pipe, the 11 NMOS pipe, the 13 NMOS pipe composition main latch; Set structure in the 20 PMOS pipe and the 20 NMOS pipe composition main latch.

7. the setable Scan Architecture d type flip flop of anti-single particle overturn as claimed in claim 1 and single-ion transient state, has eight inputs and two outputs from latch described in it is characterized in that, input is SN01, SN02, c1, c2, cn1, cn2, m1, m1r; Output is s1, s1r; Be made up of 12 PMOS pipes and 12 NMOS pipes from latch, from latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg27 of the 27 PMOS pipe connects m1r, and drain electrode Pd27 connects the source electrode Ps28 of the 28 PMOS pipe, and source electrode Ps27 connects power vd D; The grid Pg28 of the 28 PMOS pipe connects cn1, and drain electrode Pd28 connects the drain electrode Nd27 of the 27 NMOS pipe, and source electrode Ps28 connects Pd27; The grid Pg29 of the 29 PMOS pipe connects m1, and drain electrode Pd29 connects the source electrode Ps30 of the 30 PMOS pipe, and source electrode Ps29 connects power vd D; The grid Pg30 of the 30 PMOS pipe connects cn2, and drain electrode Pd30 connects the drain electrode Nd29 of the 29 NMOS pipe, and source electrode Ps30 connects Pd29; The grid Pg31 of the 31 PMOS pipe connects the drain electrode Pd28 of the 28 PMOS pipe, and drain electrode Pd31 connects the drain electrode Nd31 of the 31 NMOS pipe and as an output s1 from latch, source electrode Ps31 connects power vd D; The grid Pg32 of the 32 PMOS pipe connects SN01, and drain electrode Pd32 connects the drain electrode Nd31 of the 31 NMOS pipe, and connects output s1, and source electrode Ps32 connects power vd D; The grid Pg33 of the 33 PMOS pipe connects the drain electrode Pd30 of the 30 PMOS pipe, and drain electrode Pd33 connects the drain electrode Nd33 of the 33 NMOS pipe, and as an output s1r from latch, source electrode Ps33 connects power vd D; The grid Pg34 of the 34 PMOS pipe connects SN02, and drain electrode Pd34 connects the drain electrode Nd33 of the 33 NMOS pipe, and connects output s1r, and source electrode Ps34 connects power vd D; The grid Pg35 of the 35 PMOS pipe connects Pd34, and drain electrode Pd35 connects the source electrode Ps36 of the 36 PMOS pipe, and source electrode Ps35 connects power vd D; The grid Pg36 of the 36 PMOS pipe connects cn1, and drain electrode Pd36 connects the drain electrode Nd35 of the 35 NMOS pipe, and source electrode Ps36 connects Pd35; The grid Pg37 of the 37 PMOS pipe connects Pd32, and drain electrode Pd37 connects the source electrode Ps38 of the 38 PMOS pipe, and source electrode Ps37 connects power vd D; The grid Pg38 of the 38 PMOS pipe connects cn2, and drain electrode Pd38 connects the drain electrode Nd37 of the 37 NMOS pipe, and source electrode Ps38 connects Pd37; The grid Ng27 of the 27 NMOS pipe connects c, and drain electrode Nd27 connects Pd28, and source electrode Ns27 connects the drain electrode Nd28 of the 28 NMOS pipe; The grid Ng28 of the 28 NMOS pipe connects m1, and drain electrode Nd28 connects Ns27, source electrode Ns28 ground connection VSS; The grid Ng29 of the 29 NMOS pipe connects c2, and drain electrode Nd29 connects Pd30, and source electrode Ns29 connects the drain electrode Nd30 of the 30 NMOS pipe; The grid Ng30 of the 30 NMOS pipe connects m1r, and drain electrode Nd30 connects Ns29, source electrode Ns30 ground connection VSS; The grid Ng31 of the 31 NMOS pipe connects Pd30, and drain electrode Nd31 connects Pd32, and source electrode Ns31 connects the drain electrode Nd32 of the 32 NMOS pipe; The grid Ng32 of the 32 NMOS pipe connects SN02, and drain electrode Nd32 connects Ns31, source electrode Ns32 ground connection VSS; The grid Ng33 of the 33 NMOS pipe connects Pd28, and drain electrode Nd33 connects Pd34, and source electrode Ns33 meets the drain electrode Nd34 of the 34 NMOS pipe; The grid Ng34 of the 34 NMOS pipe connects SN01, and drain electrode Nd34 connects Ns33, source electrode Ns34 ground connection VSS; The grid Ng35 of the 35 NMOS pipe connects c1, and drain electrode Nd35 connects Pd36, and source electrode Ns35 connects the drain electrode Nd36 of the 36 NMOS pipe; The grid Ng36 of the 36 NMOS pipe connects Pd32, and drain electrode Nd36 connects Ns35, source electrode Ns36 ground connection VSS; The grid Ng37 of the 37 NMOS pipe connects c2, and drain electrode Nd37 connects Pd38, and source electrode Ns37 connects the drain electrode Nd38 of the 38 NMOS pipe; The grid Ng38 of the 38 NMOS pipe connects Pd34, and drain electrode Nd38 connects Ns37, source electrode Ns38 ground connection VSS; The 32 PMOS pipe and the set structure of the 32 NMOS pipe composition from latch.

8. the setable Scan Architecture d type flip flop of anti-single particle overturn as claimed in claim 1 and single-ion transient state, is characterized in that described the first output buffer has two inputs and an output, and input connects s1 and s1r, and output is Q; Output buffer is made up of two PMOS pipes and two NMOS pipes; The substrate of all PMOS pipes of output buffer connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg51 of the 51 PMOS pipe meets input s1r, and drain electrode Pd51 connects the drain electrode Nd51 of the 51 NMOS pipe, and source electrode Ps51 meets power vd D; The grid Pg52 of the 52 PMOS pipe meets Pd51, and drain electrode Pd52 connects the drain electrode Nd52 of the 52 NMOS pipe, and as the output Q of output buffer; Source electrode Ps52 meets power vd D; The grid Ng51 of the 51 NMOS pipe meets input s1, and drain electrode Nd51 connects Pd51, source electrode Ns51 ground connection VSS; The grid Ng52 of the 52 NMOS pipe meets Nd51, and drain electrode Nd52 connects Pd52, source electrode Ns52 ground connection VSS.

9. the setable Scan Architecture d type flip flop of anti-single particle overturn as claimed in claim 1 and single-ion transient state, is characterized in that described the second output buffer has two inputs and an output, and input connects s1 and s1r, and output is QN; Output buffer is made up of a PMOS pipe and a NMOS pipe; The substrate of PMOS pipe connects power vd D, the substrate ground connection VSS of NMOS pipe; The grid Pg40 of the 40 PMOS pipe meets input s1, and drain electrode Pd40 connects the drain electrode Nd40 of the 40 NMOS pipe, and as the output QN of buffer circuit, source electrode Ps40 meets power vd D; The grid Ng40 of the 40 NMOS pipe meets input s1r, and drain electrode Nd40 connects Pd40, and connects output QN, source electrode Ns40 ground connection VSS.