CN103825583B - Anti-single particle upset can synchronous reset d type flip flop with single-ion transient state - Google Patents
Anti-single particle upset can synchronous reset d type flip flop with single-ion transient state Download PDFInfo
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- CN103825583B CN103825583B CN201310672227.6A CN201310672227A CN103825583B CN 103825583 B CN103825583 B CN 103825583B CN 201310672227 A CN201310672227 A CN 201310672227A CN 103825583 B CN103825583 B CN 103825583B
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Abstract
The invention discloses anti-single particle upset and single-ion transient state can synchronous reset d type flip flop, it is therefore an objective to solving can synchronous reset d type flip flop anti-single particle transient state and the highest problem of anti-single particle upset ability.The present invention is by clock circuit, reset circuit, main latch, form from latch, the first and second Nverter circuits, buffer circuits.Main latch and from latch be redundancy reinforce latch.Main latch and from latch tandem, and be all connected with clock circuit.Main latch is also connected with buffer circuits, reset circuit, is also connected with first, second Nverter circuit from latch.Separate main latch and the C being mutually redundant from latch2MOS circuit improves the primary particle inversion resistant ability of the present invention.Buffer circuits makes not make a mistake under long-term single event transient pulse, and duplication redundancy path further increases the ability of anti-single particle transient state.
Description
Technical field
The present invention relates to a kind of D master-slave flip-flop with synchronous reset structure, particularly to a kind of anti-single particle upset
Synchronizing of (Single Event Upset, SEU) and anti-single particle transient state (Single Event Transient, SET) is multiple
Position d type flip flop.
Background technology
There is a large amount of high energy particle (proton, electronics, heavy ion etc.) in cosmic space, the sequence circuit in integrated circuit is subject to
After these high-energy particle bombardments, its state kept is likely to occur upset, and this effect is referred to as Single event upset effecf, simple grain
LET (linear energy transfer) value of son bombardment integrated circuit is the highest, the most easily produces Single event upset effecf.In integrated circuit
Combinational circuit is by after these high-energy particle bombardments, it is possible to produce transient electrical pulses, and this effect is referred to as single-ion transient state effect,
The LET value of single-particle bombardment integrated circuit is the highest, and the transient electrical pulses persistent period of generation is the longest, and electric pulse is the easiest by sequential
Circuit gathers.The upset if the state of sequence circuit makes a mistake, or the transient electrical pulses quilt that single-ion transient state effect produces
Sequence circuit mistake gathers, and integrated circuit operation instability all can be caused even to produce fatal mistake, and this is at space flight, military neck
Territory is particularly acute.Therefore, integrated circuit is reinforced thus reduce Single event upset effecf and single-ion transient state effect is more come
The most important.
D type flip flop is to use one of most timing unit in integrated circuit, the upset of its anti-single particle and single-ion transient state
Ability the anti-single particle of whole integrated circuit is overturn and the ability of single-ion transient state plays a crucial role, d type flip flop is carried out
Corresponding reinforcing can make the anti-single particle upset of integrated circuit and single-ion transient state ability be improved.
Traditional d type flip flop is D master-slave flip-flop, typically constitutes by main latch with from level series of latches.By general
Logical latch replaces with the redundancies such as DICE (Dual Interlocked Storage Cell, dual interlocked storage cell) and adds consolidation
Structure can realize primary particle inversion resistant d type flip flop.Transform input/output port on this basis, it is possible to achieve the most anti-simple grain
Son upset and single-ion transient state.M.J.Myjak et al. is at The 47th IEEE International Midwest
Deliver on Symposium on Circuits and Systems (the 47th IEEE Circuits and Systems Midwest international conference)
" Enhanced Fault-Tolerant CMOS Memory Elements " (strengthening fault-tolerant cmos memory cell) (2004
Year, the I-453～I-456 page) on propose the DICE circuit of a kind of improvement, this circuit uses DICE circuit to carry out anti-single particle
Upset is reinforced, and bidirectional data line be divide into two write data lines and two read data lines, by the duplication redundancy of data wire,
Make to travel to the single event transient pulse of DICE circuit by a certain data wire at any time to be difficult to cause whole circuit shape
The upset of state, thus realize the reinforcing for single-ion transient state.But there is positive feedback loop in the duplication redundancy of data wire, relatively
Can produce latch information upset under the single event transient pulse of long duration, anti-single particle transient state ability is the highest.
D.G.Mavis etc. are on IEEE Reliability Physics Symposium (international Reliability Physics meeting)
" the Soft error rate mitigation techniques for modern microcircuits " that deliver (reduces existing
Technology for microcircuit soft error rate) (2002 page 216 page-225) propose time sampling d type flip flop circuit.This electricity
Road introduces delay and voting circuit in the feedback loop of latch data, thus has possessed the upset of certain anti-single particle and single-particle
Transient state ability.But voting circuit itself does not possess the ability of anti-single particle transient state, mistake can be exported under single event transient pulse
Data by mistake, anti-single particle transient state ability is the highest.
The Chinese patent of Application No. 200910046337.5 discloses a kind of anti-single particle upset and single-ion transient state arteries and veins
The d type flip flop of punching.This invention is a kind of d type flip flop being similar to that time sampling structure, including two variable connectors, two
Delay circuit, two protection gate circuits and three phase inverters, it is achieved that anti-single particle upset and the single-ion transient state of d type flip flop
Reinforce.This patent has the ability of anti-single particle transient state, but opens owing to the outfan Q of the 3rd phase inverter connects second multichannel
The input VIN0 closed, defines positive feedback loop, can produce latch letter under the single event transient pulse of longer duration
Breath upset, anti-single particle transient state ability is the highest.
Some integrated circuit needs to control the state of d type flip flop in integrated circuit, forces d type flip flop input low level.At D
Increase synchronous reset circuit and synchronous reset signal input on the original architecture basics of trigger, thus realize d type flip flop
Synchronous reset structure, and the synchronous reset function of d type flip flop is controlled by synchronous reset signal, but the most this synchronization is answered
Position d type flip flop anti-single particle upset and single-ion transient state ability are the highest, are unfavorable for the ic core in fields such as Aeronautics and Astronautics
Sheet uses.
The Chinese patent of Application No. 201110323791.8 discloses a kind of primary particle inversion resistant can touch by synchronous reset D
Send out device, as it is shown in figure 1, this invention by clock circuit, main latch, from latch, the first inverter circuit and the second phase inverter
Circuit forms, and can normally work and not produce single-particle inversion under the single-particle of higher LET value bombards.Owing to this invention exists
In clock circuit, before main latch, do not use buffer circuit, so not possessing the ability of anti-single particle transient state, and main latch
Device, being provided without duplication redundancy from latch, when the LET value of single-particle bombardment is higher, some node upset on circuit is then
Whole circuit can be caused to overturn.
Summary of the invention
The technical problem to be solved in the present invention is, for current can synchronous reset d type flip flop anti-single particle transient state and anti-
The problem that single-particle inversion ability is the highest, propose a kind of anti-single particle upset and single-ion transient state can synchronous reset d type flip flop.
Concretism of the present invention is: carries out duplication redundancy reinforcing to main latch with from latch, can turn over anti-single particle
Turn；Buffer circuit is added in clock circuit and before main latch, can be with anti-single particle transient state；Cutting off may be by from latch
The positive feedback loop that single event transient pulse causes, can not turn under the single event transient pulse of longer duration
Turn.
Anti-single particle of the present invention upset and single-ion transient state can synchronous reset d type flip flop by clock circuit, reset circuit,
Main latch, from latch, the first inverter circuit, the second inverter circuit and buffer circuits form.Main latch and from
Latch is the latch that redundancy is reinforced.Main latch and from latch tandem, and be all connected with clock circuit.Main lock
Storage is also connected with buffer circuits, reset circuit, from latch also with the first inverter circuit, the second inverter circuit phase
Even.
Anti-single particle of the present invention upset and anti-single particle transient state can have three inputs and two by synchronous reset d type flip flop
Outfan.Three inputs are clock signal input terminal CK, data signal input D and the RESET input RN respectively；Outfan
It is Q and QN.
Clock circuit has an input and four outfans, and input is CK, and outfan is c1, c2, cn1, cn2.Time
Clock circuit is made up of 12 PMOS and 14 NMOS.The grid Pg35 of the 35th PMOS connects CK, and drain electrode Pd35 is even
Meet the drain electrode Nd35 of the 35th NMOS tube；The grid Pg36 of the 36th PMOS connects the drain electrode of the 35th PMOS
Pd35, drain electrode Pd36 connect the drain electrode Nd36, source electrode Ps36 of the 36th NMOS tube and connect power vd D；37th PMOS
Grid Pg37 connect the 36th PMOS drain electrode Pd36, drain electrode Pd37 connect the 37th NMOS tube drain electrode Nd37,
Source electrode Ps37 connects power vd D；The grid Pg38 of the 38th PMOS connects the drain electrode Pd37 of the 37th PMOS, drain electrode
Pd38 connects the drain electrode Nd38, source electrode Ps38 of the 38th NMOS tube and connects power vd D；The grid Pg39 of the 39th PMOS
Connect CK, drain electrode Pd39 to connect the source electrode Ps40, source electrode Ps39 of the 40th PMOS and connect VDD；The grid of the 40th PMOS
Pg40 connects the drain electrode Pd38 of the 38th PMOS, drain electrode Pd40 and connects the drain electrode Nd39 of the 39th NMOS tube, and conduct
One outfan cn1, source electrode Ps40 of clock circuit connect Pd39；The grid Pg41 of the 41st PMOS connects CK, drain electrode
Pd41 connects the source electrode Ps42, source electrode Ps41 of the 42nd PMOS and connects VDD；The grid Pg42 of the 42nd PMOS connects
The drain electrode Pd38 of the 38th PMOS, drain electrode Pd42 connect the drain electrode Nd41 of the 41st NMOS tube；43rd PMOS
Grid Pg43 connect the 43rd NMOS tube grid Ng43 and the grid Ng47 of the 47th NMOS tube and as clock electricity
One outfan c1 on road, drain electrode Pd43 connect the drain electrode Pd40 of the 40th PMOS, and as an output of clock circuit
End cn1, source electrode Ps43 connect VDD；The grid Pg44 of the 44th PMOS connects the grid Ng44 of the 44th NMOS tube also
The drain electrode Nd44 of the 44th NMOS tube is connected and as clock circuit as an outfan c2 of clock circuit, drain electrode Pd44
An outfan cn2, source electrode Ps44 connect VDD；The grid Pg45 of the 45th PMOS connects outfan cn1, drain electrode
Pd45 connects outfan c1, source electrode Ps45 and connects VDD；The grid Pg46 of the 46th PMOS connects outfan cn2, drain electrode
Pd46 connects outfan c2, source electrode Ps46 and connects VDD；The grid Ng35 of the 35th NMOS tube connects CK, drain electrode Nd35 and connects
The drain electrode Pd35 of the 35th PMOS；The grid Ng36 of the 36th NMOS tube connects the drain electrode of the 35th NMOS tube
Nd35, drain electrode Nd36 connect the drain electrode Pd36, source electrode Ns36 of the 36th PMOS and connect VSS；The grid of the 37th NMOS tube
Pole Ng37 connects the drain electrode Nd36 of the 36th NMOS tube, drain electrode Nd37 and connects the drain electrode Pd37 of the 37th PMOS, source electrode
Ns37 connects VSS；The grid Ng38 of the 38th NMOS tube connects the drain electrode Nd37 of the 37th NMOS tube, drain electrode Nd38 and connects
The drain electrode Pd38 of the 38th PMOS, source electrode Ns38 connect VSS；The grid Ng39 of the 39th NMOS tube connects the 38th
The drain electrode Nd38 of NMOS tube, source electrode Ns39 connect the drain electrode Nd40 of the 40th NMOS tube, and drain electrode connects cn1；40th NMOS tube
Grid Ng40 connect CK, drain electrode Nd40 connect the 39th NMOS tube source electrode Nd39, source electrode Ns40 connect VSS；40th
The grid Ng41 of one NMOS tube connects the leakage of drain electrode Nd38, source electrode Ns41 connection the 42nd NMOS tube of the 38th NMOS tube
Pole Nd42, drain electrode connects cn2；The grid Ng42 of the 42nd NMOS tube connects CK, drain electrode Nd42 and connects the 41st NMOS tube
Source electrode Ns41, source electrode Ns42 connect VSS；The grid Ng43 of the 43rd NMOS tube connects outfan c1, drain electrode Nd43 and connects
Outfan cn1, source electrode Ns43 connect the drain electrode Nd47 of the 47th NMOS tube；The grid Ng44 of the 44th NMOS tube connects defeated
Going out and hold c2, drain electrode Nd44 connects outfan cn2, source electrode Ns44 and connects the drain electrode Nd48 of the 48th NMOS tube；45th
The grid Ng45 of NMOS tube connects outfan cn1, drain electrode Nd45 and connects outfan c1, source electrode Ns45 and connect VSS；46th
The grid Ng46 of NMOS tube connects outfan cn2, drain electrode Nd46 and connects outfan c2, source electrode Ns46 and connect VSS；47th
The drain electrode Nd47 of NMOS tube connects the source electrode Ns43, grid Ng47 of the 43rd NMOS tube and connects outfan c1, source electrode Ns47 even
Meet VSS；The drain electrode Nd48 of the 48th NMOS tube connects the source electrode Ns44, grid Ng48 of the 44th NMOS tube and connects outfan
C2, source electrode Ns48 connect VSS.
Reset circuit has an input and two outfans, and input is RN, and outfan is rn01, rn02.Reset electricity
It route ten PMOS and ten NMOS compositions.The grid Pg47 of the 47th PMOS connects RN, drain electrode Pd47 and connects the 40th
The drain electrode Nd49 of nine NMOS tube, source electrode Ps47 connect VDD；The grid Pg48 of the 48th PMOS connects the 47th PMOS
Drain electrode Pd47, drain electrode Pd48 connect the 50th NMOS tube drain electrode Nd50, source electrode Ps48 connect power vd D；49th
The grid Pg49 of PMOS connects the drain electrode Pd48 of the 48th PMOS, drain electrode Pd49 and connects the drain electrode of the 51st NMOS tube
Nd51, source electrode Ps49 connect power vd D；The grid Pg50 of the 50th PMOS connects the drain electrode Pd49 of the 49th PMOS,
Drain electrode Pd50 connects the drain electrode Nd52, source electrode Ps50 of the 52nd NMOS tube and connects power vd D；The grid of the 51st PMOS
Pg51 connects RN, drain electrode Pd51 and connects the source electrode Ps52, source electrode Ps51 of the 52nd PMOS and connect VDD；52nd PMOS
The grid Pg52 of pipe connects the drain electrode Pd50 of the 50th PMOS, drain electrode Pd52 and connects the drain electrode Nd53 of the 53rd NMOS tube；
The grid Pg53 of the 53rd PMOS connects RN, drain electrode Pd53 and connects the source electrode Ps54, source electrode Ps53 of the 54th PMOS
Connect VDD；The grid Pg54 of the 54th PMOS connects the drain electrode Pd50 of the 50th PMOS, drain electrode Pd54 and connects the 50th
The drain electrode Nd55 of five NMOS tube；The grid Pg55 of the 55th PMOS connects the drain electrode Nd53 of the 53rd NMOS tube, drain electrode
Pd55 connects the drain electrode Nd57 of the 57th NMOS tube and the outfan rn01, source electrode Ps55 as reset circuit connects
VDD；The grid Pg56 of the 56th PMOS connects the drain electrode Pd54 of the 54th PMOS, drain electrode Pd56 and connects the 58th
NMOS tube drain electrode Nd58 an outfan rn02 as reset circuit；The grid Ng49 of the 49th NMOS tube connects RN,
Drain electrode Nd49 connects the drain electrode Pd47, source electrode Ns49 of the 47th PMOS and connects VSS；The grid Ng50 of the 50th NMOS tube is even
Meet the drain electrode Nd49 of the 49th NMOS tube, drain electrode Nd50 to connect the drain electrode Pd48, source electrode Ns50 of the 48th PMOS and connect
VSS；The grid Ng51 of the 51st NMOS tube connects the drain electrode Nd50 of the 50th NMOS tube, drain electrode Nd51 and connects the 49th
The drain electrode Pd49 of PMOS, source electrode Ns51 connect VSS；The grid Ng52 of the 52nd NMOS tube connects the 51st NMOS tube
Drain electrode Nd51, drain electrode Nd52 connect the drain electrode Pd50, source electrode Ns52 of the 50th PMOS and connect VSS；53rd NMOS tube
Grid Ng53 connects the drain electrode Nd54 of drain electrode Nd52, source electrode Ns53 connection the 54th NMOS tube of the 52nd NMOS tube, leakage
Pole connects the drain electrode Pd52 of the 52nd PMOS；The grid Ng54 of the 54th NMOS tube connects RN, drain electrode Nd54 and connects the
The source electrode Ns53 of 53 NMOS tube, source electrode Ns54 connect VSS；The grid Ng55 of the 55th NMOS tube connects the 52nd
The drain electrode Nd52 of NMOS tube, source electrode Ns55 connect the drain electrode Nd56 of the 56th NMOS tube, and drain electrode connects the 56th PMOS
Grid Pg56；The grid Ng56 of the 56th NMOS tube connects RN, drain electrode Nd56 and connects the source electrode of the 55th NMOS tube
Ns55, source electrode Ns56 connect VSS；The grid Ng57 of the 57th NMOS tube connects the grid Pg55 of the 55th PMOS, leakage
Pole Nd57 connects the drain electrode Pd55 of the 55th PMOS and connects outfan rn01, and source electrode Ns57 connects VSS；58th
The grid Ng58 of NMOS tube connects the grid Pg56 of the 56th PMOS, drain electrode Nd58 and connects the 56th PMOS drain electrode
Pd56 also connects outfan rn02, and source electrode Ns58 connects VSS；
Buffer circuits has an input and an outfan, and input is D, and outfan is D1.Buffer circuits by
Eight PMOS and eight NMOS tube compositions, in buffer circuits, the substrate of all PMOS connects power vd D, all NMOS tube
Substrate ground VSS.The grid Pg1 of the first PMOS connects input D and the grid Ng1 with the first NMOS tube connects, and drain Pd1
Connecting the drain electrode Ng1 of the first NMOS tube, source electrode Ps1 connects VDD；The grid Pg2 of the second PMOS connects the leakage of the first PMOS
Pole Pd1, drain electrode Pd2 connect the drain electrode Nd2, source electrode Ps2 of the second NMOS tube and connect VDD；The grid Pg3 of the 3rd PMOS connects the
The drain electrode Pd2 of two PMOS, drain electrode Pd3 connect the drain electrode Nd3, source electrode Ps3 of the 3rd NMOS tube and connect VDD；4th PMOS
Grid Pg4 connects the drain electrode Pd3 of the 3rd PMOS, drain electrode Pd4 and connects the drain electrode Nd4, source electrode Ps4 of the 4th NMOS tube and connect VDD；
The grid Pg5 of the 5th PMOS connects the drain electrode Pd4 of the 4th PMOS, drain electrode Pd5 and connects the drain electrode Nd5 of the 5th NMOS tube, source
Pole Ps5 connects VDD；The grid Pg6 of the 6th PMOS connects the drain electrode Pd5 of the 5th PMOS, drain electrode Pd6 and connects the 6th NMOS tube
Drain electrode Nd6, source electrode Ps6 connect VDD；The grid Pg7 of the 7th PMOS connects the drain electrode Pd6 of the 6th PMOS, and drain electrode Pd7 is even
Meet the drain electrode Nd7 of the 7th NMOS tube, source electrode Ps7 and connect VDD；The grid Pg8 of the 8th PMOS connects the drain electrode of the 7th PMOS
Pd7, drain electrode Pd8 connects the drain electrode Nd8 of the 8th NMOS tube and the outfan D1, source electrode Ps8 as buffer connects VDD；First
The grid Ng1 of NMOS tube connects Pg1, drain electrode Nd1 and connects Pd1, source electrode Ns1 and connect VSS；The grid Ng2 of the second NMOS tube connects
The drain electrode Nd1 of the first NMOS tube, drain electrode Nd2 connect Pd2, source electrode Ns2 and connect VSS；The grid Ng3 of the 3rd NMOS tube connects second
The drain electrode Nd2 of NMOS tube, drain electrode Nd3 connect Pd3, source electrode Ns3 and connect VSS；The grid Ng4 of the 4th NMOS tube connects the 3rd NMOS
The drain electrode Nd3 of pipe, drain electrode Nd4 connect Pd4, source electrode Ns4 and connect VSS；The grid Ng5 of the 5th NMOS tube connects the 4th NMOS tube
Drain electrode Nd4, drain electrode Nd5 connect Pd5, source electrode Ns5 and connect VSS；The grid Ng6 of the 6th NMOS tube connects the drain electrode of the 5th NMOS tube
Nd5, drain electrode Nd6 connect Pd6, source electrode Ns6 and connect VSS；The grid Ng7 of the 7th NMOS tube connects the drain electrode Nd6 of the 6th NMOS tube,
Drain electrode Nd7 connects Pd7, source electrode Ns7 and connects VSS；The grid Ng8 of the 8th NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, drain electrode
Nd8 connects Pd8, source electrode Ns8 and connects VSS.
Main latch has eight inputs and two outfans, input and D, D1, c1, c2, cn1, cn2, rn01, rn02
It is connected；Outfan is m1, m1r.Main latch is made up of 14 PMOS and 14 NMOS, all PMOS in main latch
Substrate connect power vd D, the Substrate ground VSS of all NMOS tube.The grid Pg9 of the 9th PMOS connects D, and drain electrode connects the tenth
The source electrode Ps10 of PMOS, source electrode Ps9 connect VDD；The grid Pg10 of the tenth PMOS connects D1, source electrode Ps10 and connects the 9th PMOS
Drain electrode Pd9, drain electrode Pd10 connect the 11st PMOS source electrode Ps11；The grid Pg11 of the 11st PMOS connects c1, source
Pole Ps11 connects the drain electrode Pd10 of the tenth PMOS, drain electrode Pd11 and connects the 9th NMOS drain electrode Nd9；The grid of the 12nd PMOS
Pg12 connects rn01, drain electrode Pd12 and connects the source electrode Ps11, source electrode Ps12 of the 11st PMOS and connect VDD；The grid of the 13rd PMOS
Pole Pg13 connects D, source electrode Ps13 and connects VDD, the source electrode Ps14 of drain electrode Pd13 connection the 14th PMOS；14th PMOS
Grid Pg14 connects D1, source electrode Ps14 and connects the drain electrode Pd13 of the 13rd PMOS, drain electrode Pd14 connection the 15th pmos source
Ps15；The grid Pg15 of the 15th PMOS connects c2, drain electrode Pd15 and connects the drain electrode Nd13, source electrode Ps15 of the 13rd NMOS tube even
Meet the drain electrode Pd14 of the 14th PMOS；The grid Pg16 of the 16th PMOS connects rn02, drain electrode Pd16 and connects the 15th PMOS
The source electrode Ps15 of pipe, source electrode Ps16 connect VDD；17th PMOS grid Pg17 connects the drain electrode Pd11 of the 11st PMOS,
Drain electrode Pd17 connects the drain electrode Pd17 of the 17th NMOS tube and connects VDD as an outfan m1r, source electrode Ps17；18th
The grid Pg18 of PMOS connects the drain electrode Pd15 of the 15th PMOS, drain electrode Pd18 and connects the drain electrode Nd18 of the 18th NMOS tube also
VDD is connected as an outfan m1, source electrode Ps18；The grid Pg19 of the 19th PMOS connects the drain electrode of the 18th PMOS
Pd18, the most also connects outfan m1, drain electrode Pd19 and connects the source electrode Ps20, source electrode Ps19 of the 20th PMOS and connect VDD；The
The grid Pg20 of 20 PMOS connects cn1, drain electrode Pd20 and connects the drain electrode Nd19, source electrode Ps20 of the 19th NMOS tube and connect
Pd19；The grid Pg21 of the 21st PMOS connects the drain electrode Pd17 of the 17th PMOS, the most also connects outfan m1r,
Drain electrode Pd21 connects the source electrode Ps22, source electrode Ps21 of the 22nd PMOS and connects VDD；The grid Pg22 of the 22nd PMOS
Connecting cn2, drain electrode Pd22 connect the drain electrode Nd21 of the 21st NMOS tube and be connected to Pd15, source electrode Ps22 connects the 21st
PMOS drains Pd21；The grid Ng9 of the 9th NMOS tube connects cn1, source electrode Ns9 and connects the drain electrode Nd10 of the tenth NMOS tube, drain electrode
Nd9 connects the drain electrode Pd11 of the 11st PMOS；The grid Ng10 of the tenth NMOS tube connects D1, drain electrode Nd10 and connects the 9th NMOS
The source electrode Ns9 of pipe, source electrode Ns10 connect Nd11；The grid Ng11 of the 11st NMOS tube connects input D, drain electrode Nd11 and connects
Ns10, source electrode Ns11 connect Nd12；The grid Ng12 of the 12nd NMOS tube connects rn02, source electrode Ns12 and connects VSS, and drain Nd12
Connect the source electrode Ns11 of the 11st NMOS tube；The grid Ng13 of the 13rd NMOS tube connects cn2, drain electrode Nd13 and connects the 15th
The drain electrode Pd15 of PMOS, source electrode Ns13 connect Nd14；The grid Ng14 of the 14th NMOS tube connects input D1, and drain electrode Nd14 is even
Meet Ns13, source electrode Ns14 and connect Nd15；The grid Ng15 of the 15th NMOS tube connects D, drain electrode Nd15 and connects the 14th NMOS tube
Source electrode Ns14, source electrode Ns15 connect Nd16；The grid Ng16 of the 16th NMOS tube connects rn01, drain electrode Nd16 and connects Ns15,
Source electrode Ns16 connects VSS；The grid Ng17 of the 17th NMOS tube connects the drain electrode Nd13 of the 13rd NMOS tube, drain electrode Nd17 and connects
The drain electrode Pd17 of the 17th PMOS, source electrode Ns17 connect VSS；The grid Ng18 of the 18th NMOS tube connects the 11st PMOS
Drain electrode Pd11, drain electrode Nd18 connect Pd18, source electrode connect VSS；The grid Ng19 of the 19th NMOS tube connects input c1, leakage
Pole Nd19 connects the drain electrode Nd20 of drain electrode Pd20, source electrode Ns19 connection the 20th NMOS tube of the 20th PMOS；20th
The grid Ng20 of NMOS tube connects the drain electrode Nd17 of the 17th NMOS tube, is simultaneously connected with m1r, drain electrode Nd20 and connects Ns19, source electrode
Ns20 connects VSS.The grid Ng21 of the 21st NMOS tube connects c2, drain electrode Nd21 and connects the Pd22 of the 22nd pipe, source electrode
Ns21 connects Nd22；The grid Ng22 of the 22nd NMOS tube connects the drain electrode Nd18 of the 18th NMOS tube, is simultaneously connected with m1, leakage
Pole Nd22 connects Ns21, and source electrode connects VSS.
Having six inputs and four outfans, input and c1 from latch, c2, cn1, cn2, m1, m1r are connected；Defeated
Going out end is s0, s0r, s1, s1r.It is made up of ten PMOS and ten NMOS tube from latch, all PMOS from latch
Substrate connect power vd D, the Substrate ground VSS of all NMOS tube.The grid Pg23 of the 23rd PMOS connects m1r, leakage
Pole Pd23 connects the source electrode Ps24, source electrode Ps23 of the 24th PMOS and connects power vd D；The grid of the 24th PMOS
Pg24 connects cn1, and drain electrode Pd24 connects the drain electrode Nd23 of the 23rd NMOS tube also as from latch outfan s0,
Source electrode Ps24 connects Pd23；The grid Pg25 of the 25th PMOS connects m1, drain electrode Pd25 and connects the 26th PMOS
Source electrode Ps26, source electrode Ps25 connect power vd D；The grid Pg26 of the 26th PMOS connects cn2, drain electrode Pd26 and connects second
The drain electrode Nd25 of 15 NMOS tube connects Pd25 as from another outfan s0r, source electrode Ps26 of latch；27th
The grid Pg27 of PMOS connects Pd24, drain electrode Pd27 and connects the drain electrode Nd27 of the 27th NMOS tube and as from latch
Another outfan s1, source electrode Ps27 connect power vd D；The grid Pg28 of the 28th PMOS connects Pd26, and drain Pd28
The drain electrode Nd28 connecting the 28th NMOS tube connects power supply as from another outfan s1r of latch, source electrode Ps28
VDD；The grid Pg29 of the 29th PMOS connects Pd28, drain electrode Pd29 and connects the source electrode Ps30 of the 30th PMOS, source electrode
Ps29 connects power vd D；The grid Pg30 of the 30th PMOS connects c1, drain electrode Pd30 and connects the drain electrode of the 29th NMOS tube
Nd29 also connects outfan s0, and source electrode Ps30 connects Pd29；The grid Pg31 of the 31st PMOS connects Pd27, and drain Pd31
Connect the source electrode Ps32 of the 32nd PMOS, source electrode Ps31 and connect power vd D；The grid Pg32 of the 32nd PMOS connects
C2, drain electrode Pd32 connect the drain electrode Nd31 of the 31st NMOS tube and connect outfan s0r, and source electrode Ps32 connects Pd31；Second
The grid Ng23 of 13 NMOS tube connects c1, drain electrode Nd23 and connects Pd24, source electrode Ns23 and connect the drain electrode of the 24th NMOS tube
Nd24；The grid Ng24 of the 24th NMOS tube connects m1, drain electrode Nd24 and connects Ns23, source electrode Ns24 ground connection VSS；25th
The grid Ng25 of NMOS tube connects c2, drain electrode Nd25 and connects Pd26, source electrode Ns25 and connect the drain electrode Nd26 of the 26th NMOS tube；
The grid Ng26 of the 26th NMOS tube connects m1r, drain electrode Nd26 and connects Ns25, source electrode Ns26 ground connection VSS；27th NMOS
The grid Ng27 of pipe connects Pd26, drain electrode Nd27 and connects Pd27, source electrode Ns27 ground connection VSS；The grid of the 28th NMOS tube
Ng28 connects Pd24, drain electrode Nd28 and connects Pd28, source electrode Ns28 ground connection VSS；The grid Ng29 of the 29th NMOS tube connects
Cn1, drain electrode Nd29 connect Pd30, source electrode Ns29 and connect the drain electrode Nd30 of the 30th NMOS tube；The grid of the 30th NMOS tube
Ng30 connects Pd27, drain electrode Nd30 and connects Ns29, source electrode Ns30 ground connection VSS；The grid Ng31 of the 31st NMOS tube connects
Cn2, drain electrode Nd31 connect Pd32 and outfan s0r, source electrode Ns31 and connect the drain electrode Nd32 of the 32nd NMOS tube；32nd
The grid Ng32 of NMOS tube connects Pd28, drain electrode Nd32 and connects Ns31, source electrode Ns32 ground connection VSS.
First inverter circuit has two inputs and an outfan, and input connects s1 and s1r, and outfan is QN.
First inverter circuit is made up of the 33rd PMOS and the 33rd NMOS tube.The substrate of the 33rd PMOS and source electrode
Ps33 is all connected with power vd D, the substrate of the 33rd NMOS tube and source electrode Ns33 equal ground connection VSS.The grid of the 33rd PMOS
Pole Pg33 meets input s1r, and drain electrode Pd33 connects the drain electrode Nd33 of the 33rd NMOS tube and as the outfan QN of phase inverter.
The grid Ng33 of the 33rd NMOS tube meets input s1, drain electrode Nd33 and connects Pd33.
Second inverter circuit has two inputs and an outfan, and input connects s0 and s0r, and outfan is Q.The
Two inverter circuits are made up of the 34th PMOS and the 34th NMOS tube.The substrate of the 34th PMOS and source electrode
Ps34 is all connected with power vd D, the substrate of the 34th NMOS tube and source electrode Ns34 equal ground connection VSS.The grid of the 34th PMOS
Pole Pg34 meets input s0, and drain electrode Pd34 connects the drain electrode Nd34 of the 34th NMOS tube and as the outfan Q of phase inverter.The
The grid Ng34 of 34 NMOS tube meets input s0r, drain electrode Nd34 and connects Pd34.
Anti-single particle of the present invention upset and anti-single particle transient state can synchronous reset d type flip flop work process as follows:
Clock circuit receives CK, produces reverse with CK by the inverter circuit of circuit intermediate formation after buffering it
Cn1 and cn2, produced and CK c1 and c2 in the same direction by the inverter circuit of circuit end, and cn1, cn2, c1 and c2 biography
Enter to main latch with from latch.Reset circuit receives RN, by the phase inverter of circuit intermediate formation after buffering it
Circuit produces the signal reverse with RN, is produced and RN RN01 and RN02 in the same direction by the inverter circuit of circuit end, and handle
RN01 and RN02 is passed to main latch.Buffer circuits receives D, output and the D1 of D homophase after being postponed by D, at CK is
Between low period, cn1 and cn2 be high level, c1 and c2 be low level, main latch is opened, and receives D and D1, and in D and D1
May with single event transient pulse filter, if now RN is high level, d type flip flop does not carry out synchronous reset, and
After buffering D and D1, output and m1 and m1r of D homophase, be in preservation state from latch, does not receive main latch output
M1, m1r, but preserve m1, m1r that a CK trailing edge samples；If now RN is low level, d type flip flop is carried out
Synchronous reset, does not receives D but receives data signal " 0 ", and m1, the m1r simultaneously exported is low level.It is high period at CK
Between, cn1 and cn2 be low level, c1 and c2 be high level, main latch is in preservation state, preserves previous CK rising edge and adopts
D that sample arrives also exports m1 and m1r with D homophase, opens and receive output m1 and m1r of main latch from latch, to m1 with
M1r carries out buffering and export s0 and s0r anti-phase with m1 and m1r and s1 and s1r with m1 and m1r homophase.At any time
Two inverter circuits will receive output s0 and s0r from latch, buffers s0 and s0r and export anti-phase with s0 and s0r
Q.First inverter circuit will receive output s1 and s1r from latch at any time, s1 and s1r is buffered and exports with
The QN that s1 and s1r is anti-phase.
Reset circuit input signal is postponed after by the C of duplication redundancy2MOS structure filter in RN may with
Single event transient pulse, and RN01 and RN02 with RN homophase of output is sent into main latch and from latch, reset
The control of behavior.
Use the present invention can reach techniques below effect:
Anti-single particle of the present invention upset and anti-single particle transient state can the anti-single particle upset of synchronous reset d type flip flop and anti-
Single-ion transient state ability is better than that tradition is unguyed can triggering by synchronous reset D of reinforcing of synchronous reset d type flip flop, time sampling
What device and tradition duplication redundancy were reinforced can synchronous reset d type flip flop.The present invention to tradition is unguyed can synchronous reset d type flip flop
Structure is transformed, to main latch with all carried out duplication redundancy reinforcing from latch, and for main latch with from latch
C in device2MOS circuit is improved, and i.e. separates the C being mutually redundant2Pull-up PMOS in MOS circuit and pull-down NMOS pipe, carry
The high primary particle inversion resistant ability of the present invention.Add buffer circuits in clock circuit and before main latch, make the present invention
Do not make a mistake under long-term single event transient pulse；By well-designed duplication redundancy path, cut off from lock
The positive feedback loop that may be caused by single event transient pulse in storage, further increases the ability of anti-single particle transient state.This
The upset of invention anti-single particle can be suitable for anti-single particle upset and anti-single particle by synchronous reset d type flip flop with single-ion transient state
Transient state reinforces the standard cell lib of integrated circuit, is applied to the fields such as Aeronautics and Astronautics.
Accompanying drawing explanation
Fig. 1 is that the primary particle inversion resistant of Application No. 201110323791.8 can synchronous reset d type flip flop overall logic
Structural representation.
Fig. 2 is anti-single particle of the present invention upset and can synchronous reset d type flip flop overall logic structure the showing of single-ion transient state
It is intended to.
Fig. 3 be anti-single particle of the present invention upset and single-ion transient state can clock circuit structure in synchronous reset d type flip flop
Schematic diagram.
Fig. 4 be anti-single particle of the present invention upset and single-ion transient state can reset circuit structure in synchronous reset d type flip flop
Schematic diagram.
Fig. 5 be anti-single particle of the present invention upset and single-ion transient state can buffer circuits knot in synchronous reset d type flip flop
Structure schematic diagram.
Fig. 6 be anti-single particle of the present invention upset and single-ion transient state can main latch structure in synchronous reset d type flip flop
Schematic diagram.
Fig. 7 be anti-single particle of the present invention upset and single-ion transient state can be from latch structure in synchronous reset d type flip flop
Schematic diagram.
Fig. 8 be anti-single particle of the present invention upset and single-ion transient state can the second phase inverter electricity in synchronous reset d type flip flop
Line structure schematic diagram.
Fig. 9 be anti-single particle of the present invention upset and single-ion transient state can the first phase inverter electricity in synchronous reset d type flip flop
Line structure schematic diagram.
Detailed description of the invention
Fig. 2 be anti-single particle of the present invention upset and single-ion transient state can synchronous reset d type flip flop logical structure schematic diagram.
The present invention is by clock circuit (as shown in Figure 3), reset circuit (as shown in Figure 4), buffer circuits (as shown in Figure 5) main latch
(as shown in Figure 6), form from latch (as shown in Figure 7) and inverter circuit (as shown in Figure 8,9).Anti-single particle of the present invention
Upset can have three inputs and two outfans by synchronous reset d type flip flop with anti-single particle transient state.Three inputs are respectively
It is CK i.e. clock signal input terminal, D i.e. data signal input and RN i.e. reset signal input；Outfan is Q and QN.Clock
Circuit receives CK, exports c1, c2 and cn1, cn2 after CK is carried out buffered respectively.Buffer circuits receives D, is prolonged by D
Lag the output D1 with D homophase.Main latch receives D, D1 and c1, c2, cn1, cn2 and rn01, rn02, and main latch exists
C1, c2, cn1, cn2 and rn01, rn02 control under D and D1 carried out latch process after export m1, m1r.Receive from latch
M1, m1r and c1, c2 and cn1, cn2, from latch c1, c2 and cn1, cn2 control m1, m1r are carried out latch process
Rear export s0, s0r, s1, s1r respectively.First inverter circuit receives s0, s0r, carries out exporting after buffered Q to it, and second
Inverter circuit receives s1, s1r, exports QN after it is carried out buffered.
As it is shown on figure 3, clock circuit has an input and four outfans, input is CK, outfan is c1, c2,
cn1、cn2.Clock circuit is made up of 12 PMOS and 14 NMOS.The grid Pg35 of the 35th PMOS connects CK,
Drain electrode Pd35 connects the drain electrode Nd35 of the 35th NMOS tube；The grid Pg36 of the 36th PMOS connects the 35th PMOS
The drain electrode Pd35 of pipe, drain electrode Pd36 connect the drain electrode Nd36, source electrode Ps36 of the 36th NMOS tube and connect power vd D；30th
The grid Pg37 of seven PMOS connects the drain electrode Pd36 of the 36th PMOS, drain electrode Pd37 and connects the leakage of the 37th NMOS tube
Pole Nd37, source electrode Ps37 connect power vd D；The grid Pg38 of the 38th PMOS connects the drain electrode of the 37th PMOS
Pd37, drain electrode Pd38 connect the drain electrode Nd38, source electrode Ps38 of the 38th NMOS tube and connect power vd D；39th PMOS
Grid Pg39 connect CK, drain electrode Pd39 connect the 40th PMOS source electrode Ps40, source electrode Ps39 connect VDD；40th
The grid Pg40 of PMOS connects the drain electrode Pd38 of the 38th PMOS, drain electrode Pd40 and connects the drain electrode of the 39th NMOS tube
Nd39, and the outfan cn1, source electrode Ps40 as clock circuit connect Pd39；The grid Pg41 of the 41st PMOS
Connect CK, drain electrode Pd41 to connect the source electrode Ps42, source electrode Ps41 of the 42nd PMOS and connect VDD；42nd PMOS
Grid Pg42 connects the drain electrode Pd38 of the 38th PMOS, drain electrode Pd42 and connects the drain electrode Nd41 of the 41st NMOS tube；The
The grid Pg43 of 43 PMOS connects the grid Ng43 and the grid Ng47 of the 47th NMOS tube of the 43rd NMOS tube
And connect the drain electrode Pd40 of the 40th PMOS as an outfan c1 of clock circuit, drain electrode Pd43, and as clock electricity
One outfan cn1, source electrode Ps43 on road connect VDD；The grid Pg44 of the 44th PMOS connects the 44th NMOS tube
Grid Ng44 and connect the drain electrode Nd44 of the 44th NMOS tube also as an outfan c2 of clock circuit, drain electrode Pd44
An outfan cn2, source electrode Ps44 as clock circuit connect VDD；The grid Pg45 of the 45th PMOS connects output
End cn1, drain electrode Pd45 connect outfan c1, source electrode Ps45 and connect VDD；The grid Pg46 of the 46th PMOS connects outfan
Cn2, drain electrode Pd46 connect outfan c2, source electrode Ps46 and connect VDD；The grid Ng35 of the 35th NMOS tube connects CK, drain electrode
Nd35 connects the drain electrode Pd35 of the 35th PMOS；The grid Ng36 of the 36th NMOS tube connects the 35th NMOS tube
Drain electrode Nd35, drain electrode Nd36 connect the drain electrode Pd36, source electrode Ns36 of the 36th PMOS and connect VSS；37th NMOS tube
Grid Ng37 connect the 36th NMOS tube drain electrode Nd36, drain electrode Nd37 connect the 37th PMOS drain electrode Pd37,
Source electrode Ns37 connects VSS；The grid Ng38 of the 38th NMOS tube connects the drain electrode Nd37 of the 37th NMOS tube, and drain Nd38
Connect the drain electrode Pd38 of the 38th PMOS, source electrode Ns38 and connect VSS；The grid Ng39 of the 39th NMOS tube connects the 3rd
The drain electrode Nd38 of 18 NMOS tube, source electrode Ns39 connect the drain electrode Nd40 of the 40th NMOS tube, and drain electrode connects cn1；40th
The grid Ng40 of NMOS tube connects CK, drain electrode Nd40 and connects the source electrode Nd39, source electrode Ns40 of the 39th NMOS tube and connect VSS；
The grid Ng41 of the 41st NMOS tube connects the drain electrode Nd38, source electrode Ns41 of the 38th NMOS tube and connects the 42nd NMOS
The drain electrode Nd42 of pipe, drain electrode connects cn2；The grid Ng42 of the 42nd NMOS tube connects CK, drain electrode Nd42 and connects the 41st
The source electrode Ns41 of NMOS tube, source electrode Ns42 connect VSS；The grid Ng43 of the 43rd NMOS tube connects outfan c1, drain electrode
Nd43 connects outfan cn1, source electrode Ns43 and connects the drain electrode Nd47 of the 47th NMOS tube；The grid of the 44th NMOS tube
Ng44 connects outfan c2, drain electrode Nd44 and connects outfan cn2, source electrode Ns44 and connect the drain electrode Nd48 of the 48th NMOS tube；
The grid Ng45 of the 45th NMOS tube connects outfan cn1, drain electrode Nd45 and connects outfan c1, source electrode Ns45 and connect VSS；The
The grid Ng46 of 46 NMOS tube connects outfan cn2, drain electrode Nd46 and connects outfan c2, source electrode Ns46 and connect VSS；4th
The drain electrode Nd47 of 17 NMOS tube connects the source electrode Ns43, grid Ng47 of the 43rd NMOS tube and connects outfan c1, source electrode
Ns47 connects VSS；The drain electrode Nd48 of the 48th NMOS tube connects the source electrode Ns44, grid Ng48 of the 44th NMOS tube and connects
Outfan c2, source electrode Ns48 connect VSS.
As shown in Figure 4, reset circuit has an input and two outfans, and input is RN, outfan be rn01,
rn02.Reset circuit is made up of ten PMOS and ten NMOS.The grid Pg47 of the 47th PMOS connects RN, and drain Pd47
Connect the drain electrode Nd49 of the 49th NMOS tube, source electrode Ps47 and connect VDD；The grid Pg48 of the 48th PMOS connects the 4th
The drain electrode Pd47 of 17 PMOS, drain electrode Pd48 connect the drain electrode Nd50, source electrode Ps48 of the 50th NMOS tube and connect power vd D；
The grid Pg49 of the 49th PMOS connects the drain electrode Pd48 of the 48th PMOS, drain electrode Pd49 and connects the 51st NMOS
The drain electrode Nd51 of pipe, source electrode Ps49 connect power vd D；The grid Pg50 of the 50th PMOS connects the leakage of the 49th PMOS
Pole Pd49, drain electrode Pd50 connect the drain electrode Nd52, source electrode Ps50 of the 52nd NMOS tube and connect power vd D；51st PMOS
The grid Pg51 of pipe connects RN, drain electrode Pd51 and connects the source electrode Ps52, source electrode Ps51 of the 52nd PMOS and connect VDD；5th
The grid Pg52 of 12 PMOS connects the drain electrode Pd50 of the 50th PMOS, drain electrode Pd52 and connects the leakage of the 53rd NMOS tube
Pole Nd53；The grid Pg53 of the 53rd PMOS connects RN, drain electrode Pd53 and connects the source electrode Ps54 of the 54th PMOS, source
Pole Ps53 connects VDD；The grid Pg54 of the 54th PMOS connects the drain electrode Pd50 of the 50th PMOS, drain electrode Pd54 and connects
The drain electrode Nd55 of the 55th NMOS tube；The grid Pg55 of the 55th PMOS connects the drain electrode of the 53rd NMOS tube
Nd53, drain electrode Pd55 connect the drain electrode Nd57 of the 57th NMOS tube and as an outfan rn01 of reset circuit, source electrode
Ps55 connects VDD；The grid Pg56 of the 56th PMOS connects the drain electrode Pd54 of the 54th PMOS, drain electrode Pd56 and connects
58th NMOS tube drain electrode Nd58 an outfan rn02 as reset circuit；The grid Ng49 of the 49th NMOS tube
Connect RN, drain electrode Nd49 to connect the drain electrode Pd47, source electrode Ns49 of the 47th PMOS and connect VSS；The grid of the 50th NMOS tube
Pole Ng50 connects the drain electrode Nd49 of the 49th NMOS tube, drain electrode Nd50 and connects the drain electrode Pd48 of the 48th PMOS, source electrode
Ns50 connects VSS；The grid Ng51 of the 51st NMOS tube connects the drain electrode Nd50 of the 50th NMOS tube, drain electrode Nd51 and connects the
The drain electrode Pd49 of 49 PMOS, source electrode Ns51 connect VSS；The grid Ng52 of the 52nd NMOS tube connects the 51st
The drain electrode Nd51 of NMOS tube, drain electrode Nd52 connect the drain electrode Pd50, source electrode Ns52 of the 50th PMOS and connect VSS；53rd
The grid Ng53 of NMOS tube connects the drain electrode of drain electrode Nd52, source electrode Ns53 connection the 54th NMOS tube of the 52nd NMOS tube
Nd54, drain electrode connects the drain electrode Pd52 of the 52nd PMOS；The grid Ng54 of the 54th NMOS tube connects RN, and drain Nd54
Connect the source electrode Ns53 of the 53rd NMOS tube, source electrode Ns54 and connect VSS；The grid Ng55 of the 55th NMOS tube connects the 5th
The drain electrode Nd52 of 12 NMOS tube, source electrode Ns55 connect the drain electrode Nd56 of the 56th NMOS tube, and drain electrode connects the 56th
The grid Pg56 of PMOS；The grid Ng56 of the 56th NMOS tube connects RN, drain electrode Nd56 and connects the 55th NMOS tube
Source electrode Ns55, source electrode Ns56 connect VSS；The grid Ng57 of the 57th NMOS tube connects the grid of the 55th PMOS
Pg55, drain electrode Nd57 connect the drain electrode Pd55 of the 55th PMOS and connect outfan rn01, and source electrode Ns57 connects VSS；The
The grid Ng58 of 58 NMOS tube connects the grid Pg56 of the 56th PMOS, drain electrode Nd58 and connects the 56th PMOS
Drain electrode Pd56 also connects outfan rn02, and source electrode Ns58 connects VSS；
As it is shown in figure 5, buffer circuits has an input and an outfan, input is D, and outfan is D1.Slow
Rushing device circuit to be made up of eight PMOS and eight NMOS tube, in buffer circuits, the substrate of all PMOS connects power vd D,
The Substrate ground VSS of all NMOS tube.The grid Pg1 of the first PMOS connects input D and the grid Ng1 with the first NMOS tube connects
Connecing, drain electrode Pd1 connects the drain electrode Ng1, source electrode Ps1 of the first NMOS tube and connects VDD；The grid Pg2 of the second PMOS connects first
The drain electrode Pd1 of PMOS, drain electrode Pd2 connect the drain electrode Nd2, source electrode Ps2 of the second NMOS tube and connect VDD；The grid of the 3rd PMOS
Pole Pg3 connects the drain electrode Pd2 of the second PMOS, drain electrode Pd3 and connects the drain electrode Nd3, source electrode Ps3 of the 3rd NMOS tube and connect VDD；The
The grid Pg4 of four PMOS connects the drain electrode Pd3 of the 3rd PMOS, drain electrode Pd4 and connects the drain electrode Nd4 of the 4th NMOS tube, source electrode
Ps4 connects VDD；The grid Pg5 of the 5th PMOS connects the drain electrode Pd4 of the 4th PMOS, drain electrode Pd5 and connects the 5th NMOS tube
Drain electrode Nd5, source electrode Ps5 connect VDD；The grid Pg6 of the 6th PMOS connects the drain electrode Pd5 of the 5th PMOS, drain electrode Pd6 and connects
The drain electrode Nd6 of the 6th NMOS tube, source electrode Ps6 connect VDD；The grid Pg7 of the 7th PMOS connects the drain electrode of the 6th PMOS
Pd6, drain electrode Pd7 connect the drain electrode Nd7, source electrode Ps7 of the 7th NMOS tube and connect VDD；The grid Pg8 of the 8th PMOS connects the 7th
The drain electrode Pd7 of PMOS, drain electrode Pd8 connect the drain electrode Nd8 of the 8th NMOS tube and as the outfan D1, source electrode Ps8 of buffer
Connect VDD；The grid Ng1 of the first NMOS tube connects Pg1, drain electrode Nd1 and connects Pd1, source electrode Ns1 and connect VSS；Second NMOS tube
Grid Ng2 connects the drain electrode Nd1 of the first NMOS tube, drain electrode Nd2 and connects Pd2, source electrode Ns2 and connect VSS；The grid of the 3rd NMOS tube
Ng3 connects the drain electrode Nd2 of the second NMOS tube, drain electrode Nd3 and connects Pd3, source electrode Ns3 and connect VSS；The grid Ng4 of the 4th NMOS tube
Connect the drain electrode Nd3 of the 3rd NMOS tube, drain electrode Nd4 to connect Pd4, source electrode Ns4 and connect VSS；The grid Ng5 of the 5th NMOS tube connects
The drain electrode Nd4 of the 4th NMOS tube, drain electrode Nd5 connect Pd5, source electrode Ns5 and connect VSS；The grid Ng6 of the 6th NMOS tube connects the 5th
The drain electrode Nd5 of NMOS tube, drain electrode Nd6 connect Pd6, source electrode Ns6 and connect VSS；The grid Ng7 of the 7th NMOS tube connects the 6th NMOS
The drain electrode Nd6 of pipe, drain electrode Nd7 connect Pd7, source electrode Ns7 and connect VSS；The grid Ng8 of the 8th NMOS tube connects the 7th NMOS tube
Drain electrode Nd7, drain electrode Nd8 connect Pd8, source electrode Ns8 and connect VSS.
As shown in Figure 6, main latch has eight inputs and two outfans, input and D, D1, c1, c2, cn1,
Cn2, rn01, rn02 are connected；Outfan is m1, m1r.Main latch is made up of 14 PMOS and 14 NMOS, main latch
In device, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube.The grid Pg9 of the 9th PMOS connects
D, drain electrode connects the source electrode Ps10, source electrode Ps9 of the tenth PMOS and connects VDD；The grid Pg10 of the tenth PMOS connects D1, source electrode Ps10
Connect the drain electrode Pd9 of the 9th PMOS, drain electrode Pd10 and connect the source electrode Ps11 of the 11st PMOS；The grid of the 11st PMOS
Pg11 connects c1, source electrode Ps11 and connects the drain electrode Pd10 of the tenth PMOS, drain electrode Pd11 connection the 9th NMOS drain electrode Nd9；Tenth
The grid Pg12 of two PMOS connects rn01, drain electrode Pd12 and connects the source electrode Ps11, source electrode Ps12 of the 11st PMOS and connect VDD；The
The grid Pg13 of 13 PMOS connects D, source electrode Ps13 and connects VDD, the source electrode Ps14 of drain electrode Pd13 connection the 14th PMOS；The
The grid Pg14 of 14 PMOS connects D1, source electrode Ps14 and connects the drain electrode Pd13 of the 13rd PMOS, drain electrode Pd14 and connect the
15 pmos source Ps15；The grid Pg15 of the 15th PMOS connects c2, drain electrode Pd15 and connects the drain electrode of the 13rd NMOS tube
Nd13, source electrode Ps15 connect the drain electrode Pd14 of the 14th PMOS；The grid Pg16 of the 16th PMOS connects rn02, and drain Pd16
Connect the source electrode Ps15 of the 15th PMOS, source electrode Ps16 and connect VDD；17th PMOS grid Pg17 connects the 11st PMOS
The drain electrode Pd11 of pipe, drain electrode Pd17 connect the drain electrode Pd17 of the 17th NMOS tube and connect as an outfan m1r, source electrode Ps17
Meet VDD；The grid Pg18 of the 18th PMOS connects the drain electrode Pd15 of the 15th PMOS, drain electrode Pd18 and connects the 18th NMOS tube
Drain electrode Nd18 and connect VDD as an outfan m1, source electrode Ps18；The grid Pg19 of the 19th PMOS connects the 18th
The drain electrode Pd18 of PMOS, the most also connects outfan m1, drain electrode Pd19 and connects the source electrode Ps20 of the 20th PMOS, source electrode
Ps19 connects VDD；The grid Pg20 of the 20th PMOS connects cn1, drain electrode Pd20 and connects the drain electrode Nd19 of the 19th NMOS tube,
Source electrode Ps20 connects Pd19；The grid Pg21 of the 21st PMOS connects the drain electrode Pd17 of the 17th PMOS, also connects simultaneously
Meet outfan m1r, drain electrode Pd21 to connect the source electrode Ps22, source electrode Ps21 of the 22nd PMOS and connect VDD；22nd PMOS
The grid Pg22 of pipe connects cn2, drain electrode Pd22 and connects the drain electrode Nd21 of the 21st NMOS tube and be connected to Pd15, source electrode Ps22
Connect the 21st PMOS drain electrode Pd21；The grid Ng9 of the 9th NMOS tube connects cn1, source electrode Ns9 and connects the leakage of the tenth NMOS tube
Pole Nd10, drain electrode Nd9 connect the drain electrode Pd11 of the 11st PMOS；The grid Ng10 of the tenth NMOS tube connects D1, and drain Nd10
Connect the source electrode Ns9 of the 9th NMOS tube, source electrode Ns10 and connect Nd11；The grid Ng11 of the 11st NMOS tube connects input D, drain electrode
Nd11 connects Ns10, source electrode Ns11 and connects Nd12；The grid Ng12 of the 12nd NMOS tube connects rn02, source electrode Ns12 and connects VSS,
Drain electrode Nd12 connects the source electrode Ns11 of the 11st NMOS tube；The grid Ng13 of the 13rd NMOS tube connects cn2, drain electrode Nd13 and connects
The drain electrode Pd15 of the 15th PMOS, source electrode Ns13 connect Nd14；The grid Ng14 of the 14th NMOS tube connects input D1, drain electrode
Nd14 connects Ns13, source electrode Ns14 and connects Nd15；The grid Ng15 of the 15th NMOS tube connects D, drain electrode Nd15 and connects the 14th
The source electrode Ns14 of NMOS tube, source electrode Ns15 connect Nd16；The grid Ng16 of the 16th NMOS tube connects rn01, drain electrode Nd16 and connects
Ns15, source electrode Ns16 connect VSS；The grid Ng17 of the 17th NMOS tube connects the drain electrode Nd13 of the 13rd NMOS tube, drain electrode
Nd17 connects the drain electrode Pd17, source electrode Ns17 of the 17th PMOS and connects VSS；The grid Ng18 of the 18th NMOS tube connects the tenth
The drain electrode Pd11 of one PMOS, drain electrode Nd18 connect Pd18, and source electrode connects VSS；The grid Ng19 of the 19th NMOS tube connects defeated
Entering and hold c1, drain electrode Nd19 connects the drain electrode Nd20 of drain electrode Pd20, source electrode Ns19 connection the 20th NMOS tube of the 20th PMOS；
The grid Ng20 of the 20th NMOS tube connects the drain electrode Nd17 of the 17th NMOS tube, is simultaneously connected with m1r, drain electrode Nd20 and connects
Ns19, source electrode Ns20 connect VSS.The grid Ng21 of the 21st NMOS tube connects c2, drain electrode Nd21 and connects the 22nd pipe
Pd22, source electrode Ns21 connect Nd22；The grid Ng22 of the 22nd NMOS tube connects the drain electrode Nd18 of the 18th NMOS tube, simultaneously
Connecting m1, drain electrode Nd22 and connect Ns21, source electrode connects VSS.
As it is shown in fig. 7, have six inputs and four outfans from latch, input and c1, c2, cn1, cn2, m1,
M1r is connected；Outfan is s0, s0r, s1, s1r.It is made up of, from latch ten PMOS and ten NMOS tube from latch
The substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube.The grid Pg23 of the 23rd PMOS
Connect m1r, drain electrode Pd23 to connect the source electrode Ps24, source electrode Ps23 of the 24th PMOS and connect power vd D；24th PMOS
The grid Pg24 of pipe connects cn1, drain electrode Pd24 and connects the drain electrode Nd23 of the 23rd NMOS tube and as from the one of latch
Outfan s0, source electrode Ps24 connect Pd23；The grid Pg25 of the 25th PMOS connects m1, drain electrode Pd25 and connects the 26th
The source electrode Ps26 of PMOS, source electrode Ps25 connect power vd D；The grid Pg26 of the 26th PMOS connects cn2, and drain Pd26
The drain electrode Nd25 connecting the 25th NMOS tube connects Pd25 as from another outfan s0r of latch, source electrode Ps26；The
The grid Pg27 of 27 PMOS connects Pd24, drain electrode Pd27 and connects the drain electrode Nd27 of the 27th NMOS tube and as from lock
Another outfan s1, source electrode Ps27 of storage connects power vd D；The grid Pg28 of the 28th PMOS connects Pd26, leakage
Pole Pd28 connects the drain electrode Nd28 of the 28th NMOS tube and connects as from another outfan s1r of latch, source electrode Ps28
Power vd D；The grid Pg29 of the 29th PMOS connects Pd28, drain electrode Pd29 and connects the source electrode Ps30 of the 30th PMOS,
Source electrode Ps29 connects power vd D；The grid Pg30 of the 30th PMOS connects c1, drain electrode Pd30 and connects the 29th NMOS tube
Drain electrode Nd29 also connects outfan s0, and source electrode Ps30 connects Pd29；The grid Pg31 of the 31st PMOS connects Pd27, drain electrode
Pd31 connects the source electrode Ps32, source electrode Ps31 of the 32nd PMOS and connects power vd D；The grid Pg32 of the 32nd PMOS
Connecting c2, drain electrode Pd32 connect the drain electrode Nd31 of the 31st NMOS tube and connect outfan s0r, source electrode Ps32 connects Pd31；
The grid Ng23 of the 23rd NMOS tube connects c1, drain electrode Nd23 and connects Pd24, source electrode Ns23 and connect the 24th NMOS tube
Drain electrode Nd24；The grid Ng24 of the 24th NMOS tube connects m1, drain electrode Nd24 and connects Ns23, source electrode Ns24 ground connection VSS；Second
The grid Ng25 of 15 NMOS tube connects c2, drain electrode Nd25 and connects Pd26, source electrode Ns25 and connect the drain electrode of the 26th NMOS tube
Nd26；The grid Ng26 of the 26th NMOS tube connects m1r, drain electrode Nd26 and connects Ns25, source electrode Ns26 ground connection VSS；20th
The grid Ng27 of seven NMOS tube connects Pd26, drain electrode Nd27 and connects Pd27, source electrode Ns27 ground connection VSS；28th NMOS tube
Grid Ng28 connects Pd24, drain electrode Nd28 and connects Pd28, source electrode Ns28 ground connection VSS；The grid Ng29 of the 29th NMOS tube is even
Meet cn1, drain electrode Nd29 to connect Pd30, source electrode Ns29 and connect the drain electrode Nd30 of the 30th NMOS tube；The grid of the 30th NMOS tube
Ng30 connects Pd27, drain electrode Nd30 and connects Ns29, source electrode Ns30 ground connection VSS；The grid Ng31 of the 31st NMOS tube connects
Cn2, drain electrode Nd31 connect Pd32 and outfan s0r, source electrode Ns31 and connect the drain electrode Nd32 of the 32nd NMOS tube；32nd
The grid Ng32 of NMOS tube connects Pd28, drain electrode Nd32 and connects Ns31, source electrode Ns32 ground connection VSS.
As shown in Figure 8, the second inverter circuit has two inputs and an outfan, and input connects s0 and s0r, defeated
Going out end is Q.Inverter circuit is made up of the 34th PMOS and the 34th NMOS tube.The substrate of the 34th PMOS and
Source electrode Ps34 is all connected with power vd D, the substrate of the 34th NMOS tube and source electrode Ns34 equal ground connection VSS.34th PMOS
Grid Pg34 meet input s0, drain electrode Pd34 connects the drain electrode Nd34 of the 34th NMOS tube the outfan as phase inverter
Q.The grid Ng34 of the 34th NMOS tube meets input s0r, drain electrode Nd34 and connects Pd34.
As it is shown in figure 9, the first inverter circuit has two inputs and an outfan, input connects s1 and s1r, defeated
Going out end is QN.Inverter circuit is made up of the 33rd PMOS and the 33rd NMOS tube.The substrate of the 33rd PMOS
It is all connected with power vd D, the substrate of the 33rd NMOS tube and source electrode Ns33 equal ground connection VSS with source electrode Ps33.33rd PMOS
The grid Pg33 of pipe meets input s1r, drain electrode Pd33 and connects the drain electrode Nd33 of the 33rd NMOS tube defeated as phase inverter
Go out to hold QN.The grid Ng33 of the 33rd NMOS tube meets input s1, drain electrode Nd33 and connects Pd33..
Beijing Institute of Atomic Energy's H-13 tandem accelerator can produce LET value and be respectively 2.88MeV cm2/mg、
8.62MeV·cm2/mg、12.6MeV·cm2/ mg and 17.0MeV cm2Four kinds of ground heavy ion irradiation test environments of/mg.
By unguyed for the tradition being in normal operating conditions can synchronizing of reinforcing of synchronous reset d type flip flop, tradition duplication redundancy multiple
What position d type flip flop, time sampling were reinforced can synchronous reset d type flip flop, the Chinese patent of Application No. 201110323795.6 carry
Go out primary particle inversion resistant can synchronous reset d type flip flop and anti-single particle of the present invention upset and single-ion transient state synchronize multiple
Position d type flip flop connects the outfan of identical 1000 grade chain of inverters respectively and works with the clock frequency of 40MHz, and 1000 grades anti-
The input of phase device chain connects low level.Foregoing circuit is placed in what Beijing Institute of Atomic Energy's H-13 tandem accelerator produced
LET value is respectively 2.88MeV cm2/mg、8.62MeV·cm2/mg、12.6MeV·cm2/ mg and 21.3MeV cm2/ mg's
In the heavy ion irradiation test environment of ground, during adding up the heavy ion irradiation of each LET, respectively mistake can occur synchronous reset d type flip flop
The number of times of output by mistake.The total fluence of heavy ion irradiation of every kind of LET is 107ion/cm2.Table 1 is for using Beijing Institute of Atomic Energy H-
What tradition that ground heavy particle irradiation test that 13 tandem accelerators are carried out obtains was unguyed can synchronous reset d type flip flop, tradition
Duplication redundancy reinforce can synchronous reset d type flip flop, time sampling reinforce can synchronous reset d type flip flop, Application No.
The primary particle inversion resistant of Chinese patent proposition of 201110323795.6 can synchronous reset d type flip flop and anti-single particle of the present invention
Overturn can be respectively 2.88MeV cm in LET value by synchronous reset d type flip flop2/mg、8.62MeV·cm2/mg、12.6MeV·
cm2/ mg and 21.3MeV cm2Make a mistake during the ground heavy ion irradiation of/mg the number of times exported.The weight of every kind of LET from
The total fluence of sub-irradiation is 107ion/cm2.From the statistics of table 1 it can be seen that the anti-single particle of the present invention overturns and single-ion transient state
Ability be better than tradition unguyed can synchronous reset d type flip flop, time sampling reinforce can synchronous reset d type flip flop, application number
Be 201110323795.6 Chinese patent propose primary particle inversion resistant can synchronous reset d type flip flop and tradition duplication redundancy
Reinforce can synchronous reset d type flip flop, be suitable for anti-single particle upset and single-ion transient state reinforce integrated circuit standard list
Unit storehouse, is applied to the fields such as Aeronautics and Astronautics.
Table 1
Claims (1)
1. anti-single particle upset and single-ion transient state can synchronous reset d type flip flop, including clock circuit, main latch, from lock
Storage, the first inverter circuit, the second inverter circuit, it is characterised in that anti-single particle upset synchronizes with single-ion transient state
Reset d type flip flop also includes buffer circuits, reset circuit；Main latch and from latch be redundancy reinforce latch；
Main latch and from latch tandem, and be all connected with clock circuit；Main latch also with buffer circuits, reset circuit
It is connected, is also connected with the first inverter circuit, the second inverter circuit from latch；There are three inputs and two outfans；
Three inputs are clock signal input terminal CK, data signal input D and the RESET input RN respectively；Outfan is Q and QN；
Described clock circuit has an input and four outfans, and input is CK, and outfan is c1, c2, cn1, cn2；Time
Clock circuit is made up of 12 PMOS and 14 NMOS；The grid Pg35 of the 35th PMOS connects CK, and drain electrode Pd35 is even
Meet the drain electrode Nd35 of the 35th NMOS tube；The grid Pg36 of the 36th PMOS connects the drain electrode of the 35th PMOS
Pd35, drain electrode Pd36 connect the drain electrode Nd36, source electrode Ps36 of the 36th NMOS tube and connect power vd D；37th PMOS
Grid Pg37 connect the 36th PMOS drain electrode Pd36, drain electrode Pd37 connect the 37th NMOS tube drain electrode Nd37,
Source electrode Ps37 connects power vd D；The grid Pg38 of the 38th PMOS connects the drain electrode Pd37 of the 37th PMOS, drain electrode
Pd38 connects the drain electrode Nd38, source electrode Ps38 of the 38th NMOS tube and connects power vd D；The grid Pg39 of the 39th PMOS
Connect CK, drain electrode Pd39 to connect the source electrode Ps40, source electrode Ps39 of the 40th PMOS and connect VDD；The grid of the 40th PMOS
Pg40 connects the drain electrode Pd38 of the 38th PMOS, drain electrode Pd40 and connects the drain electrode Nd39 of the 39th NMOS tube, and conduct
One outfan cn1, source electrode Ps40 of clock circuit connect Pd39；The grid Pg41 of the 41st PMOS connects CK, drain electrode
Pd41 connects the source electrode Ps42, source electrode Ps41 of the 42nd PMOS and connects VDD；The grid Pg42 of the 42nd PMOS connects
The drain electrode Pd38 of the 38th PMOS, drain electrode Pd42 connect the drain electrode Nd41 of the 41st NMOS tube；43rd PMOS
Grid Pg43 connect the 43rd NMOS tube grid Ng43 and the grid Ng47 of the 47th NMOS tube and as clock electricity
One outfan c1 on road, drain electrode Pd43 connect the drain electrode Pd40 of the 40th PMOS, and as an output of clock circuit
End cn1, source electrode Ps43 connect VDD；The grid Pg44 of the 44th PMOS connects the grid Ng44 of the 44th NMOS tube also
The drain electrode Nd44 of the 44th NMOS tube is connected and as clock circuit as an outfan c2 of clock circuit, drain electrode Pd44
An outfan cn2, source electrode Ps44 connect VDD；The grid Pg45 of the 45th PMOS connects outfan cn1, drain electrode
Pd45 connects outfan c1, source electrode Ps45 and connects VDD；The grid Pg46 of the 46th PMOS connects outfan cn2, drain electrode
Pd46 connects outfan c2, source electrode Ps46 and connects VDD；The grid Ng35 of the 35th NMOS tube connects CK, drain electrode Nd35 and connects
The drain electrode Pd35 of the 35th PMOS；The grid Ng36 of the 36th NMOS tube connects the drain electrode of the 35th NMOS tube
Nd35, drain electrode Nd36 connect the drain electrode Pd36, source electrode Ns36 of the 36th PMOS and connect VSS；The grid of the 37th NMOS tube
Pole Ng37 connects the drain electrode Nd36 of the 36th NMOS tube, drain electrode Nd37 and connects the drain electrode Pd37 of the 37th PMOS, source electrode
Ns37 connects VSS；The grid Ng38 of the 38th NMOS tube connects the drain electrode Nd37 of the 37th NMOS tube, drain electrode Nd38 and connects
The drain electrode Pd38 of the 38th PMOS, source electrode Ns38 connect VSS；The grid Ng39 of the 39th NMOS tube connects the 38th
The drain electrode Nd38 of NMOS tube, source electrode Ns39 connect the drain electrode Nd40 of the 40th NMOS tube, and drain electrode connects cn1；40th NMOS tube
Grid Ng40 connect CK, drain electrode Nd40 connect the 39th NMOS tube source electrode Nd39, source electrode Ns40 connect VSS；40th
The grid Ng41 of one NMOS tube connects the leakage of drain electrode Nd38, source electrode Ns41 connection the 42nd NMOS tube of the 38th NMOS tube
Pole Nd42, drain electrode connects cn2；The grid Ng42 of the 42nd NMOS tube connects CK, drain electrode Nd42 and connects the 41st NMOS tube
Source electrode Ns41, source electrode Ns42 connect VSS；The grid Ng43 of the 43rd NMOS tube connects outfan c1, drain electrode Nd43 and connects
Outfan cn1, source electrode Ns43 connect the drain electrode Nd47 of the 47th NMOS tube；The grid Ng44 of the 44th NMOS tube connects defeated
Going out and hold c2, drain electrode Nd44 connects outfan cn2, source electrode Ns44 and connects the drain electrode Nd48 of the 48th NMOS tube；45th
The grid Ng45 of NMOS tube connects outfan cn1, drain electrode Nd45 and connects outfan c1, source electrode Ns45 and connect VSS；46th
The grid Ng46 of NMOS tube connects outfan cn2, drain electrode Nd46 and connects outfan c2, source electrode Ns46 and connect VSS；47th
The drain electrode Nd47 of NMOS tube connects the source electrode Ns43, grid Ng47 of the 43rd NMOS tube and connects outfan c1, source electrode Ns47 even
Meet VSS；The drain electrode Nd48 of the 48th NMOS tube connects the source electrode Ns44, grid Ng48 of the 44th NMOS tube and connects outfan
C2, source electrode Ns48 connect VSS；
Described reset circuit has an input and two outfans, and input is RN, and outfan is rn01, rn02；Reset electricity
It route ten PMOS and ten NMOS compositions；The grid Pg47 of the 47th PMOS connects RN, drain electrode Pd47 and connects the 40th
The drain electrode Nd49 of nine NMOS tube, source electrode Ps47 connect VDD；The grid Pg48 of the 48th PMOS connects the 47th PMOS
Drain electrode Pd47, drain electrode Pd48 connect the 50th NMOS tube drain electrode Nd50, source electrode Ps48 connect power vd D；49th
The grid Pg49 of PMOS connects the drain electrode Pd48 of the 48th PMOS, drain electrode Pd49 and connects the drain electrode of the 51st NMOS tube
Nd51, source electrode Ps49 connect power vd D；The grid Pg50 of the 50th PMOS connects the drain electrode Pd49 of the 49th PMOS,
Drain electrode Pd50 connects the drain electrode Nd52, source electrode Ps50 of the 52nd NMOS tube and connects power vd D；The grid of the 51st PMOS
Pg51 connects RN, drain electrode Pd51 and connects the source electrode Ps52, source electrode Ps51 of the 52nd PMOS and connect VDD；52nd PMOS
The grid Pg52 of pipe connects the drain electrode Pd50 of the 50th PMOS, drain electrode Pd52 and connects the drain electrode Nd53 of the 53rd NMOS tube；
The grid Pg53 of the 53rd PMOS connects RN, drain electrode Pd53 and connects the source electrode Ps54, source electrode Ps53 of the 54th PMOS
Connect VDD；The grid Pg54 of the 54th PMOS connects the drain electrode Pd50 of the 50th PMOS, drain electrode Pd54 and connects the 50th
The drain electrode Nd55 of five NMOS tube；The grid Pg55 of the 55th PMOS connects the drain electrode Nd53 of the 53rd NMOS tube, drain electrode
Pd55 connects the drain electrode Nd57 of the 57th NMOS tube and the outfan rn01, source electrode Ps55 as reset circuit connects
VDD；The grid Pg56 of the 56th PMOS connects the drain electrode Pd54 of the 54th PMOS, drain electrode Pd56 and connects the 58th
NMOS tube drain electrode Nd58 an outfan rn02 as reset circuit；The grid Ng49 of the 49th NMOS tube connects RN,
Drain electrode Nd49 connects the drain electrode Pd47, source electrode Ns49 of the 47th PMOS and connects VSS；The grid Ng50 of the 50th NMOS tube is even
Meet the drain electrode Nd49 of the 49th NMOS tube, drain electrode Nd50 to connect the drain electrode Pd48, source electrode Ns50 of the 48th PMOS and connect
VSS；The grid Ng51 of the 51st NMOS tube connects the drain electrode Nd50 of the 50th NMOS tube, drain electrode Nd51 and connects the 49th
The drain electrode Pd49 of PMOS, source electrode Ns51 connect VSS；The grid Ng52 of the 52nd NMOS tube connects the 51st NMOS tube
Drain electrode Nd51, drain electrode Nd52 connect the drain electrode Pd50, source electrode Ns52 of the 50th PMOS and connect VSS；53rd NMOS tube
Grid Ng53 connects the drain electrode Nd54 of drain electrode Nd52, source electrode Ns53 connection the 54th NMOS tube of the 52nd NMOS tube, leakage
Pole connects the drain electrode Pd52 of the 52nd PMOS；The grid Ng54 of the 54th NMOS tube connects RN, drain electrode Nd54 and connects the
The source electrode Ns53 of 53 NMOS tube, source electrode Ns54 connect VSS；The grid Ng55 of the 55th NMOS tube connects the 52nd
The drain electrode Nd52 of NMOS tube, source electrode Ns55 connect the drain electrode Nd56 of the 56th NMOS tube, and drain electrode connects the 56th PMOS
Grid Pg56；The grid Ng56 of the 56th NMOS tube connects RN, drain electrode Nd56 and connects the source electrode of the 55th NMOS tube
Ns55, source electrode Ns56 connect VSS；The grid Ng57 of the 57th NMOS tube connects the grid Pg55 of the 55th PMOS, leakage
Pole Nd57 connects the drain electrode Pd55 of the 55th PMOS and connects outfan rn01, and source electrode Ns57 connects VSS；58th
The grid Ng58 of NMOS tube connects the grid Pg56 of the 56th PMOS, drain electrode Nd58 and connects the 56th PMOS drain electrode
Pd56 also connects outfan rn02, and source electrode Ns58 connects VSS；；
Described buffer circuits has an input and an outfan, and input is D, and outfan is D1；Buffer circuits by
Eight PMOS and eight NMOS tube compositions, in buffer circuits, the substrate of all PMOS connects power vd D, all NMOS tube
Substrate ground VSS；The grid Pg1 of the first PMOS connects input D and the grid Ng1 with the first NMOS tube connects, and drain Pd1
Connecting the drain electrode Ng1 of the first NMOS tube, source electrode Ps1 connects VDD；The grid Pg2 of the second PMOS connects the leakage of the first PMOS
Pole Pd1, drain electrode Pd2 connect the drain electrode Nd2, source electrode Ps2 of the second NMOS tube and connect VDD；The grid Pg3 of the 3rd PMOS connects the
The drain electrode Pd2 of two PMOS, drain electrode Pd3 connect the drain electrode Nd3, source electrode Ps3 of the 3rd NMOS tube and connect VDD；4th PMOS
Grid Pg4 connects the drain electrode Pd3 of the 3rd PMOS, drain electrode Pd4 and connects the drain electrode Nd4, source electrode Ps4 of the 4th NMOS tube and connect VDD；
The grid Pg5 of the 5th PMOS connects the drain electrode Pd4 of the 4th PMOS, drain electrode Pd5 and connects the drain electrode Nd5 of the 5th NMOS tube, source
Pole Ps5 connects VDD；The grid Pg6 of the 6th PMOS connects the drain electrode Pd5 of the 5th PMOS, drain electrode Pd6 and connects the 6th NMOS tube
Drain electrode Nd6, source electrode Ps6 connect VDD；The grid Pg7 of the 7th PMOS connects the drain electrode Pd6 of the 6th PMOS, and drain electrode Pd7 is even
Meet the drain electrode Nd7 of the 7th NMOS tube, source electrode Ps7 and connect VDD；The grid Pg8 of the 8th PMOS connects the drain electrode of the 7th PMOS
Pd7, drain electrode Pd8 connects the drain electrode Nd8 of the 8th NMOS tube and the outfan D1, source electrode Ps8 as buffer connects VDD；First
The grid Ng1 of NMOS tube connects Pg1, drain electrode Nd1 and connects Pd1, source electrode Ns1 and connect VSS；The grid Ng2 of the second NMOS tube connects
The drain electrode Nd1 of the first NMOS tube, drain electrode Nd2 connect Pd2, source electrode Ns2 and connect VSS；The grid Ng3 of the 3rd NMOS tube connects second
The drain electrode Nd2 of NMOS tube, drain electrode Nd3 connect Pd3, source electrode Ns3 and connect VSS；The grid Ng4 of the 4th NMOS tube connects the 3rd NMOS
The drain electrode Nd3 of pipe, drain electrode Nd4 connect Pd4, source electrode Ns4 and connect VSS；The grid Ng5 of the 5th NMOS tube connects the 4th NMOS tube
Drain electrode Nd4, drain electrode Nd5 connect Pd5, source electrode Ns5 and connect VSS；The grid Ng6 of the 6th NMOS tube connects the drain electrode of the 5th NMOS tube
Nd5, drain electrode Nd6 connect Pd6, source electrode Ns6 and connect VSS；The grid Ng7 of the 7th NMOS tube connects the drain electrode Nd6 of the 6th NMOS tube,
Drain electrode Nd7 connects Pd7, source electrode Ns7 and connects VSS；The grid Ng8 of the 8th NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, drain electrode
Nd8 connects Pd8, source electrode Ns8 and connects VSS；
Described main latch has eight inputs and two outfans, input and D, D1, c1, c2, cn1, cn2, rn01, rn02
It is connected；Outfan is m1, m1r；Main latch is made up of 14 PMOS and 14 NMOS, all PMOS in main latch
Substrate connect power vd D, the Substrate ground VSS of all NMOS tube；The grid Pg9 of the 9th PMOS connects D, and drain electrode connects the tenth
The source electrode Ps10 of PMOS, source electrode Ps9 connect VDD；The grid Pg10 of the tenth PMOS connects D1, source electrode Ps10 and connects the 9th PMOS
Drain electrode Pd9, drain electrode Pd10 connect the 11st PMOS source electrode Ps11；The grid Pg11 of the 11st PMOS connects c1, source
Pole Ps11 connects the drain electrode Pd10 of the tenth PMOS, drain electrode Pd11 and connects the 9th NMOS drain electrode Nd9；The grid of the 12nd PMOS
Pg12 connects rn01, drain electrode Pd12 and connects the source electrode Ps11, source electrode Ps12 of the 11st PMOS and connect VDD；The grid of the 13rd PMOS
Pole Pg13 connects D, source electrode Ps13 and connects VDD, the source electrode Ps14 of drain electrode Pd13 connection the 14th PMOS；14th PMOS
Grid Pg14 connects D1, source electrode Ps14 and connects the drain electrode Pd13 of the 13rd PMOS, drain electrode Pd14 connection the 15th pmos source
Ps15；The grid Pg15 of the 15th PMOS connects c2, drain electrode Pd15 and connects the drain electrode Nd13, source electrode Ps15 of the 13rd NMOS tube even
Meet the drain electrode Pd14 of the 14th PMOS；The grid Pg16 of the 16th PMOS connects rn02, drain electrode Pd16 and connects the 15th PMOS
The source electrode Ps15 of pipe, source electrode Ps16 connect VDD；17th PMOS grid Pg17 connects the drain electrode Pd11 of the 11st PMOS,
Drain electrode Pd17 connects the drain electrode Pd17 of the 17th NMOS tube and connects VDD as an outfan m1r, source electrode Ps17；18th
The grid Pg18 of PMOS connects the drain electrode Pd15 of the 15th PMOS, drain electrode Pd18 and connects the drain electrode Nd18 of the 18th NMOS tube also
VDD is connected as an outfan m1, source electrode Ps18；The grid Pg19 of the 19th PMOS connects the drain electrode of the 18th PMOS
Pd18, the most also connects outfan m1, drain electrode Pd19 and connects the source electrode Ps20, source electrode Ps19 of the 20th PMOS and connect VDD；The
The grid Pg20 of 20 PMOS connects cn1, drain electrode Pd20 and connects the drain electrode Nd19, source electrode Ps20 of the 19th NMOS tube and connect
Pd19；The grid Pg21 of the 21st PMOS connects the drain electrode Pd17 of the 17th PMOS, the most also connects outfan m1r,
Drain electrode Pd21 connects the source electrode Ps22, source electrode Ps21 of the 22nd PMOS and connects VDD；The grid Pg22 of the 22nd PMOS
Connecting cn2, drain electrode Pd22 connect the drain electrode Nd21 of the 21st NMOS tube and be connected to Pd15, source electrode Ps22 connects the 21st
PMOS drains Pd21；The grid Ng9 of the 9th NMOS tube connects cn1, source electrode Ns9 and connects the drain electrode Nd10 of the tenth NMOS tube, drain electrode
Nd9 connects the drain electrode Pd11 of the 11st PMOS；The grid Ng10 of the tenth NMOS tube connects D1, drain electrode Nd10 and connects the 9th NMOS
The source electrode Ns9 of pipe, source electrode Ns10 connect Nd11；The grid Ng11 of the 11st NMOS tube connects input D, drain electrode Nd11 and connects
Ns10, source electrode Ns11 connect Nd12；The grid Ng12 of the 12nd NMOS tube connects rn02, source electrode Ns12 and connects VSS, and drain Nd12
Connect the source electrode Ns11 of the 11st NMOS tube；The grid Ng13 of the 13rd NMOS tube connects cn2, drain electrode Nd13 and connects the 15th
The drain electrode Pd15 of PMOS, source electrode Ns13 connect Nd14；The grid Ng14 of the 14th NMOS tube connects input D1, and drain electrode Nd14 is even
Meet Ns13, source electrode Ns14 and connect Nd15；The grid Ng15 of the 15th NMOS tube connects D, drain electrode Nd15 and connects the 14th NMOS tube
Source electrode Ns14, source electrode Ns15 connect Nd16；The grid Ng16 of the 16th NMOS tube connects rn01, drain electrode Nd16 and connects Ns15,
Source electrode Ns16 connects VSS；The grid Ng17 of the 17th NMOS tube connects the drain electrode Nd13 of the 13rd NMOS tube, drain electrode Nd17 and connects
The drain electrode Pd17 of the 17th PMOS, source electrode Ns17 connect VSS；The grid Ng18 of the 18th NMOS tube connects the 11st PMOS
Drain electrode Pd11, drain electrode Nd18 connect Pd18, source electrode connect VSS；The grid Ng19 of the 19th NMOS tube connects input c1, leakage
Pole Nd19 connects the drain electrode Nd20 of drain electrode Pd20, source electrode Ns19 connection the 20th NMOS tube of the 20th PMOS；20th
The grid Ng20 of NMOS tube connects the drain electrode Nd17 of the 17th NMOS tube, is simultaneously connected with m1r, drain electrode Nd20 and connects Ns19, source electrode
Ns20 connects VSS；The grid Ng21 of the 21st NMOS tube connects c2, drain electrode Nd21 and connects the Pd22 of the 22nd pipe, source electrode
Ns21 connects Nd22；The grid Ng22 of the 22nd NMOS tube connects the drain electrode Nd18 of the 18th NMOS tube, is simultaneously connected with m1, leakage
Pole Nd22 connects Ns21, and source electrode connects VSS；
Described have six inputs and four outfans, input and c1 from latch, and c2, cn1, cn2, m1, m1r are connected；Defeated
Going out end is s0, s0r, s1, s1r；It is made up of ten PMOS and ten NMOS tube from latch, all PMOS from latch
Substrate connect power vd D, the Substrate ground VSS of all NMOS tube；The grid Pg23 of the 23rd PMOS connects m1r, leakage
Pole Pd23 connects the source electrode Ps24, source electrode Ps23 of the 24th PMOS and connects power vd D；The grid of the 24th PMOS
Pg24 connects cn1, and drain electrode Pd24 connects the drain electrode Nd23 of the 23rd NMOS tube also as from latch outfan s0,
Source electrode Ps24 connects Pd23；The grid Pg25 of the 25th PMOS connects m1, drain electrode Pd25 and connects the 26th PMOS
Source electrode Ps26, source electrode Ps25 connect power vd D；The grid Pg26 of the 26th PMOS connects cn2, drain electrode Pd26 and connects second
The drain electrode Nd25 of 15 NMOS tube connects Pd25 as from another outfan s0r, source electrode Ps26 of latch；27th
The grid Pg27 of PMOS connects Pd24, drain electrode Pd27 and connects the drain electrode Nd27 of the 27th NMOS tube and as from latch
Another outfan s1, source electrode Ps27 connect power vd D；The grid Pg28 of the 28th PMOS connects Pd26, and drain Pd28
The drain electrode Nd28 connecting the 28th NMOS tube connects power supply as from another outfan s1r of latch, source electrode Ps28
VDD；The grid Pg29 of the 29th PMOS connects Pd28, drain electrode Pd29 and connects the source electrode Ps30 of the 30th PMOS, source electrode
Ps29 connects power vd D；The grid Pg30 of the 30th PMOS connects c1, drain electrode Pd30 and connects the drain electrode of the 29th NMOS tube
Nd29 also connects outfan s0, and source electrode Ps30 connects Pd29；The grid Pg31 of the 31st PMOS connects Pd27, and drain Pd31
Connect the source electrode Ps32 of the 32nd PMOS, source electrode Ps31 and connect power vd D；The grid Pg32 of the 32nd PMOS connects
C2, drain electrode Pd32 connect the drain electrode Nd31 of the 31st NMOS tube and connect outfan s0r, and source electrode Ps32 connects Pd31；Second
The grid Ng23 of 13 NMOS tube connects c1, drain electrode Nd23 and connects Pd24, source electrode Ns23 and connect the drain electrode of the 24th NMOS tube
Nd24；The grid Ng24 of the 24th NMOS tube connects m1, drain electrode Nd24 and connects Ns23, source electrode Ns24 ground connection VSS；25th
The grid Ng25 of NMOS tube connects c2, drain electrode Nd25 and connects Pd26, source electrode Ns25 and connect the drain electrode Nd26 of the 26th NMOS tube；
The grid Ng26 of the 26th NMOS tube connects m1r, drain electrode Nd26 and connects Ns25, source electrode Ns26 ground connection VSS；27th NMOS
The grid Ng27 of pipe connects Pd26, drain electrode Nd27 and connects Pd27, source electrode Ns27 ground connection VSS；The grid of the 28th NMOS tube
Ng28 connects Pd24, drain electrode Nd28 and connects Pd28, source electrode Ns28 ground connection VSS；The grid Ng29 of the 29th NMOS tube connects
Cn1, drain electrode Nd29 connect Pd30, source electrode Ns29 and connect the drain electrode Nd30 of the 30th NMOS tube；The grid of the 30th NMOS tube
Ng30 connects Pd27, drain electrode Nd30 and connects Ns29, source electrode Ns30 ground connection VSS；The grid Ng31 of the 31st NMOS tube connects
Cn2, drain electrode Nd31 connect Pd32 and outfan s0r, source electrode Ns31 and connect the drain electrode Nd32 of the 32nd NMOS tube；32nd
The grid Ng32 of NMOS tube connects Pd28, drain electrode Nd32 and connects Ns31, source electrode Ns32 ground connection VSS；
Described first inverter circuit has two inputs and an outfan, and input connects s1 and s1r, and outfan is QN；
First inverter circuit is made up of the 33rd PMOS and the 33rd NMOS tube；The substrate of the 33rd PMOS and source electrode
Ps33 is all connected with power vd D, the substrate of the 33rd NMOS tube and source electrode Ns33 equal ground connection VSS；The grid of the 33rd PMOS
Pole Pg33 meets input s1r, and drain electrode Pd33 connects the drain electrode Nd33 of the 33rd NMOS tube and as the outfan QN of phase inverter；
The grid Ng33 of the 33rd NMOS tube meets input s1, drain electrode Nd33 and connects Pd33；
Described second inverter circuit has two inputs and an outfan, and input connects s0 and s0r, and outfan is Q；The
Two inverter circuits are made up of the 34th PMOS and the 34th NMOS tube；The substrate of the 34th PMOS and source electrode
Ps34 is all connected with power vd D, the substrate of the 34th NMOS tube and source electrode Ns34 equal ground connection VSS；The grid of the 34th PMOS
Pole Pg34 meets input s0, and drain electrode Pd34 connects the drain electrode Nd34 of the 34th NMOS tube and as the outfan Q of phase inverter；The
The grid Ng34 of 34 NMOS tube meets input s0r, drain electrode Nd34 and connects Pd34.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310672227.6A CN103825583B (en) | 2013-12-11 | 2013-12-11 | Anti-single particle upset can synchronous reset d type flip flop with single-ion transient state |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310672227.6A CN103825583B (en) | 2013-12-11 | 2013-12-11 | Anti-single particle upset can synchronous reset d type flip flop with single-ion transient state |
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