CN103825585B - Anti-single particle upset and single-ion transient state can synchronous reset Scan Architecture d type flip flops - Google Patents
Anti-single particle upset and single-ion transient state can synchronous reset Scan Architecture d type flip flops Download PDFInfo
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- CN103825585B CN103825585B CN201310674467.XA CN201310674467A CN103825585B CN 103825585 B CN103825585 B CN 103825585B CN 201310674467 A CN201310674467 A CN 201310674467A CN 103825585 B CN103825585 B CN 103825585B
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Abstract
The invention discloses anti-single particle upset and single-ion transient state can synchronous reset Scan Architecture d type flip flop, it is therefore an objective to solving can the Scan Architecture d type flip flop anti-single particle upset of synchronous reset and the highest problem of single-ion transient state ability.The present invention is by buffer circuit, scan control buffer circuit, synchronous reset buffer circuit, clock circuit, main latch, form from latch and inverter circuit.Main latch and from latch be redundancy reinforce latch.Main latch and from series of latches, and be all connected with clock circuit.Main latch is also connected with buffer circuit, scan control buffer circuit, synchronous reset buffer circuit, is also connected with inverter circuit from latch.Separate main latch and the C being mutually redundant from latch2MOS circuit improves primary particle inversion resistant ability.Buffer circuits makes not make a mistake under long-term single event transient pulse, and duplication redundancy path adds the ability of anti-single particle transient state.
Description
Technical field
The present invention relates to a kind of synchronous reset structure and the D master-slave flip-flop of Scan Architecture, particularly to one
Anti-single particle upset (Single Event Upset, SEU) and anti-single particle transient state (Single Event Transient,
SET) can the Scan Architecture d type flip flop of synchronous reset.
Background technology
Cosmic space exists a large amount of high energy particle (proton, electronics, heavy ion etc.), in integrated circuit time
Sequence circuit is by after these high-energy particle bombardments, and its state kept is likely to occur upset, and this effect is referred to as
Single event upset effecf, the LET(linear energy transfer of single-particle bombardment integrated circuit) value is the highest, more holds
It is easily generated Single event upset effecf.Combinational circuit in integrated circuit is by, after these high-energy particle bombardments, having
May produce transient electrical pulses, this effect is referred to as single-ion transient state effect, the LET of single-particle bombardment integrated circuit
Being worth the highest, the transient electrical pulses persistent period of generation is the longest, and electric pulse is the easiest to be gathered by sequence circuit.As
Really the state of sequence circuit makes a mistake upset, or the transient electrical pulses that produces of single-ion transient state effect by time
Sequence circuit error gathers, and integrated circuit operation instability all can be caused even to produce fatal mistake, and this is in boat
My god, military field is particularly acute.Therefore, integrated circuit is reinforced thus reduce Single event upset effecf
More and more important with single-ion transient state effect.
D type flip flop is to use one of most timing unit in integrated circuit, the upset of its anti-single particle and simple grain
The anti-single particle of whole integrated circuit is overturn by the ability of sub-transient state and the ability of single-ion transient state plays crucial work
With, d type flip flop is reinforced accordingly anti-single particle upset and the single-ion transient state energy that can make integrated circuit
Power is improved.
Traditional d type flip flop is D master-slave flip-flop, typically by main latch with from level series of latches structure
Become.Common lock storage is replaced with DICE(Dual Interlocked Storage Cell, dual interlocked storage cell)
Primary particle inversion resistant d type flip flop can be realized etc. redundancy ruggedized construction.Transform input and output on this basis
Port, it is possible to achieve anti-single particle upset simultaneously and single-ion transient state.M.J.Myjak et al. is at The47th
IEEE International Midwest Symposium the 47th IEEE electricity of on Circuits and Systems(
Road and the international conference of system Midwest) on " the Enhanced Fault-Tolerant CMOS Memory that delivers
Elements " (strengthening fault-tolerant cmos memory cell) (2004, the I-453～I-456 page) upper proposition
The DICE circuit of a kind of improvement, this circuit uses DICE circuit to carry out anti-single particle upset and reinforces, and handle
Bidirectional data line divide into two write data lines and two read data lines, by the duplication redundancy of data wire, makes
Travel to the single event transient pulse of DICE circuit by a certain data wire at any time and be difficult to cause whole
The upset of individual circuit state, thus realize the reinforcing for single-ion transient state.But the duplication redundancy of data wire
There is positive feedback loop, latch information upset can be produced under the single event transient pulse of longer duration,
Anti-single particle transient state ability is the highest.
D.G.Mavis etc. are in IEEE Reliability Physics Symposium(world Reliability Physics meeting)
On " the Soft error rate mitigation techniques for modern microcircuits " that deliver (reduce existing
Technology for microcircuit soft error rate) (2002 page 216 page-225) propose time sampling D touch
Send out device circuit.This circuit introduces delay and voting circuit in the feedback loop of latch data, thus possesses
Certain anti-single particle upset and single-ion transient state ability.But voting circuit itself does not possess anti-single particle transient state
Ability, under single event transient pulse can output error data, anti-single particle transient state ability is the highest.
The Chinese patent of Application No. 200910046337.5 discloses a kind of anti-single particle upset and single-particle wink
The d type flip flop of state pulse.This invention is a kind of d type flip flop being similar to that time sampling structure, including
Two variable connectors, two delay circuits, two protection gate circuits and three phase inverters, it is achieved that D triggers
The anti-single particle upset of device and the reinforcing of single-ion transient state.This patent has the ability of anti-single particle transient state, but
Outfan Q due to the 3rd reverser connects the input VIN0 of second variable connector, defines positive and negative
It is fed back to road, latch information upset, anti-single particle can be produced under the single event transient pulse of longer duration
Transient state ability is the highest.
Common D master-slave flip-flop is unfavorable for detecting circuit at test phase so that test job becomes
The most loaded down with trivial details, complicated.Scan Architecture is added on common D master-slave flip-flop architecture basics, can be effective
Ground simplifies circuit test work, i.e. can control the defeated of D master-slave flip-flop by scanning signal at test phase
Enter, and then control circuit state.
Some integrated circuit needs to control the state of d type flip flop in integrated circuit, forces d type flip flop output low
Level and the data wherein stored are set to logical zero.At Scan Architecture d type flip flop original structure base
Synchronous reset circuit and synchronous reset signal input is increased, it is possible to achieve the synchronous reset of d type flip flop on plinth
Structure, and the synchronous reset function of d type flip flop is controlled by synchronous reset signal.But can synchronize multiple at present
Position Scan Architecture d type flip flop anti-single particle upset and anti-single particle transient state ability the highest, be unfavorable for aviation,
The IC chip in the fields such as space flight uses.
The Chinese patent of Application No. 201110322679.2 discloses a kind of primary particle inversion resistant synchronization and answers
Bit scan structure d type flip flop, as it is shown in figure 1, this invention by clock circuit, main latch, from latch,
Scan control buffer circuit, the first inverter circuit and the second Nverter circuit composition, can be at higher LET
Normally work under the single-particle bombardment of value and do not produce single-particle inversion.Due to this invention in clock circuit,
Buffer circuit is not used before main latch, so not possessing the ability of anti-single particle transient state, and main latch
Device, it is provided without duplication redundancy from latch, when the LET value of single-particle bombardment is higher, a certain on circuit
The upset of individual node then can cause whole circuit to overturn.
Summary of the invention
The technical problem to be solved in the present invention is, for current can the Scan Architecture d type flip flop of synchronous reset
Anti-single particle upset ability and the highest problem of anti-single particle transient state, propose a kind of anti-single particle upset and simple grain
Sub-transient state can the Scan Architecture d type flip flop of synchronous reset.
Concretism of the present invention is: carries out duplication redundancy reinforcing to main latch with from latch, can resist list
Particle overturns；In clock circuit, add buffer circuit in reset circuit and before main latch, list can be resisted
Particle transient state；Cut off the positive feedback loop that may be caused from latch, Ke Yi by single event transient pulse
Do not overturn under the anti-single particle transient state of longer duration.
Anti-single particle of the present invention upset single-ion transient state can synchronous reset Scan Architecture d type flip flop by buffering electricity
Road, scan control buffer circuit, synchronous reset buffer circuit, clock circuit, main latch, from latch
Form with inverter circuit.Main latch and from latch be redundancy reinforce latch.Main latch and
From latch tandem, and all it is connected with clock circuit.Main latch also with buffer circuit, scan control
Buffer circuit, synchronous reset buffer circuit are connected, and are also connected with inverter circuit from latch.
The present invention has five inputs and an outfan.Five inputs are clock signal input terminal respectively
CK, data signal input D, scan control signal input SE, scan data input SI and synchronization
Reset signal input RN；Outfan is Q.
Clock circuit has an input and four outfans, and input is CK, outfan is c1, c2, cn1,
cn2.Clock circuit is made up of 12 PMOS and 14 NMOS, all PMOS in circuit
Substrate connects power vd D, the Substrate ground VSS of all NMOS tube.The grid of the 49th PMOS
Pole Pg49 connects CK, drain electrode Pd49 and connects the drain electrode Nd49 of the 49th NMOS tube；50th PMOS
The grid Pg50 of pipe connects the drain electrode Pd49 of the 49th PMOS, drain electrode Pd50 and connects the 50th NMOS
The drain electrode Nd50 of pipe, source electrode Ps50 connect power vd D；The grid Pg51 of the 51st PMOS is even
Meet the drain electrode Pd50 of the 50th PMOS, drain electrode Pd51 and connect the drain electrode Nd51 of the 51st NMOS tube,
Source electrode Ps51 connects power vd D；The grid Pg52 of the 52nd PMOS connects the 51st PMOS
The drain electrode Pd51 of pipe, drain electrode Pd52 connect the drain electrode Nd52, source electrode Ps52 of the 52nd NMOS tube even
Meet power vd D；The grid Pg53 of the 53rd PMOS connects CK, drain electrode Pd53 and connects the 50th
The source electrode Ps54 of four PMOS, source electrode Ps53 connect VDD；The grid Pg54 of the 54th PMOS
Connect the drain electrode Pd52 of the 52nd PMOS, drain electrode Pd54 and connect the drain electrode of the 53rd NMOS tube
Nd53, and the outfan cn1, source electrode Ps54 as clock circuit connect Pd53；55th PMOS
The grid Pg55 of pipe connects CK, drain electrode Pd55 and connects the source electrode Ps56 of the 56th PMOS, source electrode
Ps55 connects VDD；The grid Pg56 of the 56th PMOS connects the drain electrode of the 52nd PMOS
Pd52, drain electrode Pd56 connects the drain electrode Nd55 of the 55th NMOS tube and as clock circuit one is defeated
Going out and hold cn2, source electrode Ps56 connects Pd55；The grid Pg57 of the 57th PMOS connects the 57th
The grid Ng57 of NMOS tube the outfan c1, drain electrode Pd57 as clock circuit connect the 50th
The drain electrode Pd54 of four PMOS, and connect outfan cn1, source electrode Ps57 connects VDD；58th
The grid Pg58 of PMOS connects the grid Ng58 of the 58th NMOS tube and as the one of clock circuit
Individual outfan c2, drain electrode Pd58 connect the drain electrode Nd58 and outfan cn2 of the 58th NMOS tube, source
Pole Ps58 connects VDD；The grid Pg59 of the 59th PMOS connects outfan cn1, and drain Pd59
Connect outfan c1, source electrode Ps59 and connect VDD；The grid Pg60 of the 60th PMOS connects outfan
Cn2, drain electrode Pd60 connect outfan c2, source electrode Ps60 and connect VDD；The grid of the 49th NMOS tube
Pole Ng49 connects CK, drain electrode Nd49 and connects the drain electrode Pd49 of the 49th PMOS；50th NMOS
The grid Ng50 of pipe connects the drain electrode Nd49 of the 49th NMOS tube, drain electrode Nd50 and connects the 50th
The drain electrode Pd50 of PMOS, source electrode Ns50 connect VSS；The grid Ng51 of the 51st NMOS tube
Connect the drain electrode Nd50 of the 50th NMOS tube, drain electrode Nd51 and connect the drain electrode of the 51st PMOS
Pd51, source electrode Ns51 connect VSS；The grid Ng52 of the 52nd NMOS tube connects the 51st NMOS
The drain electrode Nd51 of pipe, drain electrode Nd52 connect the drain electrode Pd52, source electrode Ns52 of the 52nd PMOS even
Meet VSS；The grid Ng53 of the 53rd NMOS tube connects the drain electrode Nd52 of the 52nd NMOS tube,
Source electrode Ns53 connects the drain electrode Nd54 of the 54th NMOS tube, and drain electrode connects cn1；54th NMOS
The grid Ng54 of pipe connects CK, drain electrode Nd54 and connects the source electrode Nd53 of the 53rd NMOS tube, source
Pole Ns54 connects VSS；The grid Ng55 of the 55th NMOS tube connects the 52nd NMOS tube
Drain electrode Nd52, source electrode Ns55 connect the drain electrode Nd56 of the 56th NMOS tube, and drain electrode connects cn2；The
The grid Ng56 of 56 NMOS tube connects CK, drain electrode Nd56 and connects the source of the 55th NMOS tube
Pole Nd55, source electrode Ns56 connect VSS；The grid Ng57 of the 57th NMOS tube connects outfan c1,
Drain electrode Nd57 connects outfan cn2, source electrode Ns57 and connects the drain electrode Nd61 of the 61st NMOS tube；The
The grid Ng58 of 58 NMOS tube connects outfan c2, drain electrode Nd58 and connects outfan cn2, source electrode
Ns58 connects the drain electrode Nd62 of the 62nd NMOS tube；The grid Ng59 of the 59th NMOS tube is even
Meet outfan cn1, drain electrode Nd59 to connect outfan c1, source electrode Ns59 and connect VSS；60th NMOS
The grid Ng60 of pipe connects outfan cn2, drain electrode Nd60 and connects outfan c2, source electrode Ns60 and connect VSS；
The drain electrode Nd61 of the 61st NMOS tube connects the source electrode Ns57, grid Ng61 of the 57th NMOS tube
Connect outfan c1, source electrode Ns61 and connect VSS；The drain electrode Nd62 of the 62nd NMOS tube connects the
The source electrode Ns58 of 58 NMOS tube, grid Ng62 connect outfan c1, source electrode Ns62 and connect VSS.
Buffer circuit has an input and an outfan, and input is D, and outfan is D1.Buffering electricity
Routeing eight PMOS and eight NMOS tube compositions, in buffer circuit, the substrate of all PMOS connects
Power vd D, the Substrate ground VSS of all NMOS tube.The grid Pg1 of the first PMOS connects defeated
Entering D and the grid Ng1 with the first NMOS tube connects, drain electrode Pd1 connects the drain electrode of the first NMOS tube
Ng1, source electrode Ps1 connect VDD；The grid Pg2 of the second PMOS connects the drain electrode of the first PMOS
Pd1, drain electrode Pd2 connect the drain electrode Nd2, source electrode Ps2 of the second NMOS tube and connect VDD；3rd PMOS
The grid Pg3 of pipe connects the drain electrode Pd2 of the second PMOS, drain electrode Pd3 and connects the leakage of the 3rd NMOS tube
Pole Nd3, source electrode Ps3 connect VDD；The grid Pg4 of the 4th PMOS connects the leakage of the 3rd PMOS
Pole Pd3, drain electrode Pd4 connect the drain electrode Nd4, source electrode Ps4 of the 4th NMOS tube and connect VDD；5th PMOS
The grid Pg5 of pipe connects the drain electrode Pd4 of the 4th PMOS, drain electrode Pd5 and connects the leakage of the 5th NMOS tube
Pole Nd5, source electrode Ps5 connect VDD；The grid Pg6 of the 6th PMOS connects the leakage of the 5th PMOS
Pole Pd5, drain electrode Pd6 connect the drain electrode Nd6, source electrode Ps6 of the 6th NMOS tube and connect VDD；7th PMOS
The grid Pg7 of pipe connects the drain electrode Pd6 of the 6th PMOS, drain electrode Pd7 and connects the leakage of the 7th NMOS tube
Pole Nd7, source electrode Ps7 connect VDD；The grid Pg8 of the 8th PMOS connects the leakage of the 7th PMOS
Pole Pd7, drain electrode Pd8 connect the drain electrode Nd8 of the 8th NMOS tube and as the outfan D1 of buffer,
Source electrode Ps8 connects VDD；The grid Ng1 of the first NMOS tube connects Pg1, drain electrode Nd1 and connects Pd1,
Source electrode Ns1 connects VSS;The grid Ng2 of the second NMOS tube connects the drain electrode Nd1 of the first NMOS tube,
Drain electrode Nd2 connects Pd2, source electrode Ns2 and connects VSS；The grid Ng3 of the 3rd NMOS tube connects second
The drain electrode Nd2 of NMOS tube, drain electrode Nd3 connect Pd3, source electrode Ns3 and connect VSS；4th NMOS tube
Grid Ng4 connect the 3rd NMOS tube drain electrode Nd3, drain electrode Nd4 connect Pd4, source electrode Ns4 connect
VSS；The grid Ng5 of the 5th NMOS tube connects the drain electrode Nd4 of the 4th NMOS tube, and drain electrode Nd5 is even
Meet Pd5, source electrode Ns5 and connect VSS；The grid Ng6 of the 6th NMOS tube connects the 5th NMOS tube
Drain electrode Nd5, drain electrode Nd6 connect Pd6, source electrode Ns6 and connect VSS；The grid Ng7 of the 7th NMOS tube
Connect the drain electrode Nd6 of the 6th NMOS tube, drain electrode Nd7 to connect Pd7, source electrode Ns7 and connect VSS；8th
The grid Ng8 of NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, drain electrode Nd8 and connects Pd8, source electrode
Ns8 connects VSS.
Scan control buffer circuit has an input and an outfan, and input is SE, and outfan is
SEN.Scan control buffer circuit is made up of the 37th PMOS and the 37th NMOS tube.3rd
The substrate of 17 PMOS and source electrode Ps37 are all connected with power vd D, the substrate of the 37th NMOS tube
Ground connection VSS equal with source electrode Ns37.The grid Pg37 of the 37th PMOS connects SE, and drain Pd37
Connect the drain electrode Nd37 of the 37th NMOS tube, and as the outfan SEN of scan control circuit；The
The grid Ng37 of 37 NMOS tube connects SE, drain electrode Nd37 and connects Pd37.
Synchronous reset buffer circuit has an input and two outfans, and input is RN, and outfan is
RN1, RN2.Synchronous reset buffer circuit is made up of ten NMOS tube and ten PMOS, synchronizes multiple
In bit buffering circuit, the substrate of all PMOS connects power vd D, the Substrate ground of all NMOS tube
VSS.The grid Pg38 of the 38th PMOS connects RN, drain electrode Pd38 and connects the 38th NMOS
The drain electrode Nd38 of pipe, source electrode Ps38 connect power vd D；The grid Pg39 of the 39th PMOS is even
Meet the drain electrode Pd38 of the 38th PMOS, drain electrode Pd39 and connect the drain electrode of the 39th NMOS tube
Nd39, source electrode Ps39 connect power vd D；The grid Pg40 of the 40th PMOS connects the 39th
The drain electrode Pd39 of PMOS, drain electrode Pd40 connect the drain electrode Nd40, source electrode Ps40 of the 40th NMOS tube
Connect power vd D；The grid Pg41 of the 41st PMOS connects the drain electrode of the 40th PMOS
Pd40, drain electrode Pd41 connect the drain electrode Nd41, source electrode Ps41 of the 41st NMOS tube and connect power vd D；
The grid Pg42 of the 42nd PMOS connects RN, drain electrode Pd42 and connects the 43rd PMOS
Source electrode Ps43, source electrode Ps42 connect VDD；The grid Pg43 of the 43rd PMOS connects the 41st
The drain electrode Pd41 of PMOS, drain electrode Pd43 connect the drain electrode Nd42 of the 42nd NMOS tube, source electrode
Ps43 connects Pd42；The grid Pg44 of the 44th PMOS connects RN, drain electrode Pd44 and connects the 4th
The source electrode Ps45 of 15 PMOS, source electrode Ps44 connect VDD；The grid Pg45 of the 45th PMOS
Connect the drain electrode Pd41 of the 41st PMOS, drain electrode Pd45 and connect the drain electrode of the 44th NMOS tube
Nd44, source electrode Ps45 connect Pd44；The grid Pg46 of the 46th PMOS connects the 43rd PMOS
The drain electrode Pd43 of pipe, drain electrode Pd46 connect the drain electrode Nd46 of the 46th NMOS tube, and multiple as synchronizing
One outfan RN1, source electrode Ps46 of bit buffering circuit connect VDD；The grid of the 47th PMOS
Pole Pg47 connects the drain electrode Pd45 of the 45th PMOS, drain electrode Pd47 and connects the 47th NMOS
The drain electrode Nd47 of pipe, and as an outfan RN2, the source electrode Ps47 connection of synchronous reset buffer circuit
VDD；The grid Ng38 of the 38th NMOS tube connects RN, drain electrode Nd38 and connects the 38th PMOS
The drain electrode Pd38 of pipe, source electrode Ns38 connect VSS；The grid Ng39 of the 39th NMOS tube connects the
The drain electrode Nd38 of 38 NMOS tube, drain electrode Nd39 connect the drain electrode Pd39 of the 39th PMOS,
Source electrode Ns39 connects VSS；The grid Ng40 of the 40th NMOS tube connects the 39th NMOS tube
Drain electrode Nd39, drain electrode Nd40 connect the drain electrode Pd40, source electrode Ns40 of the 40th PMOS and connect VSS；
The grid Ng41 of the 41st NMOS tube connects the drain electrode Nd40 of the 40th NMOS tube, and drain Nd41
Connect the drain electrode Pd41 of the 41st PMOS, source electrode Ns41 and connect VSS；42nd NMOS tube
Grid Ng42 connect the 41st NMOS tube drain electrode Nd41, source electrode Ns42 connect the 43rd
The drain electrode Nd43 of NMOS tube, drain electrode Nd42 connect Pd43；The grid Ng43 of the 43rd NMOS tube
Connect RN, drain electrode Nd43 to connect the source electrode Nd42, source electrode Ns43 of the 42nd NMOS tube and connect VSS；
The grid Ng44 of the 44th NMOS tube connects the drain electrode Nd41, source electrode Ns44 of the 41st NMOS tube
Connect the drain electrode Nd45 of the 45th NMOS tube, drain electrode Nd44 and connect Pd45；45th NMOS
The grid Ng45 of pipe connects RN, drain electrode Nd45 and connects the source electrode Nd44 of the 44th NMOS tube, source
Pole Ns45 connects VSS；The grid Ng46 of the 46th NMOS tube connects Pd43, drain electrode Nd46 and connects
RN1, source electrode Ns46 connect VSS；The grid Ng47 of the 47th NMOS tube connects Pd45, drain electrode
Nd47 connects RN2, source electrode Ns47 and connects VSS.
Main latch has 11 inputs and two outfans, and input is D, D1, SI, SE, SEN,
RN1, RN2, c1, c2, cn1, cn2；Outfan is m1, m1r.Main latch is by 18 PMOS
Pipe and 18 NMOS tube compositions, in main latch, the substrate of all PMOS connects power vd D,
The Substrate ground VSS of all NMOS tube.The grid Pg9 of the 9th PMOS connects SI, and drain Pd9
Connect the source electrode Ps10 of the tenth PMOS, source electrode Ps9 and connect power vd D；The grid of the tenth PMOS
Pole Pg10 connects SEN, drain electrode Pd10 and connects the source electrode Ps14, source electrode Ps10 of the 14th PMOS even
Meet Pd9；The grid Pg11 of the 11st PMOS connects SE, drain electrode Pd11 and connects the 12nd PMOS
Source electrode Ps12, source electrode Ps11 connect power vd D；The grid Pg12 of the 12nd PMOS connects D,
Drain electrode Pd12 connects Ps14, source electrode Ps12 and connects Pd11；The grid Pg13 of the 13rd PMOS connects
RN1, drain electrode Pd13 connect Ps14, source electrode Ps13 and connect Pd11；The grid Pg14 of the 14th PMOS
Connect c1, drain electrode Pd14 to connect the drain electrode Nd9, source electrode Ps14 of the 9th NMOS tube and connect Pd10；Tenth
The grid Pg15 of five PMOS connects SI, drain electrode Pd15 and connects the source electrode Ps16 of the 16th PMOS,
Source electrode Ps15 connects power vd D；The grid Pg16 of the 16th PMOS connects SEN, and drain Pd16
Connect the source electrode Ps20 of the 20th PMOS, source electrode Ps16 and connect Pd15；The grid of the 17th PMOS
Pole Pg17 connects SE, drain electrode Pd17 and connects the source electrode Ps18, source electrode Ps18 of the 18th PMOS and connect
Power vd D；The grid Pg18 of the 18th PMOS connects D1, drain electrode Pd18 and connects the 20th PMOS
The source electrode Ps20 of pipe, source electrode Ps18 connect Pd17；The grid Pg19 of the 19th PMOS connects RN2,
Drain electrode Pd19 connects the source electrode Ps20, source electrode Ps19 of the 20th PMOS and connects Pd17；20th PMOS
The grid Pg20 of pipe connects c2, drain electrode Pd20 and connects the drain electrode Nd15, source electrode Ps20 of the 15th NMOS tube
Connect Pd16；The grid Pg21 of the 21st PMOS connects Pd14, drain electrode Pd21 and connects the 20th
The drain electrode Nd21 of one NMOS tube, and as an outfan m1r, the source electrode Ps21 connection of main latch
Power vd D；The grid Pg22 of the 22nd PMOS connects Pd20, drain electrode Pd22 and connects the 20th
The drain electrode Nd22 of two NMOS tube, and the outfan m1, source electrode Ps22 as main latch connect electricity
Source VDD；The grid Pg23 of the 23rd PMOS connects Pd22, drain electrode Pd23 and connects the 24th
The source electrode Ps24 of PMOS, source electrode Ps23 connect power vd D；The grid Pg24 of the 24th PMOS
Connect cn1, drain electrode Pd24 to connect the drain electrode Nd23, source electrode Ps24 of the 23rd NMOS tube and connect Pd23；
The grid Pg25 of the 25th PMOS connects Pd21, drain electrode Pd25 and connects the 26th PMOS
Source electrode Ps26, source electrode Ps25 connect power vd D；The grid Pg26 of the 26th PMOS connects cn2,
Drain electrode Pd26 connects drain electrode Nd25 and Pd20, source electrode Ps26 of the 25th NMOS tube and connects Pd25；
The grid Ng9 of the 9th NMOS tube connects cn1, drain electrode Nd9 and connects Pd14, source electrode Ns9 and connect the tenth
The drain electrode Nd10 of NMOS tube；The grid Ng10 of the tenth NMOS tube connects SE, drain electrode Nd10 and connects
Ns9, source electrode Ns10 connect the drain electrode Nd11 of the 11st NMOS tube；The grid Ng11 of the 11st NMOS tube
Connect SI, drain electrode Nd11 and connect Ns10, source electrode Ns11 ground connection VSS；The grid of the 12nd NMOS tube
Ng12 connects D, drain electrode Nd12 and connects Ns9, source electrode Ns12 and connect the drain electrode Nd13 of the 13rd NMOS tube；
The grid Ng13 of the 13rd NMOS tube connects SEN, drain electrode Nd13 and connects Ns12, source electrode Ns13 even
Meet the drain electrode Nd14 of the 14th NMOS tube；The grid Ng14 of the 14th NMOS tube connects RN2, leakage
Pole Nd14 connects Ns13, source electrode Ns14 ground connection VSS；The grid Ng15 of the 15th NMOS tube connects
Cn2, drain electrode Nd15 connect Pd20, source electrode Ns15 and connect the drain electrode Nd16 of the 16th NMOS tube；The
The grid Ng16 of 16 NMOS tube connects SE, drain electrode Nd16 and connects Ns15, source electrode Ns16 and connect the
The drain electrode Nd17 of 17 NMOS tube；The grid Ng17 of the 17th NMOS tube connects SI, and drain Nd17
Connect Ns16, source electrode Ns17 ground connection VSS；The grid Ng18 of the 18th NMOS tube connects D1, drain electrode
Nd18 connects Ns15, source electrode Ns18 and connects the drain electrode Nd19 of the 19th NMOS tube；19th NMOS
The grid Ng19 of pipe connects SEN, drain electrode Nd19 and connects Ns18, source electrode Ns19 and connect the 20th NMOS
The drain electrode Nd20 of pipe；The grid Ng20 of the 20th NMOS tube connects RN2, drain electrode Nd20 and connects Ns19,
Source electrode Ns20 ground connection VSS；The grid Ng21 of the 21st NMOS tube connects Pd20, and drain Nd21
Connect Pd21, source electrode Ns21 ground connection VSS；The grid Ng22 of the 22nd NMOS tube connects Pd14,
Drain electrode Nd22 connects Pd22, source electrode Ns22 ground connection VSS；The grid Ng23 of the 23rd NMOS tube
Connect c1, drain electrode Nd23 to connect Pd24, source electrode Ns23 and connect the drain electrode Nd24 of the 24th NMOS tube；
The grid Ng24 of the 24th NMOS tube connects Pd21, drain electrode Nd24 and connects Ns23, source electrode Ns24
Ground connection VSS；The grid Ng25 of the 25th NMOS tube connects c2, drain electrode Nd25 and connects Pd26, source
Pole Ns25 connects the drain electrode Nd26 of the 26th NMOS tube；The grid Ng26 of the 26th NMOS tube
Connect Pd22, drain electrode Nd26 and connect Ns25, source electrode Ns26 ground connection VSS.9th PMOS, the tenth
PMOS, the 11st PMOS and the tenth NMOS tube, the 11st NMOS tube, the 13rd NMOS
Scan Architecture in pipe composition main latch；13rd PMOS and the 14th NMOS tube composition main latch
Synchronous reset structure in device.
Having six inputs and two outfans from latch, input is c1, c2, cn1, cn2, m1,
m1r；Outfan is s1, s1r.It is made up of, from lock ten PMOS and ten NMOS tube from latch
In storage, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube.
The grid Pg27 of the 27th PMOS connects m1r, drain electrode Pd27 and connects the 28th PMOS
Source electrode Ps28, source electrode Ps27 connect power vd D；The grid Pg28 of the 28th PMOS connects cn1,
Drain electrode Pd28 connects the drain electrode Nd27, source electrode Ps28 of the 27th NMOS tube and connects Pd27；20th
The grid Pg29 of nine PMOS connects m1, drain electrode Pd29 and connects the source electrode Ps30 of the 30th PMOS,
Source electrode Ps29 connects power vd D；The grid Pg30 of the 30th PMOS connects cn2, and drain Pd30
Connect the drain electrode Nd29 of the 29th NMOS tube, source electrode Ps30 and connect Pd29；31st PMOS
The grid Pg31 of pipe connects Pd28, drain electrode Pd31 and connects the drain electrode Nd31 of the 31st NMOS tube, source
Pole Ps31 connects power vd D；The grid Pg32 of the 32nd PMOS connects Pd30, and drain Pd32
Connect the drain electrode Nd32 of the 32nd NMOS tube, source electrode Ps32 and connect power vd D；33rd PMOS
The grid Pg33 of pipe connects Pd32, drain electrode Pd33 and connects the source electrode Ps34 of the 34th PMOS, source electrode
Ps33 connects power vd D；The grid Pg34 of the 34th PMOS connects c1, drain electrode Pd34 and connects
Drain electrode Nd33 and Pd28 of the 33rd NMOS tube, and as from latch outfan s1, source
Pole Ps34 connects Pd33；The grid Pg35 of the 35th PMOS connects Pd31, drain electrode Pd35 and connects
The source electrode Ps36 of the 36th PMOS, source electrode Ps35 connect power vd D；36th PMOS
Grid Pg36 connect c2, drain electrode Pd36 connect the 35th NMOS tube drain electrode Nd35 and Pd30
And connect Pd35 as from latch outfan s1r, source electrode Ps36；27th NMOS tube
Grid Ng27 connects c, drain electrode Nd27 and connects Pd28, source electrode Ns27 and connect the 28th NMOS tube
Drain electrode Nd28；The grid Ng28 of the 28th NMOS tube connects m1, drain electrode Nd28 and connects Ns27,
Source electrode Ns28 ground connection VSS；The grid Ng29 of the 29th NMOS tube connects c2, drain electrode Nd29 and connects
Pd30, source electrode Ns29 connect the drain electrode Nd30 of the 30th NMOS tube；The grid of the 30th NMOS tube
Ng30 connects m1r, drain electrode Nd30 and connects Ns29, source electrode Ns30 ground connection VSS；31st NMOS
The grid Ng31 of pipe connects Pd30, drain electrode Nd31 and connects Pd31, source electrode Ns31 ground connection VSS；30th
The grid Ng32 of two NMOS tube connects Pd28, drain electrode Nd32 and connects Pd32, source electrode Ns32 ground connection VSS；
The grid Ng33 of the 33rd NMOS tube connects cn1, drain electrode Nd33 and connects Pd34, source electrode Ns33 even
Meet the drain electrode Nd34 of the 34th NMOS tube；The grid Ng34 of the 34th NMOS tube connects Pd31,
Drain electrode Nd34 connects Ns33, source electrode Ns34 ground connection VSS；The grid Ng35 of the 35th NMOS tube
Connect cn2, drain electrode Nd35 to connect Pd36, source electrode Ns35 and connect the drain electrode Nd36 of the 32nd NMOS tube；
The grid Ng36 of the 36th NMOS tube connects Pd32, drain electrode Nd36 and connects Ns35, source electrode Ns36
Ground connection VSS.
Inverter circuit has two inputs and an outfan, and input connects s1 and s1r, and outfan is Q.
Inverter circuit is made up of the 48th PMOS and the 48th NMOS tube.48th PMOS
The substrate of pipe and source electrode Ps48 are all connected with power vd D, the substrate of the 48th NMOS tube and source electrode Ns48
All ground connection VSS.The grid Pg48 of the 48th PMOS meets input s1, drain electrode Pd48 and connects the 4th
The drain electrode Nd48 of 18 NMOS tube, and as the outfan Q of inverter circuit, source electrode Ps48 connects power supply
VDD.The grid Ng48 of the 48th NMOS tube meets input s1r, drain electrode Nd48 and connects Pd48, source
Pole Ns48 ground connection VSS.
Anti-single particle of the present invention upset and anti-single particle transient state can the Scan Architecture d type flip flop work of synchronous reset
Make process as follows:
The Scan Architecture d type flip flop of anti-single particle of the present invention upset and anti-single particle transient state can when circuit test
Control the input of d type flip flop, and then control circuit state.Scan function is inputted by the i.e. scan control signal of SE
End controls, and scan values input is i.e. scanned signal input part control by SI.Anti-single particle of the present invention upset can synchronize
The Scan Architecture d type flip flop resetted can enter reset state, the present invention the time marquis being in normal operating conditions
Anti-single particle upset can the Scan Architecture d type flip flop of synchronous reset can be with clock synchronous reset, synchronous reset
Function is controlled by the i.e. synchronous reset signal input of RN.
When SE is low level, RN is anti-single particle of the present invention upset and anti-single particle transient state when being high level
Scan Architecture d type flip flop is in normal operating conditions.Buffer circuit receives D, produces the D1 with D homophase.
Clock circuit receives CK, is produced and CK by the inverter circuit of circuit intermediate formation after buffering it
Anti-phase cn1 and cn2, produces c1 and c2 with CK homophase by the inverter circuit of circuit end, and
Cn1, cn2, c1 and c2 are passed to main latch and from latch.Buffer circuits receives D, by D
After postponing, output and the D1 of D homophase, be between low period at CK, cn1 and cn2 be high level,
C1 and c2 is low level, main latch open, receive D and D1, and in D and D1 may with
Single event transient pulse filters, then by m1, m1r of latch output with D, D1 homophase, and
It is to preserve m1, m1r that a upper CK trailing edge samples；It is between high period at CK, cn1 and cn2
Being high level for low level, c1 and c2, main latch is in preservation state, preserves previous CK rising edge
D Yu D1 sampled m1 and m1r exporting homophase, open from latch and receive the defeated of main latch
Go out m1 and m1r, m1 and m1r buffers and export s1 and s1r anti-phase with m1 and m1r.?
Any time inverter circuit will receive output s1 and s1r from latch, buffers s1 and s1r defeated
Go out the Q anti-phase with s1 and s1r.
When SE is low level, RN is anti-single particle of the present invention upset and anti-single particle transient state when being low level
Scan Architecture d type flip flop is in synchronous reset state.Synchronous reset buffer circuit receives RN, produces and RN
RN1 and RN2 of homophase.Clock circuit receives CK, by circuit intermediate formation after buffering it
Inverter circuit produces cn1 and cn2 anti-phase with CK, produced by the inverter circuit of circuit end and
C1 and c2 of CK homophase, and cn1, cn2, c1 and c2 are passed to main latch and from latch.?
CK is between low period, cn1 and cn2 be high level, c1 and c2 be low level, main latch is opened, and connects
Export m1 and m1r of homophase after receiving RN1 and RN2 and it being carried out buffered, be in guarantor from latch
Deposit state, do not receive m1, m1r of main latch output, but preserve a CK trailing edge and sample
M1, m1r；Be between high period at CK, cn1 and cn2 be low level, c1 and c2 be high level,
Main latch is in preservation state, preserve RN1 and RN2 that previous CK rising edge samples and export with
M1 and m1r of phase, opens and receives output m1 and m1r of main latch, to m1 and m1r from latch
Carry out buffering and export s1 and s1r anti-phase with m1 and m1r.Inverter circuit will receive at any time
From output s1 and s1r of latch, s1 and s1r is buffered and exports the Q anti-phase with s1 and s1r.
When SE is high level, the Scan Architecture D of anti-single particle of the present invention upset and anti-single particle transient state triggers
Device is in scanning mode.Clock circuit receives CK, passes through the anti-phase of circuit intermediate formation after buffering it
Device circuit produces cn1 and cn2 anti-phase with CK, is produced same with CK by the inverter circuit of circuit end
C1 and c2 of phase, and cn1, cn2, c1 and c2 are passed to main latch and from latch.At CK it is
Between low period, cn1 and cn2 be high level, c1 and c2 be low level, main latch is opened, and receives SI
And after it is carried out buffered, export m1 and m1r of homophase, it is in preservation state from latch, does not receives
M1, m1r of main latch output, but preserve m1, m1r that a CK trailing edge samples；?
CK is between high period, cn1 and cn2 be low level, c1 and c2 be high level, main latch is in preservation
State, preserves the SI that previous CK rising edge samples m1 and m1r exporting homophase, opens from latch
Open and receive output m1 and m1r of main latch, m1 and m1r is buffered and exports and m1 and m1r
Anti-phase s1 and s1r.Inverter circuit will receive output s1 and s1r from latch at any time, right
S1 and s1r buffers and exports the Q anti-phase with s1 and s1r.
Scan control buffer circuit exports the SEN anti-phase with SE after input signal carries out buffered, and will
It sends into main latch, is scanned the control of behavior.
Reset buffer circuit input signal is postponed after by the C of duplication redundancy2MOS structure filters RN
Middle may with single event transient pulse, and by output with RN1 and RN2 of RN homophase send into main lock
Storage and from latch, carries out the control of reset behavior.
Use the present invention can reach techniques below effect:
Anti-single particle of the present invention upset and anti-single particle transient state can the Scan Architecture d type flip flop of synchronous reset
Anti-single particle upset and anti-single particle transient state ability are better than that tradition is unguyed can the Scan Architecture D of synchronous reset
Trigger, time sampling reinforce can synchronous reset Scan Architecture d type flip flop and tradition duplication redundancy reinforce
Can the Scan Architecture d type flip flop of synchronous reset.The present invention to tradition is unguyed can the scanning of synchronous reset
Structure d type flip flop structure is transformed, to main latch with all carried out duplication redundancy reinforcing from latch,
And for main latch and from latch C2MOS circuit is improved, and i.e. separates the C being mutually redundant2
Pull-up PMOS in MOS circuit and pull-down NMOS pipe, improve the present invention primary particle inversion resistant
Ability.Add buffer circuit in clock circuit, in reset circuit and before main latch, make the present invention hold
Do not make a mistake under the single event transient pulse that the continuous time is longer；By well-designed duplication redundancy path, cut
The disconnected positive feedback loop that may be caused by single event transient pulse from latch, further increases anti-simple grain
The ability of sub-transient state.Anti-single particle of the present invention upset and single-ion transient state can the Scan Architecture D of synchronous reset
Trigger is suitable for anti-single particle upset and the standard cell lib of anti-single particle transient state reinforcing integrated circuit, should
For fields such as Aeronautics and Astronautics.
Accompanying drawing explanation
Fig. 1 is that the anti-single particle upset of Application No. 201110322679.2 can the Scan Architecture D of synchronous reset
Trigger overall logic structural representation
Fig. 2 be anti-single particle of the present invention upset and single-ion transient state can synchronous reset Scan Architecture D trigger
Device overall logic structural representation.
Fig. 3 be anti-single particle of the present invention upset and single-ion transient state can synchronous reset Scan Architecture D trigger
Clock circuit structural representation in device.
Fig. 4 be anti-single particle of the present invention upset and single-ion transient state can synchronous reset Scan Architecture D trigger
Buffer circuit structure schematic diagram in device.
Fig. 5 be anti-single particle of the present invention upset and single-ion transient state can synchronous reset Scan Architecture D trigger
Scan control buffer circuit structure schematic diagram in device.
Fig. 6 be anti-single particle of the present invention upset and single-ion transient state can synchronous reset Scan Architecture D trigger
Synchronous reset buffer circuit structure schematic diagram in device.
Fig. 7 be anti-single particle of the present invention upset and single-ion transient state can synchronous reset Scan Architecture D trigger
Main latch structural representation in device.
Fig. 8 be anti-single particle of the present invention upset and single-ion transient state can synchronous reset Scan Architecture D trigger
From latch structure schematic diagram in device.
Fig. 9 be anti-single particle of the present invention upset and single-ion transient state can synchronous reset Scan Architecture D trigger
Inverter circuit structure schematic diagram in device.
Detailed description of the invention
Fig. 2 is that the Scan Architecture d type flip flop logical structure of anti-single particle of the present invention upset and single-ion transient state is shown
It is intended to.The present invention is by clock circuit (as shown in Figure 3), buffer circuit (as shown in Figure 4), scan control
Buffer circuit (as shown in Figure 5), synchronous reset buffer circuit (as shown in Figure 6) main latch are (such as Fig. 7
Shown in), buffer (as shown in Figure 9) composition from latch (as shown in Figure 8) and phase inverter.The present invention
Anti-single particle upset and anti-single particle transient state the Scan Architecture d type flip flop of synchronous reset can have five inputs
With an outfan.Five inputs are clock signal input terminal CK, data signal input D respectively, sweep
Retouch control signal input SE, scan data input SI and synchronous reset signal input RN；Outfan
It is Q.Clock circuit receives CK, exports c1, c2 and cn1, cn2 after CK is carried out buffered respectively.
Buffer circuit receives D, exports D1 after D is carried out buffered respectively.Scan control buffer circuit receives
SE, exports SEN after SE carries out buffered.Synchronous reset buffer circuit receives RN, carries out RN
RN1 and RN2 is exported after buffered.Main latch receives D, D1, SI, SE, SEN, RN1, RN2,
C1, c2, cn1, cn2.When SE is high level, main latch is in c1, c2 and cn1, the control of cn2
Under SI carried out latch process after export m1, m1r；From latch receive m1, m1r and c1, c2 and
Cn1, cn2, from latch c1, c2 and cn1, cn2 control m1, m1r are carried out latch process
Rear export s1, s1r respectively；Inverter circuit receive s1, s1r, s1 and s1r buffer and exports and s1 and
The Q that s1r is anti-phase.When SE be high level, R1 and R2 be low level time, " 0 " is locked by main latch
" 0 ", " 0 " is exported after depositing process；From latch c1, c2 and cn1, cn2 control to " 0 ", " 0 "
" 1 ", " 1 " is exported respectively after carrying out latch process；Inverter circuit receives " 1 ", " 1 ", to " 1 ", " 1 "
Buffer and export " 0 " anti-phase with " 1 ", " 1 ".When SE be high level, R1 and R2 be high level time,
Main latch c1, c2 and cn1, cn2 control under D and D1 is carried out latch process after export m1,
m1r；Receive m1, m1r and c1, c2 and cn1, cn2 from latch, from latch at c1, c2 and
S1, s1r is exported respectively after m1, m1r being carried out latch process under the control of cn1, cn2；Inverter circuit connects
Receive s1, s1r, s1 and s1r is buffered and exports the Q anti-phase with s1 and s1r.
As it is shown on figure 3, clock circuit has an input and four outfans, input is CK, outfan
For c1, c2, cn1, cn2.Clock circuit is made up of, in circuit 12 PMOS and 14 NMOS
The substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube.40th
The grid Pg49 of nine PMOS connects CK, drain electrode Pd49 and connects the drain electrode of the 49th NMOS tube
Nd49；The grid Pg50 of the 50th PMOS connects the drain electrode Pd49 of the 49th PMOS, drain electrode
Pd50 connects the drain electrode Nd50, source electrode Ps50 of the 50th NMOS tube and connects power vd D；51st
The grid Pg51 of PMOS connects the drain electrode Pd50 of the 50th PMOS, drain electrode Pd51 and connects the 50th
The drain electrode Nd51 of one NMOS tube, source electrode Ps51 connect power vd D；The grid of the 52nd PMOS
Pole Pg52 connects the drain electrode Pd51 of the 51st PMOS, drain electrode Pd52 and connects the 52nd NMOS
The drain electrode Nd52 of pipe, source electrode Ps52 connect power vd D；The grid Pg53 of the 53rd PMOS is even
Meet CK, drain electrode Pd53 to connect the source electrode Ps54, source electrode Ps53 of the 54th PMOS and connect VDD；
The grid Pg54 of the 54th PMOS connects the drain electrode Pd52 of the 52nd PMOS, and drain Pd54
Connect the drain electrode Nd53 of the 53rd NMOS tube, and as an outfan cn1 of clock circuit, source electrode
Ps54 connects Pd53；The grid Pg55 of the 55th PMOS connects CK, drain electrode Pd55 and connects the 5th
The source electrode Ps56 of 16 PMOS, source electrode Ps55 connect VDD；The grid Pg56 of the 56th PMOS
Connect the drain electrode Pd52 of the 52nd PMOS, drain electrode Pd56 and connect the drain electrode of the 55th NMOS tube
Nd55 an outfan cn2, source electrode Ps56 as clock circuit connect Pd55；57th PMOS
The grid Pg57 of pipe connects the grid Ng57 of the 57th NMOS tube and as an output of clock circuit
End c1, drain electrode Pd57 connect the drain electrode Pd54 of the 54th PMOS, and connect outfan cn1, source
Pole Ps57 connects VDD；The grid Pg58 of the 58th PMOS connects the 58th NMOS tube
Grid Ng58 an outfan c2 as clock circuit, drain electrode Pd58 connects the 58th NMOS
The drain electrode Nd58 and outfan cn2 of pipe, source electrode Ps58 connect VDD；The grid of the 59th PMOS
Pg59 connects outfan cn1, drain electrode Pd59 and connects outfan c1, source electrode Ps59 and connect VDD；60th
The grid Pg60 of PMOS connects outfan cn2, drain electrode Pd60 and connects outfan c2, source electrode Ps60 even
Meet VDD；The grid Ng49 of the 49th NMOS tube connects CK, drain electrode Nd49 and connects the 49th
The drain electrode Pd49 of PMOS；The grid Ng50 of the 50th NMOS tube connects the 49th NMOS tube
Drain electrode Nd49, drain electrode Nd50 connect the drain electrode Pd50, source electrode Ns50 of the 50th PMOS and connect VSS；
The grid Ng51 of the 51st NMOS tube connects the drain electrode Nd50 of the 50th NMOS tube, and drain Nd51
Connect the drain electrode Pd51 of the 51st PMOS, source electrode Ns51 and connect VSS；52nd NMOS tube
Grid Ng52 connect the 51st NMOS tube drain electrode Nd51, drain electrode Nd52 connect the 52nd
The drain electrode Pd52 of PMOS, source electrode Ns52 connect VSS；The grid Ng53 of the 53rd NMOS tube
Connect the drain electrode Nd52 of the 52nd NMOS tube, source electrode Ns53 and connect the drain electrode of the 54th NMOS tube
Nd54, drain electrode connects cn1；The grid Ng54 of the 54th NMOS tube connects CK, and drain electrode Nd54 is even
Meet the source electrode Nd53 of the 53rd NMOS tube, source electrode Ns54 and connect VSS；55th NMOS tube
Grid Ng55 connect the 52nd NMOS tube drain electrode Nd52, source electrode Ns55 connect the 56th
The drain electrode Nd56 of NMOS tube, drain electrode connects cn2；The grid Ng56 of the 56th NMOS tube connects CK,
Drain electrode Nd56 connects the source electrode Nd55, source electrode Ns56 of the 55th NMOS tube and connects VSS；50th
The grid Ng57 of seven NMOS tube connects outfan c1, drain electrode Nd57 and connects outfan cn2, source electrode Ns57
Connect the drain electrode Nd61 of the 61st NMOS tube；The grid Ng58 of the 58th NMOS tube connects defeated
Going out and hold c2, drain electrode Nd58 connects outfan cn2, source electrode Ns58 and connects the drain electrode of the 62nd NMOS tube
Nd62；The grid Ng59 of the 59th NMOS tube connects outfan cn1, drain electrode Nd59 and connects outfan
C1, source electrode Ns59 connect VSS；The grid Ng60 of the 60th NMOS tube connects outfan cn2, drain electrode
Nd60 connects outfan c2, source electrode Ns60 and connects VSS；The drain electrode Nd61 of the 61st NMOS tube is even
Meet the source electrode Ns57 of the 57th NMOS tube, grid Ng61 and connect outfan c1, source electrode Ns61 connection
VSS；The drain electrode Nd62 of the 62nd NMOS tube connects the source electrode Ns58 of the 58th NMOS tube, grid
Pole Ng62 connects outfan c1, source electrode Ns62 and connects VSS.
As shown in Figure 4, buffer circuit has an input and an outfan, and input is D, outfan
For D1.Buffer circuit is made up of eight PMOS and eight NMOS tube, all PMOS in buffer circuit
The substrate of pipe connects power vd D, the Substrate ground VSS of all NMOS tube.The grid of the first PMOS
Pole Pg1 connects input D and the grid Ng1 with the first NMOS tube connects, and drain electrode Pd1 connects a NMOS
The drain electrode Ng1 of pipe, source electrode Ps1 connect VDD；The grid Pg2 of the second PMOS connects a PMOS
The drain electrode Pd1 of pipe, drain electrode Pd2 connect the drain electrode Nd2, source electrode Ps2 of the second NMOS tube and connect VDD；
The grid Pg3 of the 3rd PMOS connects the drain electrode Pd2 of the second PMOS, drain electrode Pd3 and connects the 3rd
The drain electrode Nd3 of NMOS tube, source electrode Ps3 connect VDD；The grid Pg4 of the 4th PMOS connects the 3rd
The drain electrode Pd3 of PMOS, drain electrode Pd4 connect the drain electrode Nd4, source electrode Ps4 of the 4th NMOS tube and connect
VDD；The grid Pg5 of the 5th PMOS connects the drain electrode Pd4 of the 4th PMOS, drain electrode Pd5 and connects
The drain electrode Nd5 of the 5th NMOS tube, source electrode Ps5 connect VDD；The grid Pg6 of the 6th PMOS is even
Meet the drain electrode Pd5 of the 5th PMOS, drain electrode Pd6 and connect the drain electrode Nd6, source electrode Ps6 of the 6th NMOS tube
Connect VDD；The grid Pg7 of the 7th PMOS connects the drain electrode Pd6 of the 6th PMOS, and drain Pd7
Connect the drain electrode Nd7 of the 7th NMOS tube, source electrode Ps7 and connect VDD；The grid Pg8 of the 8th PMOS
Connect the drain electrode Pd7 of the 7th PMOS, drain electrode Pd8 and connect drain electrode Nd8 the conduct of the 8th NMOS tube
The outfan D1 of buffer, source electrode Ps8 connect VDD；The grid Ng1 of the first NMOS tube connects Pg1,
Drain electrode Nd1 connects Pd1, source electrode Ns1 and connects VSS;The grid Ng2 of the second NMOS tube connects a NMOS
The drain electrode Nd1 of pipe, drain electrode Nd2 connect Pd2, source electrode Ns2 and connect VSS；The grid of the 3rd NMOS tube
Ng3 connects the drain electrode Nd2 of the second NMOS tube, drain electrode Nd3 and connects Pd3, source electrode Ns3 and connect VSS；
The grid Ng4 of the 4th NMOS tube connects the drain electrode Nd3 of the 3rd NMOS tube, drain electrode Nd4 and connects Pd4,
Source electrode Ns4 connects VSS；The grid Ng5 of the 5th NMOS tube connects the drain electrode Nd4 of the 4th NMOS tube,
Drain electrode Nd5 connects Pd5, source electrode Ns5 and connects VSS；The grid Ng6 of the 6th NMOS tube connects the 5th
The drain electrode Nd5 of NMOS tube, drain electrode Nd6 connect Pd6, source electrode Ns6 and connect VSS；7th NMOS tube
Grid Ng7 connect the 6th NMOS tube drain electrode Nd6, drain electrode Nd7 connect Pd7, source electrode Ns7 connect
VSS；The grid Ng8 of the 8th NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, and drain electrode Nd8 is even
Meet Pd8, source electrode Ns8 and connect VSS.
As it is shown in figure 5, scan control buffer circuit has an input and an outfan, input is SE,
Outfan is SEN.Scan control buffer circuit is by the 37th PMOS and the 37th NMOS tube group
Become.Substrate and the source electrode Ps37 of the 37th PMOS are all connected with power vd D, the 37th NMOS
The substrate of pipe and source electrode Ns37 equal ground connection VSS.The grid Pg37 of the 37th PMOS connects SE, leakage
Pole Pd37 connects the drain electrode Nd37 of the 37th NMOS tube, and as the outfan of scan control circuit
SEN；The grid Ng37 of the 37th NMOS tube connects SE, drain electrode Nd37 and connects Pd37.
As shown in Figure 6, synchronous reset buffer circuit has an input and two outfans, and input is RN,
Outfan is RN1, RN2.Synchronous reset buffer circuit is made up of ten NMOS tube and ten PMOS,
In synchronous reset buffer circuit, the substrate of all PMOS connects power vd D, the lining of all NMOS tube
End ground connection VSS.The grid Pg38 of the 38th PMOS connects RN, drain electrode Pd38 and connects the 30th
The drain electrode Nd38 of eight NMOS tube, source electrode Ps38 connect power vd D；The grid of the 39th PMOS
Pole Pg39 connects the drain electrode Pd38 of the 38th PMOS, drain electrode Pd39 and connects the 39th NMOS
The drain electrode Nd39 of pipe, source electrode Ps39 connect power vd D；The grid Pg40 of the 40th PMOS connects
The drain electrode Pd39 of the 39th PMOS, drain electrode Pd40 connect the drain electrode Nd40 of the 40th NMOS tube,
Source electrode Ps40 connects power vd D；The grid Pg41 of the 41st PMOS connects the 40th PMOS
The drain electrode Pd40 of pipe, drain electrode Pd41 connect the drain electrode Nd41, source electrode Ps41 of the 41st NMOS tube even
Meet power vd D；The grid Pg42 of the 42nd PMOS connects RN, drain electrode Pd42 and connects the 40th
The source electrode Ps43 of three PMOS, source electrode Ps42 connect VDD；The grid Pg43 of the 43rd PMOS
Connect the drain electrode Pd41 of the 41st PMOS, drain electrode Pd43 and connect the drain electrode of the 42nd NMOS tube
Nd42, source electrode Ps43 connect Pd42；The grid Pg44 of the 44th PMOS connects RN, and drain Pd44
Connect the source electrode Ps45 of the 45th PMOS, source electrode Ps44 and connect VDD；45th PMOS
Grid Pg45 connect the 41st PMOS drain electrode Pd41, drain electrode Pd45 connect the 44th NMOS
The drain electrode Nd44 of pipe, source electrode Ps45 connect Pd44；The grid Pg46 of the 46th PMOS connects the
The drain electrode Pd43 of 43 PMOS, drain electrode Pd46 connect the drain electrode Nd46 of the 46th NMOS tube,
And the outfan RN1, source electrode Ps46 as synchronous reset buffer circuit connects VDD；47th
The grid Pg47 of PMOS connects the drain electrode Pd45 of the 45th PMOS, drain electrode Pd47 and connects the 4th
The drain electrode Nd47 of 17 NMOS tube, and as an outfan RN2 of synchronous reset buffer circuit, source
Pole Ps47 connects VDD；The grid Ng38 of the 38th NMOS tube connects RN, drain electrode Nd38 and connects
The drain electrode Pd38 of the 38th PMOS, source electrode Ns38 connect VSS；The grid of the 39th NMOS tube
Pole Ng39 connects the drain electrode Nd38 of the 38th NMOS tube, drain electrode Nd39 and connects the 39th PMOS
The drain electrode Pd39 of pipe, source electrode Ns39 connect VSS；The grid Ng40 of the 40th NMOS tube connects the 3rd
The drain electrode Nd39 of 19 NMOS tube, drain electrode Nd40 connect the drain electrode Pd40 of the 40th PMOS, source
Pole Ns40 connects VSS；The grid Ng41 of the 41st NMOS tube connects the leakage of the 40th NMOS tube
Pole Nd40, drain electrode Nd41 connect the drain electrode Pd41, source electrode Ns41 of the 41st PMOS and connect VSS；
The grid Ng42 of the 42nd NMOS tube connects the drain electrode Nd41, source electrode Ns42 of the 41st NMOS tube
Connect the drain electrode Nd43 of the 43rd NMOS tube, drain electrode Nd42 and connect Pd43；43rd NMOS
The grid Ng43 of pipe connects RN, drain electrode Nd43 and connects the source electrode Nd42 of the 42nd NMOS tube, source
Pole Ns43 connects VSS；The grid Ng44 of the 44th NMOS tube connects the 41st NMOS tube
Drain electrode Nd41, source electrode Ns44 connect the drain electrode Nd45 of the 45th NMOS tube, drain electrode Nd44 and connect
Pd45；The grid Ng45 of the 45th NMOS tube connects RN, drain electrode Nd45 and connects the 44th NMOS
The source electrode Nd44 of pipe, source electrode Ns45 connect VSS；The grid Ng46 of the 46th NMOS tube connects Pd43,
Drain electrode Nd46 connects RN1, source electrode Ns46 and connects VSS；The grid Ng47 of the 47th NMOS tube is even
Meet Pd45, drain electrode Nd47 to connect RN2, source electrode Ns47 and connect VSS.
As it is shown in fig. 7, main latch has 11 inputs and two outfans, input is D, D1,
SI, SE, SEN, RN1, RN2, c1, c2, cn1, cn2；Outfan is m1, m1r.Main latch
Being made up of 18 PMOS and 18 NMOS tube, in main latch, the substrate of all PMOS is even
Meet power vd D, the Substrate ground VSS of all NMOS tube.The grid Pg9 of the 9th PMOS connects
SI, drain electrode Pd9 connect the source electrode Ps10, source electrode Ps9 of the tenth PMOS and connect power vd D；Tenth
The grid Pg10 of PMOS connects SEN, drain electrode Pd10 and connects the source electrode Ps14 of the 14th PMOS,
Source electrode Ps10 connects Pd9；The grid Pg11 of the 11st PMOS connects SE, drain electrode Pd11 and connects the
The source electrode Ps12 of 12 PMOS, source electrode Ps11 connect power vd D；The grid of the 12nd PMOS
Pg12 connects D, drain electrode Pd12 and connects Ps14, source electrode Ps12 and connect Pd11；13rd PMOS
Grid Pg13 connects RN1, drain electrode Pd13 and connects Ps14, source electrode Ps13 and connect Pd11；14th PMOS
The grid Pg14 of pipe connects c1, drain electrode Pd14 and connects the drain electrode Nd9, source electrode Ps14 of the 9th NMOS tube
Connect Pd10；The grid Pg15 of the 15th PMOS connects SI, drain electrode Pd15 and connects the 16th PMOS
The source electrode Ps16 of pipe, source electrode Ps15 connect power vd D；The grid Pg16 of the 16th PMOS connects
SEN, drain electrode Pd16 connect the source electrode Ps20, source electrode Ps16 of the 20th PMOS and connect Pd15；Tenth
The grid Pg17 of seven PMOS connects SE, drain electrode Pd17 and connects the source electrode Ps18 of the 18th PMOS,
Source electrode Ps18 connects power vd D；The grid Pg18 of the 18th PMOS connects D1, and drain electrode Pd18 is even
Meet the source electrode Ps20 of the 20th PMOS, source electrode Ps18 and connect Pd17；The grid of the 19th PMOS
Pg19 connects RN2, drain electrode Pd19 and connects the source electrode Ps20, source electrode Ps19 of the 20th PMOS and connect
Pd17；The grid Pg20 of the 20th PMOS connects c2, drain electrode Pd20 and connects the 15th NMOS tube
Drain electrode Nd15, source electrode Ps20 connect Pd16；The grid Pg21 of the 21st PMOS connects Pd14,
Drain electrode Pd21 connects the drain electrode Nd21 of the 21st NMOS tube, and as an outfan of main latch
M1r, source electrode Ps21 connect power vd D；The grid Pg22 of the 22nd PMOS connects Pd20, leakage
Pole Pd22 connects the drain electrode Nd22 of the 22nd NMOS tube, and as an outfan of main latch
M1, source electrode Ps22 connect power vd D；The grid Pg23 of the 23rd PMOS connects Pd22, leakage
Pole Pd23 connects the source electrode Ps24, source electrode Ps23 of the 24th PMOS and connects power vd D；20th
The grid Pg24 of four PMOS connects cn1, drain electrode Pd24 and connects the drain electrode of the 23rd NMOS tube
Nd23, source electrode Ps24 connect Pd23；The grid Pg25 of the 25th PMOS connects Pd21, drain electrode
Pd25 connects the source electrode Ps26, source electrode Ps25 of the 26th PMOS and connects power vd D；26th
The grid Pg26 of PMOS connects cn2, drain electrode Pd26 and connects the drain electrode Nd25 of the 25th NMOS tube
With Pd20, source electrode Ps26 connect Pd25；The grid Ng9 of the 9th NMOS tube connects cn1, and drain Nd9
Connect Pd14, source electrode Ns9 and connect the drain electrode Nd10 of the tenth NMOS tube；The grid of the tenth NMOS tube
Ng10 connects SE, drain electrode Nd10 and connects Ns9, source electrode Ns10 and connect the drain electrode of the 11st NMOS tube
Nd11；The grid Ng11 of the 11st NMOS tube connects SI, drain electrode Nd11 and connects Ns10, source electrode Ns11
Ground connection VSS；The grid Ng12 of the 12nd NMOS tube connects D, drain electrode Nd12 and connects Ns9, source electrode
Ns12 connects the drain electrode Nd13 of the 13rd NMOS tube；The grid Ng13 of the 13rd NMOS tube connects SEN,
Drain electrode Nd13 connects Ns12, source electrode Ns13 and connects the drain electrode Nd14 of the 14th NMOS tube；14th
The grid Ng14 of NMOS tube connects RN2, drain electrode Nd14 and connects Ns13, source electrode Ns14 ground connection VSS；
The grid Ng15 of the 15th NMOS tube connects cn2, drain electrode Nd15 and connects Pd20, source electrode Ns15 and connect
The drain electrode Nd16 of the 16th NMOS tube；The grid Ng16 of the 16th NMOS tube connects SE, and drain Nd16
Connect Ns15, source electrode Ns16 and connect the drain electrode Nd17 of the 17th NMOS tube；17th NMOS tube
Grid Ng17 connects SI, drain electrode Nd17 and connects Ns16, source electrode Ns17 ground connection VSS；18th NMOS
The grid Ng18 of pipe connects D1, drain electrode Nd18 and connects Ns15, source electrode Ns18 and connect the 19th NMOS
The drain electrode Nd19 of pipe；The grid Ng19 of the 19th NMOS tube connects SEN, drain electrode Nd19 and connects Ns18,
Source electrode Ns19 connects the drain electrode Nd20 of the 20th NMOS tube；The grid Ng20 of the 20th NMOS tube is even
Meet RN2, drain electrode Nd20 and connect Ns19, source electrode Ns20 ground connection VSS；The grid of the 21st NMOS tube
Pole Ng21 connects Pd20, drain electrode Nd21 and connects Pd21, source electrode Ns21 ground connection VSS；22nd NMOS
The grid Ng22 of pipe connects Pd14, drain electrode Nd22 and connects Pd22, source electrode Ns22 ground connection VSS；20th
The grid Ng23 of three NMOS tube connects c1, drain electrode Nd23 and connects Pd24, source electrode Ns23 and connect second
The drain electrode Nd24 of 14 NMOS tube；The grid Ng24 of the 24th NMOS tube connects Pd21, drain electrode
Nd24 connects Ns23, source electrode Ns24 ground connection VSS；The grid Ng25 of the 25th NMOS tube connects c2,
Drain electrode Nd25 connects Pd26, source electrode Ns25 and connects the drain electrode Nd26 of the 26th NMOS tube；20th
The grid Ng26 of six NMOS tube connects Pd22, drain electrode Nd26 and connects Ns25, source electrode Ns26 ground connection VSS.
9th PMOS, the tenth PMOS, the 11st PMOS and the tenth NMOS tube, the 11st
Scan Architecture in NMOS tube, the 13rd NMOS tube composition main latch；13rd PMOS and
Synchronous reset structure in 14 NMOS tube composition main latch.
As shown in Figure 8, having six inputs and two outfans from latch, input is c1, c2, cn1,
Cn2, m1, m1r；Outfan is s1, s1r.From latch by ten PMOS and ten NMOS tube
Composition, from latch, the substrate of all PMOS connects power vd D, the substrate of all NMOS tube
Ground connection VSS.The grid Pg27 of the 27th PMOS connects m1r, drain electrode Pd27 and connects the 28th
The source electrode Ps28 of PMOS, source electrode Ps27 connect power vd D；The grid Pg28 of the 28th PMOS
Connect cn1, drain electrode Pd28 to connect the drain electrode Nd27, source electrode Ps28 of the 27th NMOS tube and connect Pd27；
The grid Pg29 of the 29th PMOS connects m1, drain electrode Pd29 and connects the source of the 30th PMOS
Pole Ps30, source electrode Ps29 connect power vd D；The grid Pg30 of the 30th PMOS connects cn2, leakage
Pole Pd30 connects the drain electrode Nd29, source electrode Ps30 of the 29th NMOS tube and connects Pd29；31st
The grid Pg31 of PMOS connects Pd28, drain electrode Pd31 and connects the drain electrode Nd31 of the 31st NMOS tube,
Source electrode Ps31 connects power vd D；The grid Pg32 of the 32nd PMOS connects Pd30, and drain Pd32
Connect the drain electrode Nd32 of the 32nd NMOS tube, source electrode Ps32 and connect power vd D；33rd PMOS
The grid Pg33 of pipe connects Pd32, drain electrode Pd33 and connects the source electrode Ps34 of the 34th PMOS, source electrode
Ps33 connects power vd D；The grid Pg34 of the 34th PMOS connects c1, drain electrode Pd34 and connects
Drain electrode Nd33 and Pd28 of the 33rd NMOS tube, and as from latch outfan s1, source
Pole Ps34 connects Pd33；The grid Pg35 of the 35th PMOS connects Pd31, drain electrode Pd35 and connects
The source electrode Ps36 of the 36th PMOS, source electrode Ps35 connect power vd D；36th PMOS
Grid Pg36 connect c2, drain electrode Pd36 connect the 35th NMOS tube drain electrode Nd35 and Pd30
And connect Pd35 as from latch outfan s1r, source electrode Ps36；27th NMOS tube
Grid Ng27 connects c, drain electrode Nd27 and connects Pd28, source electrode Ns27 and connect the 28th NMOS tube
Drain electrode Nd28；The grid Ng28 of the 28th NMOS tube connects m1, drain electrode Nd28 and connects Ns27,
Source electrode Ns28 ground connection VSS；The grid Ng29 of the 29th NMOS tube connects c2, drain electrode Nd29 and connects
Pd30, source electrode Ns29 connect the drain electrode Nd30 of the 30th NMOS tube；The grid of the 30th NMOS tube
Ng30 connects m1r, drain electrode Nd30 and connects Ns29, source electrode Ns30 ground connection VSS；31st NMOS
The grid Ng31 of pipe connects Pd30, drain electrode Nd31 and connects Pd31, source electrode Ns31 ground connection VSS；30th
The grid Ng32 of two NMOS tube connects Pd28, drain electrode Nd32 and connects Pd32, source electrode Ns32 ground connection VSS；
The grid Ng33 of the 33rd NMOS tube connects cn1, drain electrode Nd33 and connects Pd34, source electrode Ns33 even
Meet the drain electrode Nd34 of the 34th NMOS tube；The grid Ng34 of the 34th NMOS tube connects Pd31,
Drain electrode Nd34 connects Ns33, source electrode Ns34 ground connection VSS；The grid Ng35 of the 35th NMOS tube
Connect cn2, drain electrode Nd35 to connect Pd36, source electrode Ns35 and connect the drain electrode Nd36 of the 32nd NMOS tube；
The grid Ng36 of the 36th NMOS tube connects Pd32, drain electrode Nd36 and connects Ns35, source electrode Ns36
Ground connection VSS.
As it is shown in figure 9, inverter circuit has two inputs and an outfan, input connects s1 and s1r,
Outfan is Q.Inverter circuit is made up of the 48th PMOS and the 48th NMOS tube.4th
The substrate of 18 PMOS and source electrode Ps48 are all connected with power vd D, the substrate of the 48th NMOS tube
Ground connection VSS equal with source electrode Ns48.The grid Pg48 of the 48th PMOS meets input s1, drain electrode
Pd48 connects the drain electrode Nd48 of the 48th NMOS tube, and as the outfan Q of inverter circuit, source
Pole Ps48 meets power vd D.The grid Ng48 of the 48th NMOS tube meets input s1r, and drain Nd48
Connect Pd48, source electrode Ns48 ground connection VSS.
Beijing Institute of Atomic Energy's H-13 tandem accelerator can produce LET value and be respectively
2.88MeV·cm2/mg、8.62MeV·cm2/mg、12.6MeV·cm2/ mg and 17.0MeV cm2/mg
Four kinds of ground heavy ion irradiation test environments.Unguyed for the tradition being in normal operating conditions is synchronized
Reset Scan Architecture d type flip flop, tradition duplication redundancy reinforce can synchronous reset Scan Architecture D trigger
What device, time sampling were reinforced can the Scan Architecture d type flip flop of synchronous reset, Application No. 201110322679.2
Chinese patent propose primary particle inversion resistant can synchronous reset Scan Architecture d type flip flop and the anti-list of the present invention
Particle upset and single-ion transient state the Scan Architecture d type flip flop of synchronous reset can connect identical 1000 respectively
The outfan of level reverser chain also works with the clock frequency of 40MHz, and the input of 1000 grades of reverser chains is even
Connect low level.Foregoing circuit is placed in the LET value point that Beijing Institute of Atomic Energy's H-13 tandem accelerator produces
Wei 2.88MeV cm2/mg、8.62MeV·cm2/mg、12.6MeV·cm2/ mg and 21.3MeV cm2/mg
Ground heavy ion irradiation test environment in, respectively can synchronous reset during adding up the heavy ion irradiation of each LET
Scan Architecture d type flip flop make a mistake output number of times.The total fluence of heavy ion irradiation of every kind of LET is
107ion/cm2.Table 1 is the ground heavy particle using Beijing Institute of Atomic Energy's H-13 tandem accelerator to carry out
What the tradition that obtains of irradiation test was unguyed can the Scan Architecture d type flip flop of synchronous reset, tradition duplication redundancy
Reinforce can the Scan Architecture d type flip flop of synchronous reset, time sampling reinforce can synchronous reset scanning knot
Structure d type flip flop, the Chinese patent of Application No. 201110322679.2 propose primary particle inversion resistant can be with
Step reset Scan Architecture d type flip flop and anti-single particle of the present invention upset and single-ion transient state can synchronous reset
Scan Architecture d type flip flop is respectively 2.88MeV cm in LET value2/mg、8.62MeV·cm2/mg、
12.6MeV·cm2/ mg and 21.3MeV cm2Make a mistake during the ground heavy ion irradiation of/mg defeated
The number of times gone out.The total fluence of heavy ion irradiation of every kind of LET is 107ion/cm2.Statistics from table 1 can
Go out, the upset of the anti-single particle of the present invention and single-ion transient state ability be better than tradition unguyed can synchronous reset
What Scan Architecture d type flip flop, time sampling were reinforced can the Scan Architecture d type flip flop of synchronous reset, application number
Be 201110322679.2 Chinese patent propose primary particle inversion resistant can synchronous reset Scan Architecture D touch
Send out device and tradition duplication redundancy is reinforced can the Scan Architecture d type flip flop of synchronous reset, be suitable for anti-simple grain
Son upset and single-ion transient state reinforce the standard cell lib of integrated circuit, are applied to the fields such as Aeronautics and Astronautics.
Table 1
Claims (1)
1. anti-single particle upset and single-ion transient state can synchronous reset Scan Architecture d type flip flop, including time
Clock circuit, scan control buffer circuit, main latch, from latch, inverter circuit, its feature exists
In anti-single particle upset single-ion transient state can synchronous reset Scan Architecture d type flip flop also include buffer circuit,
Synchronous reset buffer circuit, and inverter circuit only one of which；Main latch and be redundancy from latch
The latch reinforced, main latch and from latch tandem, and be all connected with clock circuit；Main lock
Storage is also connected, from latch with buffer circuit, scan control buffer circuit, synchronous reset buffer circuit
Also it is connected with inverter circuit；Having five inputs and an outfan, five inputs are clock respectively
Signal input part CK, data signal input D, scan control signal input SE, scan data are defeated
Entering to hold SI and synchronous reset signal input RN, outfan is Q；
Described clock circuit has an input and four outfans, and input is CK, outfan be c1,
c2、cn1、cn2；Clock circuit is made up of 12 PMOS and 14 NMOS, institute in circuit
The substrate having PMOS connects power vd D, the Substrate ground VSS of all NMOS tube；40th
The grid Pg49 of nine PMOS connects CK, drain electrode Pd49 and connects the leakage of the 49th NMOS tube
Pole Nd49；The grid Pg50 of the 50th PMOS connects the drain electrode Pd49 of the 49th PMOS,
Drain electrode Pd50 connects the drain electrode Nd50, source electrode Ps50 of the 50th NMOS tube and connects power vd D；The
The grid Pg51 of 51 PMOS connects the drain electrode Pd50 of the 50th PMOS, and drain Pd51
Connect the drain electrode Nd51 of the 51st NMOS tube, source electrode Ps51 and connect power vd D；52nd
The grid Pg52 of PMOS connects the drain electrode Pd51 of the 51st PMOS, drain electrode Pd52 and connects
The drain electrode Nd52 of the 52nd NMOS tube, source electrode Ps52 connect power vd D；53rd PMOS
The grid Pg53 of pipe connects CK, drain electrode Pd53 and connects the source electrode Ps54 of the 54th PMOS, source
Pole Ps53 connects VDD；The grid Pg54 of the 54th PMOS connects the 52nd PMOS
Drain electrode Pd52, drain electrode Pd54 connects the drain electrode Nd53 of the 53rd NMOS tube, and as clock
One outfan cn1, source electrode Ps54 of circuit connect Pd53；The grid Pg55 of the 55th PMOS
Connect CK, drain electrode Pd55 to connect the source electrode Ps56, source electrode Ps55 of the 56th PMOS and connect
VDD；The grid Pg56 of the 56th PMOS connects the drain electrode Pd52 of the 52nd PMOS,
Drain electrode Pd56 connects the drain electrode Nd55 of the 55th NMOS tube and as an output of clock circuit
End cn2, source electrode Ps56 connect Pd55；The grid Pg57 of the 57th PMOS connects the 57th
The grid Ng57 of NMOS tube an outfan c1 as clock circuit, drain electrode Pd57 connects the
The drain electrode Pd54 of 54 PMOS, and connect outfan cn1, source electrode Ps57 connects VDD；The
The grid Pg58 of 58 PMOS connect the 58th NMOS tube grid Ng58 and as time
One outfan c2 of clock circuit, drain electrode Pd58 connect the 58th NMOS tube drain electrode Nd58 and
Outfan cn2, source electrode Ps58 connect VDD；The grid Pg59 of the 59th PMOS connects defeated
Going out and hold cn1, drain electrode Pd59 connects outfan c1, source electrode Ps59 and connects VDD；60th PMOS
The grid Pg60 of pipe connects outfan cn2, drain electrode Pd60 and connects outfan c2, source electrode Ps60 and connect
VDD；The grid Ng49 of the 49th NMOS tube connects CK, drain electrode Nd49 and connects the 49th
The drain electrode Pd49 of PMOS；The grid Ng50 of the 50th NMOS tube connects the 49th NMOS
The drain electrode Nd49 of pipe, drain electrode Nd50 connect the drain electrode Pd50, source electrode Ns50 of the 50th PMOS
Connect VSS；The grid Ng51 of the 51st NMOS tube connects the drain electrode of the 50th NMOS tube
Nd50, drain electrode Nd51 connect the drain electrode Pd51, source electrode Ns51 of the 51st PMOS and connect VSS；
The grid Ng52 of the 52nd NMOS tube connects the drain electrode Nd51 of the 51st NMOS tube, drain electrode
Nd52 connects the drain electrode Pd52, source electrode Ns52 of the 52nd PMOS and connects VSS；53rd
The grid Ng53 of NMOS tube connects the drain electrode Nd52, source electrode Ns53 of the 52nd NMOS tube even
Meeting the drain electrode Nd54 of the 54th NMOS tube, drain electrode connects cn1；The grid of the 54th NMOS tube
Pole Ng54 connects CK, drain electrode Nd54 and connects the source electrode Nd53 of the 53rd NMOS tube, source electrode
Ns54 connects VSS；The grid Ng55 of the 55th NMOS tube connects the 52nd NMOS tube
Drain electrode Nd52, source electrode Ns55 connect the drain electrode Nd56 of the 56th NMOS tube, and drain electrode connects cn2；
The grid Ng56 of the 56th NMOS tube connects CK, drain electrode Nd56 and connects the 55th NMOS
The source electrode Nd55 of pipe, source electrode Ns56 connect VSS；The grid Ng57 of the 57th NMOS tube connects
Outfan c1, drain electrode Nd57 connect outfan cn2, source electrode Ns57 and connect the 61st NMOS tube
Drain electrode Nd61；The grid Ng58 of the 58th NMOS tube connects outfan c2, and drain Nd58
Connect outfan cn2, source electrode Ns58 and connect the drain electrode Nd62 of the 62nd NMOS tube；59th
The grid Ng59 of NMOS tube connects outfan cn1, drain electrode Nd59 and connects outfan c1, source electrode Ns59
Connect VSS；The grid Ng60 of the 60th NMOS tube connects outfan cn2, drain electrode Nd60 and connects
Outfan c2, source electrode Ns60 connect VSS；The drain electrode Nd61 of the 61st NMOS tube connects the 5th
The source electrode Ns57 of 17 NMOS tube, grid Ng61 connect outfan c1, source electrode Ns61 and connect VSS；
The drain electrode Nd62 of the 62nd NMOS tube connects the source electrode Ns58 of the 58th NMOS tube, grid
Ng62 connects outfan c1, source electrode Ns62 and connects VSS；
Described buffer circuit has an input and an outfan, and input is D, and outfan is D1；
Buffer circuit is made up of eight PMOS and eight NMOS tube, all PMOS in buffer circuit
Substrate connect power vd D, the Substrate ground VSS of all NMOS tube；The grid of the first PMOS
Pole Pg1 connects input D and the grid Ng1 with the first NMOS tube connects, and drain electrode Pd1 connects first
The drain electrode Ng1 of NMOS tube, source electrode Ps1 connect VDD；The grid Pg2 of the second PMOS connects
The drain electrode Pd1 of the first PMOS, drain electrode Pd2 connect the drain electrode Nd2 of the second NMOS tube, source electrode
Ps2 connects VDD；The grid Pg3 of the 3rd PMOS connects the drain electrode Pd2 of the second PMOS,
Drain electrode Pd3 connects the drain electrode Nd3, source electrode Ps3 of the 3rd NMOS tube and connects VDD；4th PMOS
The grid Pg4 of pipe connects the drain electrode Pd3 of the 3rd PMOS, drain electrode Pd4 and connects the 4th NMOS tube
Drain electrode Nd4, source electrode Ps4 connect VDD；The grid Pg5 of the 5th PMOS connects the 4th PMOS
The drain electrode Pd4 of pipe, drain electrode Pd5 connect the drain electrode Nd5, source electrode Ps5 of the 5th NMOS tube and connect VDD；
The grid Pg6 of the 6th PMOS connects the drain electrode Pd5 of the 5th PMOS, drain electrode Pd6 and connects the
The drain electrode Nd6 of six NMOS tube, source electrode Ps6 connect VDD；The grid Pg7 of the 7th PMOS is even
Meet the drain electrode Pd6 of the 6th PMOS, drain electrode Pd7 and connect the drain electrode Nd7 of the 7th NMOS tube, source
Pole Ps7 connects VDD；The grid Pg8 of the 8th PMOS connects the drain electrode Pd7 of the 7th PMOS,
Drain electrode Pd8 connects the drain electrode Nd8 of the 8th NMOS tube and as the outfan D1 of buffer, source electrode
Ps8 connects VDD；The grid Ng1 of the first NMOS tube connects Pg1, drain electrode Nd1 and connects Pd1,
Source electrode Ns1 connects VSS；The grid Ng2 of the second NMOS tube connects the drain electrode Nd1 of the first NMOS tube,
Drain electrode Nd2 connects Pd2, source electrode Ns2 and connects VSS；The grid Ng3 of the 3rd NMOS tube connects the
The drain electrode Nd2 of two NMOS tube, drain electrode Nd3 connect Pd3, source electrode Ns3 and connect VSS；4th NMOS
The grid Ng4 of pipe connects the drain electrode Nd3 of the 3rd NMOS tube, drain electrode Nd4 and connects Pd4, source electrode Ns4
Connect VSS；The grid Ng5 of the 5th NMOS tube connects the drain electrode Nd4 of the 4th NMOS tube, drain electrode
Nd5 connects Pd5, source electrode Ns5 and connects VSS；The grid Ng6 of the 6th NMOS tube connects the 5th NMOS
The drain electrode Nd5 of pipe, drain electrode Nd6 connect Pd6, source electrode Ns6 and connect VSS；7th NMOS tube
Grid Ng7 connects the drain electrode Nd6 of the 6th NMOS tube, drain electrode Nd7 and connects Pd7, source electrode Ns7 even
Meet VSS；The grid Ng8 of the 8th NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, drain electrode
Nd8 connects Pd8, source electrode Ns8 and connects VSS；
Described scan control buffer circuit has an input and an outfan, and input is SE, defeated
Going out end is SEN；Scan control buffer circuit is by the 37th PMOS and the 37th NMOS tube
Composition；Substrate and the source electrode Ps37 of the 37th PMOS are all connected with power vd D, and the 37th
The substrate of NMOS tube and source electrode Ns37 equal ground connection VSS；The grid Pg37 of the 37th PMOS
Connect SE, drain electrode Pd37 and connect the drain electrode Nd37 of the 37th NMOS tube, and as scan control
The outfan SEN of circuit；The grid Ng37 of the 37th NMOS tube connects SE, and drain Nd37
Connect Pd37；
Described synchronous reset buffer circuit has an input and two outfans, and input is RN, defeated
Going out end is RN1, RN2；Synchronous reset buffer circuit is by ten NMOS tube and ten PMOS groups
Becoming, in synchronous reset buffer circuit, the substrate of all PMOS connects power vd D, all NMOS
The Substrate ground VSS of pipe；The grid Pg38 of the 38th PMOS connects RN, and drain electrode Pd38 is even
Meet the drain electrode Nd38 of the 38th NMOS tube, source electrode Ps38 and connect power vd D；39th
The grid Pg39 of PMOS connects the drain electrode Pd38 of the 38th PMOS, drain electrode Pd39 and connects
The drain electrode Nd39 of the 39th NMOS tube, source electrode Ps39 connect power vd D；40th PMOS
The grid Pg40 of pipe connects the drain electrode Pd39 of the 39th PMOS, drain electrode Pd40 and connects the 40th
The drain electrode Nd40 of NMOS tube, source electrode Ps40 connect power vd D；The grid of the 41st PMOS
Pole Pg41 connects the drain electrode Pd40 of the 40th PMOS, drain electrode Pd41 and connects the 41st NMOS
The drain electrode Nd41 of pipe, source electrode Ps41 connect power vd D；The grid Pg42 of the 42nd PMOS
Connect RN, drain electrode Pd42 to connect the source electrode Ps43, source electrode Ps42 of the 43rd PMOS and connect
VDD；The grid Pg43 of the 43rd PMOS connects the drain electrode Pd41 of the 41st PMOS,
Drain electrode Pd43 connects the drain electrode Nd42, source electrode Ps43 of the 42nd NMOS tube and connects Pd42；4th
The grid Pg44 of 14 PMOS connects RN, drain electrode Pd44 and connects the source of the 45th PMOS
Pole Ps45, source electrode Ps44 connect VDD；The grid Pg45 of the 45th PMOS connects the 40th
The drain electrode Pd41 of one PMOS, drain electrode Pd45 connect the drain electrode Nd44 of the 44th NMOS tube,
Source electrode Ps45 connects Pd44；The grid Pg46 of the 46th PMOS connects the 43rd PMOS
The drain electrode Pd43 of pipe, drain electrode Pd46 connect the drain electrode Nd46 of the 46th NMOS tube, and as same
One outfan RN1, source electrode Ps46 of step reset buffer circuit connect VDD；47th PMOS
The grid Pg47 of pipe connects the drain electrode Pd45 of the 45th PMOS, drain electrode Pd47 and connects the 40th
The drain electrode Nd47 of seven NMOS tube, and as an outfan RN2 of synchronous reset buffer circuit, source
Pole Ps47 connects VDD；The grid Ng38 of the 38th NMOS tube connects RN, and drain Nd38
Connect the drain electrode Pd38 of the 38th PMOS, source electrode Ns38 and connect VSS；39th NMOS
The grid Ng39 of pipe connects the drain electrode Nd38 of the 38th NMOS tube, drain electrode Nd39 and connects the 3rd
The drain electrode Pd39 of 19 PMOS, source electrode Ns39 connect VSS；The grid of the 40th NMOS tube
Ng40 connects the drain electrode Nd39 of the 39th NMOS tube, drain electrode Nd40 and connects the 40th PMOS
The drain electrode Pd40 of pipe, source electrode Ns40 connect VSS；The grid Ng41 of the 41st NMOS tube connects
The drain electrode Nd40 of the 40th NMOS tube, drain electrode Nd41 connect the drain electrode of the 41st PMOS
Pd41, source electrode Ns41 connect VSS；The grid Ng42 of the 42nd NMOS tube connects the 41st
The drain electrode Nd41 of NMOS tube, source electrode Ns42 connect the drain electrode Nd43 of the 43rd NMOS tube, leakage
Pole Nd42 connects Pd43；The grid Ng43 of the 43rd NMOS tube connects RN, and drain Nd43
Connect the source electrode Nd42 of the 42nd NMOS tube, source electrode Ns43 and connect VSS；44th NMOS
The grid Ng44 of pipe connects the drain electrode Nd41, source electrode Ns44 of the 41st NMOS tube and connects the 40th
The drain electrode Nd45 of five NMOS tube, drain electrode Nd44 connect Pd45；The grid of the 45th NMOS tube
Ng45 connects RN, drain electrode Nd45 and connects the source electrode Nd44, source electrode Ns45 of the 44th NMOS tube
Connect VSS；The grid Ng46 of the 46th NMOS tube connects Pd43, drain electrode Nd46 and connects RN1,
Source electrode Ns46 connects VSS；The grid Ng47 of the 47th NMOS tube connects Pd45, and drain Nd47
Connect RN2, source electrode Ns47 and connect VSS；
Described main latch has 11 inputs and two outfans, and input is D, D1, SI, SE,
SEN, RN1, RN2, c1, c2, cn1, cn2；Outfan is m1, m1r；Main latch is by ten
Eight PMOS and 18 NMOS tube compositions, in main latch, the substrate of all PMOS is even
Meet power vd D, the Substrate ground VSS of all NMOS tube；The grid Pg9 of the 9th PMOS is even
Meet SI, drain electrode Pd9 to connect the source electrode Ps10, source electrode Ps9 of the tenth PMOS and connect power vd D；
The grid Pg10 of the tenth PMOS connects SEN, drain electrode Pd10 and connects the source of the 14th PMOS
Pole Ps14, source electrode Ps10 connect Pd9；The grid Pg11 of the 11st PMOS connects SE, drain electrode
Pd11 connects the source electrode Ps12, source electrode Ps11 of the 12nd PMOS and connects power vd D；12nd
The grid Pg12 of PMOS connects D, drain electrode Pd12 and connects Ps14, source electrode Ps12 and connect Pd11；
The grid Pg13 of the 13rd PMOS connects RN1, drain electrode Pd13 and connects Ps14, source electrode Ps13 even
Meet Pd11；The grid Pg14 of the 14th PMOS connects c1, drain electrode Pd14 and connects the 9th NMOS
The drain electrode Nd9 of pipe, source electrode Ps14 connect Pd10；The grid Pg15 of the 15th PMOS connects SI,
Drain electrode Pd15 connects the source electrode Ps16, source electrode Ps15 of the 16th PMOS and connects power vd D；The
The grid Pg16 of 16 PMOS connects SEN, drain electrode Pd16 and connects the source of the 20th PMOS
Pole Ps20, source electrode Ps16 connect Pd15；The grid Pg17 of the 17th PMOS connects SE, drain electrode
Pd17 connects the source electrode Ps18, source electrode Ps18 of the 18th PMOS and connects power vd D；18th
The grid Pg18 of PMOS connects D1, drain electrode Pd18 and connects the source electrode Ps20 of the 20th PMOS,
Source electrode Ps18 connects Pd17；The grid Pg19 of the 19th PMOS connects RN2, and drain Pd19
Connect the source electrode Ps20 of the 20th PMOS, source electrode Ps19 and connect Pd17；20th PMOS
Grid Pg20 connect c2, drain electrode Pd20 connect the 15th NMOS tube drain electrode Nd15, source electrode
Ps20 connects Pd16；The grid Pg21 of the 21st PMOS connects Pd14, drain electrode Pd21 and connects
The drain electrode Nd21 of the 21st NMOS tube, and as an outfan m1r of main latch, source electrode
Ps21 connects power vd D；The grid Pg22 of the 22nd PMOS connects Pd20, and drain Pd22
Connect the drain electrode Nd22 of the 22nd NMOS tube, and as an outfan m1 of main latch,
Source electrode Ps22 connects power vd D；The grid Pg23 of the 23rd PMOS connects Pd22, drain electrode
Pd23 connects the source electrode Ps24, source electrode Ps23 of the 24th PMOS and connects power vd D；Second
The grid Pg24 of 14 PMOS connects cn1, drain electrode Pd24 and connects the 23rd NMOS tube
Drain electrode Nd23, source electrode Ps24 connect Pd23；The grid Pg25 of the 25th PMOS connects Pd21,
Drain electrode Pd25 connects the source electrode Ps26, source electrode Ps25 of the 26th PMOS and connects power vd D；
The grid Pg26 of the 26th PMOS connects cn2, drain electrode Pd26 and connects the 25th NMOS
Drain electrode Nd25 and Pd20 of pipe, source electrode Ps26 connect Pd25；The grid Ng9 of the 9th NMOS tube
Connect cn1, drain electrode Nd9 to connect Pd14, source electrode Ns9 and connect the drain electrode Nd10 of the tenth NMOS tube；
The grid Ng10 of the tenth NMOS tube connects SE, drain electrode Nd10 and connects Ns9, source electrode Ns10 and connect
The drain electrode Nd11 of the 11st NMOS tube；The grid Ng11 of the 11st NMOS tube connects SI, drain electrode
Nd11 connects Ns10, source electrode Ns11 ground connection VSS；The grid Ng12 of the 12nd NMOS tube connects
D, drain electrode Nd12 connect Ns9, source electrode Ns12 and connect the drain electrode Nd13 of the 13rd NMOS tube；The
The grid Ng13 of 13 NMOS tube connects SEN, drain electrode Nd13 and connects Ns12, source electrode Ns13 even
Meet the drain electrode Nd14 of the 14th NMOS tube；The grid Ng14 of the 14th NMOS tube connects RN2,
Drain electrode Nd14 connects Ns13, source electrode Ns14 ground connection VSS；The grid Ng15 of the 15th NMOS tube
Connect cn2, drain electrode Nd15 to connect Pd20, source electrode Ns15 and connect the drain electrode Nd16 of the 16th NMOS tube；
The grid Ng16 of the 16th NMOS tube connects SE, drain electrode Nd16 and connects Ns15, source electrode Ns16
Connect the drain electrode Nd17 of the 17th NMOS tube；The grid Ng17 of the 17th NMOS tube connects SI,
Drain electrode Nd17 connects Ns16, source electrode Ns17 ground connection VSS；The grid Ng18 of the 18th NMOS tube
Connect D1, drain electrode Nd18 to connect Ns15, source electrode Ns18 and connect the drain electrode Nd19 of the 19th NMOS tube；
The grid Ng19 of the 19th NMOS tube connects SEN, drain electrode Nd19 and connects Ns18, source electrode Ns19
Connect the drain electrode Nd20 of the 20th NMOS tube；The grid Ng20 of the 20th NMOS tube connects RN2,
Drain electrode Nd20 connects Ns19, source electrode Ns20 ground connection VSS；The grid Ng21 of the 21st NMOS tube
Connect Pd20, drain electrode Nd21 and connect Pd21, source electrode Ns21 ground connection VSS；22nd NMOS
The grid Ng22 of pipe connects Pd14, drain electrode Nd22 and connects Pd22, source electrode Ns22 ground connection VSS；The
The grid Ng23 of 23 NMOS tube connects c1, drain electrode Nd23 and connects Pd24, source electrode Ns23 even
Meet the drain electrode Nd24 of the 24th NMOS tube；The grid Ng24 of the 24th NMOS tube connects
Pd21, drain electrode Nd24 connect Ns23, source electrode Ns24 ground connection VSS；The grid of the 25th NMOS tube
Pole Ng25 connects c2, drain electrode Nd25 and connects Pd26, source electrode Ns25 and connect the 26th NMOS tube
Drain electrode Nd26；The grid Ng26 of the 26th NMOS tube connects Pd22, drain electrode Nd26 and connects
Ns25, source electrode Ns26 ground connection VSS；9th PMOS, the tenth PMOS, the 11st PMOS
Manage and in the tenth NMOS tube, the 11st NMOS tube, the 13rd NMOS tube composition main latch
Scan Architecture；Synchronization in 13rd PMOS and the 14th NMOS tube composition main latch is multiple
Bit architecture；Six inputs and two outfans are had from latch, input and c1, c2, cn1, cn2,
M1, m1r are connected, and outfan is s0, s0r；From latch by ten PMOS and ten NMOS tube
Composition, from latch, the substrate of all PMOS connects power vd D, the lining of all NMOS tube
End ground connection VSS；The grid Pg21 of the 21st PMOS connects m1r, drain electrode Pd21 and connects second
The source electrode Ps22 of 12 PMOS, source electrode Ps21 connect power vd D；22nd PMOS
Grid Pg22 connect cn1, drain electrode Pd22 connect the 21st NMOS tube drain electrode Nd21, source
Pole connects Pd21；The grid Pg23 of the 23rd PMOS connects m1, drain electrode Pd23 and connects second
The source electrode Ps24 of 14 PMOS, source electrode Ps23 connect power vd D；24th PMOS
Grid Pg24 connect cn2, drain electrode Pd24 connect the 23rd NMOS tube drain electrode Nd23, source
Pole connects Pd23；The grid Pg25 of the 25th PMOS connects Pd22, drain electrode Pd25 and connects the
The drain electrode Nd25 of 25 NMOS tube, source electrode Ps25 connect power vd D；26th PMOS
The grid Pg26 of pipe connects Pd24, drain electrode Pd26 and connects the drain electrode Nd26 of the 26th NMOS tube,
Source electrode Ps26 connects power vd D；The grid Pg27 of the 27th PMOS connects Pd26, drain electrode
Pd27 connects the source electrode Ps28, source electrode Ps27 of the 28th PMOS and connects power vd D；Second
The grid Pg28 of 18 PMOS connects c1, drain electrode Pd28 and connects the leakage of the 27th NMOS tube
Pole Nd27 also connects Pd27 as from latch outfan s0, source electrode Ps28；29th
The grid Pg29 of PMOS connects Pd25, drain electrode Pd29 and connects the source electrode Ps30 of the 30th PMOS,
Source electrode Ps29 connects power vd D；The grid Pg30 of the 30th PMOS connects c2, and drain Pd30
Connect the drain electrode Nd29 of the 29th NMOS tube and as from another outfan s0r of latch,
Source electrode Ps30 connects Pd29；The grid Ng21 of the 21st NMOS tube connects c, and drain Nd21
Connect Pd22, source electrode Ns21 and connect the drain electrode Nd22 of the 22nd NMOS tube；22nd NMOS
The grid Ng22 of pipe connects m1, drain electrode Nd22 and connects Ns21, source electrode Ns22 ground connection VSS；Second
The grid Ng23 of 13 NMOS tube connects c2, drain electrode Nd23 and connects Pd24, source electrode Ns23 and connect
The drain electrode Nd24 of the 24th NMOS tube；The grid Ng24 of the 24th NMOS tube connects m1r,
Drain electrode Nd24 connects Ns23, source electrode Ns24 ground connection VSS；The grid Ng25 of the 25th NMOS tube
Connect Pd24, drain electrode Nd25 and connect Pd25, source electrode Ns25 ground connection VSS；26th NMOS
The grid Ng26 of pipe connects Pd22, drain electrode Nd26 and connects Pd26, source electrode Ns26 ground connection VSS；The
The grid Ng27 of 27 NMOS tube connects cn1, drain electrode Nd27 and connects Pd28, source electrode Ns27
Connect the drain electrode Nd28 of the 28th NMOS tube；The grid Ng28 of the 28th NMOS tube connects
Pd25, drain electrode Nd28 connect Ns27, source electrode Ns28 ground connection VSS；The grid of the 29th NMOS tube
Pole Ng29 connects cn2, drain electrode Nd29 and connects Pd30, source electrode Ns29 and connect the 30th NMOS tube
Drain electrode Nd30；The grid Ng30 of the 30th NMOS tube connects Pd26, drain electrode Nd30 and connects Ns29,
Source electrode Ns30 ground connection VSS；
Described have six inputs and two outfans from latch, and input is c1, c2, cn1, cn2,
M1, m1r；Outfan is s1, s1r；From latch by ten PMOS and ten NMOS tube groups
Becoming, from latch, the substrate of all PMOS connects power vd D, the substrate of all NMOS tube
Ground connection VSS；The grid Pg27 of the 27th PMOS connects m1r, drain electrode Pd27 and connects the 20th
The source electrode Ps28 of eight PMOS, source electrode Ps27 connect power vd D；28th PMOS
Grid Pg28 connects cn1, drain electrode Pd28 and connects the drain electrode Nd27 of the 27th NMOS tube, source electrode
Ps28 connects Pd27；The grid Pg29 of the 29th PMOS connects m1, drain electrode Pd29 and connects
The source electrode Ps30 of the 30th PMOS, source electrode Ps29 connect power vd D；30th PMOS
Grid Pg30 connect cn2, drain electrode Pd30 connect the 29th NMOS tube drain electrode Nd29, source
Pole Ps30 connects Pd29；The grid Pg31 of the 31st PMOS connects Pd28, and drain Pd31
Connect the drain electrode Nd31 of the 31st NMOS tube, source electrode Ps31 and connect power vd D；32nd
The grid Pg32 of PMOS connects Pd30, drain electrode Pd32 and connects the drain electrode of the 32nd NMOS tube
Nd32, source electrode Ps32 connect power vd D；The grid Pg33 of the 33rd PMOS connects Pd32,
Drain electrode Pd33 connects the source electrode Ps34, source electrode Ps33 of the 34th PMOS and connects power vd D；
The grid Pg34 of the 34th PMOS connects c1, drain electrode Pd34 and connects the 33rd NMOS tube
Drain electrode Nd33 and Pd28, and connect Pd33 as from latch outfan s1, source electrode Ps34；
The grid Pg35 of the 35th PMOS connects Pd31, drain electrode Pd35 and connects the 36th PMOS
The source electrode Ps36 of pipe, source electrode Ps35 connect power vd D；The grid Pg36 of the 36th PMOS
Connect c2, drain electrode Pd36 connect the 35th NMOS tube drain electrode Nd35 and Pd30 and as from
One outfan s1r, source electrode Ps36 of latch connect Pd35；The grid of the 27th NMOS tube
Ng27 connects c, drain electrode Nd27 and connects Pd28, source electrode Ns27 and connect the leakage of the 28th NMOS tube
Pole Nd28；The grid Ng28 of the 28th NMOS tube connects m1, drain electrode Nd28 and connects Ns27,
Source electrode Ns28 ground connection VSS；The grid Ng29 of the 29th NMOS tube connects c2, and drain Nd29
Connect Pd30, source electrode Ns29 and connect the drain electrode Nd30 of the 30th NMOS tube；30th NMOS tube
Grid Ng30 connect m1r, drain electrode Nd30 connect Ns29, source electrode Ns30 ground connection VSS；3rd
The grid Ng31 of 11 NMOS tube connects Pd30, and drain electrode Nd31 connection Pd31, source electrode Ns31 connect
Ground VSS；The grid Ng32 of the 32nd NMOS tube connects Pd28, drain electrode Nd32 and connects Pd32,
Source electrode Ns32 ground connection VSS；The grid Ng33 of the 33rd NMOS tube connects cn1, and drain Nd33
Connect Pd34, source electrode Ns33 and connect the drain electrode Nd34 of the 34th NMOS tube；34th NMOS
The grid Ng34 of pipe connects Pd31, drain electrode Nd34 and connects Ns33, source electrode Ns34 ground connection VSS；The
The grid Ng35 of 35 NMOS tube connects cn2, drain electrode Nd35 and connects Pd36, source electrode Ns35
Connect the drain electrode Nd36 of the 32nd NMOS tube；The grid Ng36 of the 36th NMOS tube connects
Pd32, drain electrode Nd36 connect Ns35, source electrode Ns36 ground connection VSS；
Described inverter circuit has two inputs and an outfan, and input connects s1 and s1r, defeated
Going out end is Q；Inverter circuit is made up of the 48th PMOS and the 48th NMOS tube；The
The substrate of 48 PMOS and source electrode Ps48 are all connected with power vd D, the 48th NMOS tube
Substrate and source electrode Ns48 equal ground connection VSS；The grid Pg48 of the 48th PMOS connects input
S1, drain electrode Pd48 connect the drain electrode Nd48 of the 48th NMOS tube, and as inverter circuit
Outfan Q, source electrode Ps48 meet power vd D；The grid Ng48 of the 48th NMOS tube connects input
End s1r, drain electrode Nd48 connect Pd48, source electrode Ns48 ground connection VSS.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101447786B (en) * | 2008-12-29 | 2010-11-10 | 北京时代民芯科技有限公司 | Buffer cell circuit for resisting single-particle transient state |
| CN102394602A (en) * | 2011-10-21 | 2012-03-28 | 中国人民解放军国防科学技术大学 | Single event upset-resisting scanning structure D trigger capable of setting and resetting |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2004072426A (en) * | 2002-08-06 | 2004-03-04 | Renesas Technology Corp | Master slave flip flop circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101447786B (en) * | 2008-12-29 | 2010-11-10 | 北京时代民芯科技有限公司 | Buffer cell circuit for resisting single-particle transient state |
| CN102394602A (en) * | 2011-10-21 | 2012-03-28 | 中国人民解放军国防科学技术大学 | Single event upset-resisting scanning structure D trigger capable of setting and resetting |
Non-Patent Citations (1)
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| 标准单元抗单粒子瞬态效应版图加固技术与验证方法研究;刘真;《中国优秀硕士学位论文全文数据库》;20120731;第40页至第42页 * |
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