CN106712743A - Synchronous reset D trigger for preventing single event upset - Google Patents
Synchronous reset D trigger for preventing single event upset Download PDFInfo
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- CN106712743A CN106712743A CN201710020100.4A CN201710020100A CN106712743A CN 106712743 A CN106712743 A CN 106712743A CN 201710020100 A CN201710020100 A CN 201710020100A CN 106712743 A CN106712743 A CN 106712743A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
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Abstract
The invention is suitable for the technical field of D triggers, and provides a synchronous reset D trigger for preventing single event upset. The D trigger comprises: a clock signal input circuit, a reset signal input circuit, a master latch buffer circuit, a slave latch buffer circuit, a master latch and a slave latch, and both of the master latch and slave latch are dual mode redundancy reinforcement latches. Compared with the prior art, in the synchronous reset D trigger provided by the invention, the buffer circuits are added in front of the master latch and slave latch, so the single event upset ability of the synchronous reset D trigger is improved, dual mode redundancy reinforcement is carried out on the master latch and slave latch, namely the master latch and slave latch are separated to a pull up PMOS tube and a pull down PMOS tube in a C2MOS circuit, which are redundant to each other, therefore a possible feedback circuit caused by single event transient pulses is avoided, the C2MOS circuits in the circuits of the master latch and slave latch are improved, clock signals control the circuits through SMOS transmission rates, and the single event upset ability of the synchronous reset D trigger is further improved.
Description
Technical field
The invention belongs to d type flip flop technical field, more particularly to a kind of primary particle inversion resistant synchronous reset d type flip flop.
Background technology
There are a large amount of high energy particles (proton, electronics, heavy ion etc.) in cosmic space, the sequence circuit in integrated circuit is received
To after these high-energy particle bombardments, its state for keeping is likely to occur upset, and this effect is referred to as Single event upset effecf, simple grain
LET (linear energy transfer) value of son bombardment integrated circuit is higher, easier generation Single event upset effecf.In integrated circuit
After combinational circuit is subject to these high-energy particle bombardments, it is possible to produce transient electrical pulses, this effect is referred to as single-ion transient state effect,
The LET values of single-particle bombardment integrated circuit are higher, and the transient electrical pulses duration of generation is more long, and electric pulse is easier by sequential
Circuit is gathered.The upset if state of sequence circuit makes a mistake, or the transient electrical pulses quilt that single-ion transient state effect is produced
Sequence circuit mistake is gathered, and can all be caused integrated circuit operation unstable or even be produced fatal mistake, and this is in space flight, military neck
Domain is particularly acute.Therefore, reinforced more next so as to reduce Single event upset effecf and single-ion transient state effect to integrated circuit
It is more important.
D type flip flop is that one of most timing unit structure is used in integrated circuit, and its resistance to single-particle inversion is determined
The ability of whole integrated circuit anti-single particle is determined., it is necessary to the state of d type flip flop is controllable in some integrated circuits, than
If forcing d type flip flop input low level.Increase synchronous reset signal input on the architecture basics of existing d type flip flop
With synchronous reset circuit, it is possible to achieve the synchronous reset structure of d type flip flop, d type flip flop can be controlled by synchronous reset signal
Synchronous reset function, but it is this can synchronous reset d type flip flop anti-single particle upset ability it is poor, be not suitable for being applied to highly reliable
The IC chip of property.
The content of the invention
The embodiment of the invention provides a kind of primary particle inversion resistant synchronous reset d type flip flop, it is intended to solve prior art
Middle synchronous reset d type flip flop anti-single particle upset ability problem not high.
The embodiment of the invention provides a kind of primary particle inversion resistant synchronous reset d type flip flop, the synchronous reset D triggerings
Device includes：
Clock signal input circuit, reset signal input circuit, main latch buffer circuit, from latch buffer circuit,
Main latch and from latch, the main latch and the latch that duplication redundancy reinforcing is from latch；
The synchronous reset d type flip flop has three inputs and two output ends, and three inputs are respectively clock
Signal input part CLK, reset signal input R and data signal input D, two output ends are respectively the first output end
Q and the second output end QN；
The clock signal input circuit respectively with the clock signal input terminal CLK, the reset signal input circuit,
The main latch and it is described from latch connection；
The reset signal input circuit also respectively with the reset signal input R, the main latch and it is described from
Latch is connected；
The main latch buffer circuit is connected with the data signal input D, the main latch respectively；
It is described from latch buffer circuit respectively with the main latch, described be connected from latch；
It is described to be also connected with the first output end Q and the second output end QN from latch.
Knowable to the embodiments of the present invention, compared to prior art, the present invention is by main latch and from latch
Preceding increase buffer circuit, improves the anti-single particle upset ability of synchronous reset d type flip flop, enters to main latch and from latch
Row duplication redundancy is reinforced, that is, be separated into the C being mutually redundant2Pull-up PMOS and pull-down NMOS pipe in MOS circuits, it is to avoid from
May be by backfeed loop caused by single event transient pulse, to main latch and the C from latch circuit in latch2MOS electricity
Road is improved, and control of the clock signal to circuit is realized by cmos transmission gate, further increases synchronous reset D triggerings
The anti-single particle upset ability of device.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those skilled in the art, without having to pay creative labor, can be with root
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is the electrical block diagram of the C cell circuit based on DICE structures of the prior art；
Fig. 2 is the structural representation of the primary particle inversion resistant synchronous reset d type flip flop that first embodiment of the invention is provided；
Fig. 3 be first embodiment of the invention provide primary particle inversion resistant synchronous reset d type flip flop in clock signal it is defeated
Enter the electrical block diagram of circuit；
Fig. 4 be first embodiment of the invention provide primary particle inversion resistant synchronous reset d type flip flop in reset signal it is defeated
Enter the electrical block diagram of circuit；
Fig. 5 be first embodiment of the invention provide primary particle inversion resistant synchronous reset d type flip flop in main latch delay
Rush the electrical block diagram of circuit；
Fig. 6 is main latch in the primary particle inversion resistant synchronous reset d type flip flop that first embodiment of the invention is provided
Electrical block diagram；
Fig. 7 is slow from latch in the primary particle inversion resistant synchronous reset d type flip flop that first embodiment of the invention is provided
Rush the electrical block diagram of circuit；
Fig. 8 is from latch in the primary particle inversion resistant synchronous reset d type flip flop that first embodiment of the invention is provided
Electrical block diagram.
Specific embodiment
To enable goal of the invention, feature, the advantage of the embodiment of the present invention more obvious and understandable, below in conjunction with
Accompanying drawing in the embodiment of the present invention, is clearly and completely described, it is clear that retouched to the technical scheme in the embodiment of the present invention
The embodiment stated is only a part of embodiment of the invention, and not all embodiments.Based on the embodiment in the present invention, this area
The every other embodiment that technical staff is obtained under the premise of creative work is not made, belongs to the model of present invention protection
Enclose.
Fig. 1 is referred to, Fig. 1 is the electrical block diagram of the C cell circuit based on DICE structures, DICE structures should be based on
C cell circuit include：
First signal input part IN1, secondary signal input IN2, signal output part OUT, P-channel metal-oxide-semiconductor MP1, P-channel
Metal-oxide-semiconductor MP2, N-channel MOS pipe MN1, N-channel MOS pipe MN2.The substrate of MP1 and MP2 connects power vd D (not shown)s, MN1
With the Substrate ground (not shown) of MN2.
Wherein, the grid of MP1 meets the first signal input part IN1, and source electrode meets power vd D, and drain electrode connects the source electrode of MP2；MP2's
Grid meets secondary signal input IN2, and drain electrode meets signal output part OUT；The grid of MN1 meets the first signal input part IN1, source electrode
The drain electrode of MN2 is connect, drain electrode meets signal output part OUT；The grid of MN2 meets secondary signal input IN2, source ground.
(all it is 0 when the first signal input part IN1 of C cell circuit is identical with the logical value of secondary signal input IN2
Or all for 1), signal output part OUT provides the logic opposite with the first signal input part IN1 and secondary signal input IN2
Value, now C cell circuit shows as phase inverter；When the first signal input part IN1 and secondary signal input IN2 logical value not
Simultaneously (one another for 0 be 1), signal output part OUT enters hold mode, there is provided the logical value under state before.Cause
This, C cell can be used to the logic upset of masked nodes, it is to avoid the first signal input part IN1's or secondary signal input IN2
The upset of transient state logic has influence on output end OUT.
Fig. 2 is referred to, the primary particle inversion resistant synchronous reset d type flip flop that Fig. 2 is provided for first embodiment of the invention
Structural representation, the synchronous reset d type flip flop includes：
Clock signal input circuit 1, reset signal input circuit 2, main latch buffer circuit 3, from latch buffer electricity
Road 4, main latch 5 and from latch 6, main latch 5 and from latch 6 be duplication redundancy reinforcing latch.
The synchronous reset d type flip flop has three inputs and two output ends, and it is defeated that three inputs are respectively clock signal
Enter to hold CLK, reset signal input R and data signal input D, two output ends are respectively the first output end Q and second defeated
Go out to hold QN.Wherein, the clock signal of clock signal input terminal CLK inputs is CLK0, the reset letter of reset signal input R inputs
Number be R0, data signal input D input data-signal be D0.
Clock signal input circuit respectively with clock signal input terminal CLK, reset signal input circuit, main latch and from
Latch is connected；Reset signal input circuit is also connected with reset signal input R, main latch and from latch respectively；It is main
Latch buffer circuit is connected with data signal input D, main latch respectively；From latch buffer circuit respectively with main latch
Device, from latch connection；Also it is connected with the first output end Q and the second output end QN from latch.
Fig. 3 is referred to, in the primary particle inversion resistant synchronous reset d type flip flop that Fig. 3 is provided for first embodiment of the invention
The electrical block diagram of clock signal input circuit, the clock signal input circuit includes：
One input and an output end, an input is clock signal input terminal CLK, and an output end is
CLK1。
The clock signal input circuit is made up of the first PMOS, the second PMOS, the first NMOS tube and the second NMOS tube.
First PMOS, the substrate of the second PMOS connect power vd D (not shown)s, the first NMOS tube, the 2nd NMOS
The Substrate ground (not shown) of pipe.
Grid Pg1 connections the clock signal input terminal CLK, source electrode Ps1 of the first PMOS meet power vd D, drain electrode Pd1 connections
The source electrode Ps2 of the second PMOS；The grid Pg2 connection clock signal input terminal CLK of the second PMOS, drain electrode Pd2 connections CLK1；
Grid Ng1 connections the clock signal input terminal CLK, source electrode Ns1 of the first NMOS tube connect the drain electrode Nd2 of the second NMOS tube, drain electrode
Nd1 connects CLK1；Grid Ng2 connection clock signal input terminal CLK, source electrode the Ns2 ground connection of the second NMOS tube.
Wherein, the first PMOS, the second PMOS, the first NMOS tube and the second NMOS tube constitute a circuit for C cell.
The characteristic of the circuit is, when the logical value of the first PMOS, the input signal of the second PMOS grid is identical, or, when
When one NMOS tube, the logical value of the input signal of the second NMOS tube grid are identical, output end is exported and input signal logical value phase
Anti- output signal；And when the first PMOS, the logical value of the input signal of the second PMOS grid are different, or, when first
When NMOS tube, the logical value of the input signal of the second NMOS tube grid are different, the logical value of output signal is by the shape before holding
State does not change.This C cell structure can ensure the input of the output signal CLK01 and input CLK of output end CLK1
The logic state of signal CLK0 is not always conversely, and influenceed by single particle effect.
Fig. 4 is referred to, in the primary particle inversion resistant synchronous reset d type flip flop that Fig. 4 is provided for first embodiment of the invention
The electrical block diagram of reset signal input circuit, the reset signal input circuit includes：
One input and an output end, an input are reset signal input R, and an output end is R1.
The reset signal input circuit is made up of the 3rd PMOS, the 4th PMOS, the 3rd NMOS tube and the 4th NMOS tube.
3rd PMOS, the substrate of the 4th PMOS connect power vd D (not shown)s, the 3rd NMOS tube, the 4th NMOS
The Substrate ground (not shown) of pipe.
Grid Pg3 connections the reset signal input R, source electrode Ps3 of the 3rd PMOS meet power vd D, drain electrode Pd3 connections the
The source electrode Ps4 of four PMOSs；The grid Pg4 connection reset signal input R of the 4th PMOS, drain electrode Pd4 connections R1；3rd
Grid Ng3 connection reset signals the input R, source electrode Ns3 of NMOS tube connect the drain electrode Nd4 of the 4th NMOS tube, drain electrode Nd3 connections
R1；Grid Ng4 connection reset signal input R, source electrode the Ns4 ground connection of the 4th NMOS tube.
Wherein, the 3rd PMOS, the 4th PMOS, the 3rd NMOS tube and the 4th NMOS tube constitute a circuit for C cell.
The characteristic of the circuit is, when the 3rd PMOS, the logical value of the input signal of the 4th PMOS grid are identical, or, when
When three NMOS tubes, the logical value of the input signal of the 4th NMOS tube grid are identical, output end is exported and input signal logical value phase
Anti- output signal；And when the 3rd PMOS, the logical value of the input signal of the 4th PMOS grid are different, or, when the 3rd
When NMOS tube, the logical value of the input signal of the 4th NMOS tube grid are different, the logical value of output signal is by the shape before holding
State does not change.So ensure that the logic shape of the input signal R0 of the output signal R01 and input R of output end R1
State is always conversely, the reset signal that input therefore can be effectively prevented from occurs output signal when logic state overturns follows generation
Single-particle inversion.
Fig. 5 is referred to, in the primary particle inversion resistant synchronous reset d type flip flop that Fig. 5 is provided for first embodiment of the invention
The electrical block diagram of main latch buffer circuit, the main latch buffer circuit includes：
One input and two output ends, an input is data signal input D, and two output ends are respectively D1
And D2.
The main latch buffer circuit is by the 5th PMOS, the 6th PMOS, the 7th PMOS, the 8th PMOS, the 9th
PMOS, the tenth PMOS, the 11st PMOS, the 12nd PMOS, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube,
8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube, the 11st NMOS tube, the 12nd NMOS tube composition.
Wherein, the 5th PMOS, the 6th PMOS, the 7th PMOS, the 8th PMOS, the 9th PMOS, the tenth PMOS
Pipe, the 11st PMOS, the substrate of the 12nd PMOS connect power vd D (not shown)s, the 5th NMOS tube, the 6th NMOS
Pipe, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube, the 11st NMOS tube, the lining of the 12nd NMOS tube
Bottom is grounded (not shown).
Grid Pg5 connections the data signal input D, source electrode Ps5 of the 5th PMOS meet power vd D, and drain electrode Pd5 connects respectively
Meet grid Pg6, the drain electrode Nd5 of the 5th NMOS tube, the grid Ng6 of the 6th NMOS tube of the 6th PMOS；The grid of the 5th NMOS tube
Pole Ng5 connects data signal input D, source electrode Ns5 ground connection；The source electrode Ps6 of the 6th PMOS meets power vd D, drain electrode Pd6 difference
Connect grid Pg7, the drain electrode Nd6 of the 6th NMOS tube, the grid Ng7 of the 7th NMOS tube of the 7th PMOS；6th NMOS tube source
Pole Ns6 is grounded；The source electrode Ps7 of the 7th PMOS meets power vd D, and drain electrode Pd7 connects the grid Pg8 of the 8th PMOS, the respectively
The drain electrode Nd7 of seven NMOS tubes, the grid Ng8 of the 8th NMOS tube；7th NMOS tube source electrode Ns7 is grounded；The source electrode of the 8th PMOS
Ps8 meets power vd D, and drain electrode Pd8 connects the drain electrode Nd8 and D1 of the 8th NMOS tube respectively；The source electrode Ns8 ground connection of the 8th NMOS tube.
Grid Pg9 connections the data signal input D, source electrode Ps9 of the 9th PMOS meet power vd D, and drain electrode Pd9 connects respectively
Meet grid Pg10, the drain electrode Nd9 of the 9th NMOS tube, the grid Ng12 of the 12nd NMOS tube of the tenth PMOS；9th NMOS tube
Grid Ng9 connect drain electrode Pd10, the grid Pg11 of the 11st PMOS, the drain electrode of the tenth NMOS tube of the tenth PMOS respectively
Nd10, source electrode Ns9 are grounded；The source electrode Ps10 of the tenth PMOS meets power vd D；The grid Ng10 of the tenth NMOS tube connects respectively
The drain electrode Pd11 of 11 PMOSs, the grid Pg12 of the 12nd PMOS, the drain electrode Nd11 of the 11st NMOS tube, source electrode Ns10 connect
Ground；The source electrode Ps11 of the 11st PMOS meets power vd D；The grid Ng11 of the 11st NMOS tube connects the 12nd PMOS respectively
Drain electrode Pd12, the drain electrode Nd12 of the 12nd NMOS tube, data signal input D and D2, source electrode Ns11 ground connection；12nd PMOS
The source electrode Ps12 of pipe meets power vd D；The source electrode Ns12 ground connection of the 12nd NMOS tube.
The 9th PMOS, the tenth PMOS, the 11st PMOS, the 12nd PMOS in the main latch buffer circuit
The DICE units constituted with the 9th NMOS tube, the tenth NMOS tube, the 11st NMOS tube, the 12nd NMOS tube reversely constitute feedback
Ring, forms 4 phase inverter cascades of interlocking, there is 4 storage knots with phase inverter for connecting back-to-back in this cellular construction
Point：N0, n1, n2, n3, can store two pairs of data of complementation, and wherein n0 and n2, n1 and n3 is logic state identical node.
From unlike traditional interlock circuit, the grid of PMOS and NMOS tube in the cellular construction per one-level is respectively by previous stage
Output signal with rear stage is triggered.Therefore, the state of each storage node receives its adjacent storage node in the cellular construction
State control, and adjacent storage node is mutually independent.When the voltage of only one of which storage node in circuit occurs
During change, due to the feedback influence by other nodes, the storage state of each storage node will not change in DICE units.
The 5th PMOS, the 6th PMOS, the 7th PMOS, the 8th PMOS and the 5th NMOS in the main latch buffer circuit
Pipe, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube separately constitute four phase inverters, and constitute delay circuit two-by-two.Cause
This, the logic of the signal D01 that the input signal D0 of data signal input D is obtained after being buffered through DICE units at output end D2
State should be with input signal D0 by being obtained at output end D1 after phase inverter time delay signal D0 logic state it is consistent, and tool
There is anti-single particle effect.
Fig. 6 is referred to, in the primary particle inversion resistant synchronous reset d type flip flop that Fig. 6 is provided for first embodiment of the invention
The electrical block diagram of main latch, the main latch includes：
12 inputs and an output end, wherein, four inputs are connected with clock signal input terminal CLK respectively,
Four inputs are connected with CLK1 respectively, and two inputs are connected with R1 respectively, and an input is connected with D1, an input
It is connected with D2；One output end is D3.
The main latch is by the 13rd PMOS, the 14th PMOS, the 15th PMOS, the 16th PMOS, the tenth
Seven PMOSs, the 18th PMOS, the 19th PMOS, the 20th PMOS, the 21st PMOS, the 22nd PMOS
Pipe, the 23rd PMOS, the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube, the 16th NMOS tube, the 17th
NMOS tube, the 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube, the 21st NMOS tube, the 22nd NMOS tube,
23rd NMOS tube, the 24th NMOS tube, the 25th NMOS tube composition.
Wherein, the 13rd PMOS, the 14th PMOS, the 15th PMOS, the 16th PMOS, the 17th PMOS
Pipe, the 18th PMOS, the 19th PMOS, the 20th PMOS, the 21st PMOS, the 22nd PMOS, second
The substrate of 13 PMOSs connects power vd D (not shown)s, the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube,
16th NMOS tube, the 17th NMOS tube, the 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube, the 21st NMOS
The Substrate ground (in figure of pipe, the 22nd NMOS tube, the 23rd NMOS tube, the 24th NMOS tube, the 25th NMOS tube
It is not shown).
Grid Ng13 the connections CLK, source electrode Ns13 of the 13rd NMOS tube connect the source electrode Ps13 of the 13rd PMOS respectively
And D1, drain electrode Nd13 connect drain electrode Pd13, the source electrode Ns16 of the 16th NMOS tube, the 16th PMOS of the 13rd PMOS respectively
The source electrode Ps16 of pipe, the grid Ng17 of the 17th NMOS tube, the grid Pg18 of the 18th PMOS, the grid of the 19th NMOS tube
The grid Pg20 of Ng19, the 20th PMOS；The grid Pg13 connections CLK1 of the 13rd PMOS；The grid of the 14th NMOS tube
Ng14 connects CLK, and source electrode Ns14 connects the source electrode Ps14 and D2 of the 14th PMOS respectively, and drain electrode Nd14 connects the 14th respectively
The drain electrode Pd14 of PMOS, the source electrode Ns15 of the 15th NMOS tube, the source electrode Ps15 of the 15th PMOS, the 17th PMOS
Grid Pg17, the grid Ng18 of the 18th NMOS tube, the grid Pg19 of the 19th PMOS, the grid of the 20th NMOS tube
Ng20；The grid Pg14 connections CLK1 of the 14th PMOS.
Grid Ng15 the connection CLK1, drain electrode Nd15 of the 15th NMOS tube connect the drain electrode of the 15th PMOS respectively
Pd15, the drain electrode Pd21 of the 21st PMOS, the drain electrode Nd21 of the 21st NMOS tube, the drain electrode of the 23rd NMOS tube
Nd23；The grid Pg15 connections CLK of the 15th PMOS；The grid Ng16 connection CLK1 of the 16th NMOS tube, Nd16 points of drain electrode
Not Lian Jie the 16th PMOS drain electrode Pd16, the drain electrode Pd22 of the 22nd PMOS, the drain electrode of the 22nd NMOS tube
The drain electrode Nd24 of Nd22, the 24th NMOS tube；The grid Pg16 connections CLK of the 16th PMOS.
The source electrode Ps17 of the 17th PMOS meets power vd D, and drain electrode Pd17 connects the source electrode Ps18 of the 18th PMOS；The
The drain electrode Pd18 of 18 PMOSs connect respectively the drain electrode Nd17 of the 17th NMOS tube, the grid Ng21 of the 21st NMOS tube,
The grid Pg22 of the 22nd PMOS, the grid Pg23 of the 23rd PMOS, the grid Ng25 of the 25th NMOS tube；The
The source electrode Ns17 of 17 NMOS tubes connects the drain electrode Nd18 of the 18th NMOS tube；The source electrode Ns18 ground connection of the 18th NMOS tube；The
The source electrode Ps19 of 19 PMOSs meets power vd D, and drain electrode Pd19 connects the source electrode Ps20 of the 20th PMOS；20th PMOS
Drain electrode Pd20 connect drain electrode Nd19, grid Pg21, the 22nd of the 21st PMOS of the 19th NMOS tube respectively
The grid Ng22 of NMOS tube；The source electrode Ns19 of the 19th NMOS tube connects the drain electrode Nd20 of the 20th NMOS tube；20th NMOS
The source electrode Ns20 ground connection of pipe.
The source electrode Ps21 of the 21st PMOS meets power vd D；The source electrode Ns21 ground connection of the 21st NMOS tube；20th
The source electrode Ps22 of two PMOSs meets power vd D；The source electrode Ns22 ground connection of the 22nd NMOS tube；The grid of the 23rd NMOS tube
Ng23 connects R1, source electrode Ns23 ground connection；Grid Ng24 connection R1, source electrode the Ns24 ground connection of the 24th NMOS tube；23rd
The source electrode Ps23 of PMOS meets power vd D, and drain electrode Pd23 connects the drain electrode Nd25 and D3 of the 25th NMOS tube respectively；20th
The source electrode Ns25 ground connection of five NMOS tubes.
The main latch is made up of the DICE structural circuits of dual redundant.13rd PMOS and the 13rd NMOS tube structure in figure
The second transmission gate, the 15th PMOS and the 15th are constituted into the first transmission gate, the 14th PMOS and the 14th NMOS tube
NMOS tube constitutes the 3rd transmission gate, the 16th PMOS and constitutes the 4th transmission gate with the 16th NMOS tube, and this four transmission gates are equal
By clock signal control, wherein first, second transmission gate cut-off state and the three, the 4th transmission gates to cut-off state opposite.
When the logical value of the signal CLK0 of CLK ports input is 1, the logical value of the signal CLK01 of CLK1 ports input
It is 0, and first, second transmission gate conducting, the shut-off of the three, the 4th transmission gates.D1 ports connect respectively by the first transmission gate
The grid Ng17 of the 17 NMOS tubes and grid Pg18 of the 18th PMOS, D2 ports connect the tenth respectively by the second transmission gate
The grid Pg17 of the seven PMOSs and grid Ng18 of the 18th NMOS tube.17th PMOS, the 18th PMOS, the 17th
NMOS tube, the 18th NMOS tube collectively form a C cell circuit based on DICE structures.Due to foregoing to " anti-single particle
In the explanation of main latch buffer circuit in the synchronous reset d type flip flop of upset ", the D0 signals and D2 of D1 ports input are described
The logic state of the D01 signals of port input is consistent, therefore the C cell circuit, equivalent to a phase inverter, signal passes through
A nodes output in figure, is connected to the phase inverter that the 23rd PMOS and the 25th NMOS tube are constituted, and by the main lock
The output end D3 output signals D02 of storage.Due to the presence of C cell circuit, patrolling for input signal D0 and D01 can be effectively prevented from
Collect upset and propagate to output end, now, the logic state of the output signal D02 of D3 outputs should be consistent with D0 and D01.
When the logical value of the signal CLK0 of CLK ports input is 0, the logical value of the signal CLK01 of CLK1 ports input
It is 1, and first, second transmission gate is turned off, the three, the 4th transmission gate conductings.Now, the logic state of a, b node is by by the tenth
Seven PMOSs, the 18th PMOS, the 19th PMOS, the 20th PMOS, the 21st PMOS, the 22nd PMOS
Pipe, the 17th NMOS tube, the 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube, the 21st NMOS tube, the 20th
The feedback control loop that two NMOS tubes are constituted is latched, and node a is identical with the logic state of node b, the logic shape of node c and node d
State is identical, and the logic state of node a and node c is conversely, the logic state of the output signal D02 of output end D3 keeps constant.It is brilliant
The PMOS of body pipe the 17th, the 18th PMOS, the 17th NMOS tube, the 18th NMOS tube and the 19th PMOS, the 20th
PMOS, the 19th NMOS tube, the 20th NMOS tube, two C cell circuits are respectively constituted, can be effectively prevented from feedback control loop
The logic upset that node occurs travels to output end, it is ensured that circuit has good anti-single particle ability.
Fig. 7 is referred to, in the primary particle inversion resistant synchronous reset d type flip flop that Fig. 7 is provided for first embodiment of the invention
From the electrical block diagram of latch buffer circuit, should include from latch buffer circuit：
One input and two output ends, an input connect D3, and two output ends are respectively D4 and D5.
Should be from latch buffer circuit by the 24th PMOS, the 25th PMOS, the 26th PMOS, second
17 PMOSs, the 28th PMOS, the 29th PMOS, the 30th PMOS, the 31st PMOS, the 26th
NMOS tube, the 27th NMOS tube, the 28th NMOS tube, the 29th NMOS, the 30th NMOS tube, the 31st NMOS
Pipe, the 32nd NMOS tube, the 33rd NMOS tube composition.
Wherein, the 24th PMOS, the 25th PMOS, the 26th PMOS, the 27th PMOS, second
18 PMOSs, the 29th PMOS, the 30th PMOS, the substrate of the 31st PMOS meet power vd D and (do not show in figure
Go out), the 26th NMOS tube, the 27th NMOS tube, the 28th NMOS tube, the 29th NMOS, the 30th NMOS tube,
31 NMOS tubes, the 32nd NMOS tube, the Substrate ground (not shown) of the 33rd NMOS tube.
Grid Pg24 the connections D3, source electrode Ps24 of the 24th PMOS meet power vd D, and drain electrode Pd24 connects second respectively
The grid Pg25 of 15 PMOSs, the drain electrode Nd26 of the 26th NMOS tube, the grid Ng27 of the 27th NMOS tube；20th
Grid Ng26 connection D3, source electrode the Ns26 ground connection of six NMOS tubes；The source electrode Ps25 of the 25th PMOS meets power vd D, drain electrode
Pd25 connects grid Pg26, the drain electrode Nd27 of the 27th NMOS tube, the 28th NMOS tube of the 26th PMOS respectively
Grid Ng28；27th NMOS tube source electrode Ns27 is grounded；The source electrode Ps26 of the 26th PMOS meets power vd D, drain electrode
Pd26 connects grid Pg27, the drain electrode Nd28 of the 28th NMOS tube, the 29th NMOS tube of the 27th PMOS respectively
Grid Ng29；28th NMOS tube source electrode Ns28 is grounded；The source electrode Ps27 of the 27th PMOS meets power vd D, drain electrode
Pd27 connects the drain electrode Nd29 and D4 of the 29th NMOS tube respectively；The source electrode Ns29 ground connection of the 29th NMOS tube.
Grid Pg28 the connections D3, source electrode Ps28 of the 28th PMOS meet power vd D, and drain electrode Pd28 connects second respectively
The grid Pg29 of 19 PMOSs, the drain electrode Nd30 of the 30th NMOS tube, the grid Ng33 of the 33rd NMOS tube；30th
The grid Ng30 of NMOS tube connects drain electrode Pd29, grid Pg30, the 3rd of the 30th PMOS of the 29th PMOS respectively
The drain electrode Nd31 of 11 NMOS tubes, source electrode Ns30 are grounded；The source electrode Ps29 of the 29th PMOS meets power vd D；31st
The grid Ng31 of NMOS tube connects drain electrode Pd30, grid Pg31, the 3rd of the 31st PMOS of the 30th PMOS respectively
The drain electrode Nd32 of 12 NMOS tubes, source electrode Ns31 are grounded；The source electrode Ps30 of the 30th PMOS meets power vd D；32nd
The grid Ng32 of NMOS tube connects drain electrode Pd31, drain electrode Nd33, D3 of the 33rd NMOS tube of the 31st PMOS respectively
And D5, source electrode Ns32 ground connection；The source electrode Ps31 of the 31st PMOS meets power vd D；The source electrode Ns33 of the 33rd NMOS tube
Ground connection.
This is essentially identical with the operation principle of foregoing main latch buffer circuit from latch buffer circuit, no longer goes to live in the household of one's in-laws on getting married herein
State.
Fig. 8 is referred to, in the primary particle inversion resistant synchronous reset d type flip flop that Fig. 8 is provided for first embodiment of the invention
From the electrical block diagram of latch, should include from latch：
Ten inputs and two output ends, wherein, four inputs are connected with clock signal input terminal CLK respectively, and four
Individual input is connected with CLK1 respectively, and an input is connected with D4, and an input is connected with D5；Two output ends are respectively
First output end Q and the second output end QN.
From latch by the 32nd PMOS, the 33rd PMOS, the 34th PMOS, the 35th PMOS
Pipe, the 36th PMOS, the 37th PMOS, the 38th PMOS, the 39th PMOS, the 40th PMOS,
41st PMOS, the 42nd PMOS, the 34th NMOS tube, the 35th NMOS tube, the 36th NMOS tube,
37 NMOS tubes, the 38th NMOS tube, the 39th NMOS tube, the 40th NMOS tube, the 41st NMOS tube, the 40th
Two NMOS tubes, the 43rd NMOS tube, the 44th NMOS tube composition.
32nd PMOS, the 33rd PMOS, the 34th PMOS, the 35th PMOS, the 36th
PMOS, the 37th PMOS, the 38th PMOS, the 39th PMOS, the 40th PMOS, the 41st PMOS
Pipe, the substrate of the 42nd PMOS connect power vd D (not shown)s, the 34th NMOS tube, the 35th NMOS tube, the
36 NMOS tubes, the 37th NMOS tube, the 38th NMOS tube, the 39th NMOS tube, the 40th NMOS tube, the 40th
One NMOS tube, the 42nd NMOS tube, the 43rd NMOS tube, the Substrate ground (not shown) of the 44th NMOS tube.
Grid Ng34 the connections CLK1, source electrode Ns34 of the 34th NMOS tube connect the source electrode of the 32nd PMOS respectively
Ps32 and D4, drain electrode Nd34 connect the drain electrode Pd32 of the 32nd PMOS, the source electrode Ns37 of the 37th NMOS tube, the respectively
The source electrode Ps35 of 35 PMOSs, the grid Ng38 of the 38th NMOS tube, grid Pg37, the 4th of the 37th PMOS
The grid Ng40 of ten NMOS tubes, the grid Pg39 of the 39th PMOS；The grid Pg32 connections CLK of the 32nd PMOS；
35th NMOS tube grid Ng35 connection CLK1, source electrode Ns35 connect respectively the 33rd PMOS source electrode Ps33 and
D5, drain electrode Nd35 connects drain electrode Pd33, source electrode Ns36, the 34th of the 36th NMOS tube of the 33rd PMOS respectively
The source electrode Ps34 of PMOS, the grid Pg36 of the 36th PMOS, grid Ng39, the 38th of the 39th NMOS tube
The grid Pg38 of PMOS, the grid Ng41 of the 41st NMOS tube；The grid Pg33 connections CLK of the 33rd PMOS.
Grid Ng36 the connection CLK, drain electrode Nd36 of the 36th NMOS tube connect the drain electrode of the 34th PMOS respectively
Pd34, the drain electrode Pd40 of the 40th PMOS, the drain electrode Nd42 of the 42nd NMOS tube；The grid Pg34 of the 34th PMOS
Connection CLK1；Grid Ng37 the connection CLK, drain electrode Nd37 of the 37th NMOS tube connect the drain electrode of the 35th PMOS respectively
Pd35, the drain electrode Pd41 of the 41st PMOS, the drain electrode Nd43 of the 43rd NMOS tube；The grid of the 35th PMOS
Pg35 connects CLK1.
The source electrode Ps36 of the 36th PMOS meets power vd D, and drain electrode Pd36 connects the source electrode of the 37th PMOS
Ps37；The drain electrode Pd37 of the 37th PMOS connects the drain electrode Nd38 of the 38th NMOS tube, the 42nd NMOS tube respectively
Grid Ng42, the grid Pg41 of the 41st PMOS, the grid Pg42 of the 42nd PMOS, the 44th NMOS tube
Grid Ng44 and the second output end QN；The source electrode Ns38 of the 38th NMOS tube connects the drain electrode Nd39 of the 39th NMOS tube；
The source electrode Ns39 ground connection of the 39th NMOS tube.
The source electrode Ps38 of the 38th PMOS meets power vd D, and drain electrode Pd38 connects the source electrode of the 39th PMOS
Ps39；The drain electrode Pd39 of the 39th PMOS connects drain electrode Nd40, the grid of the 40th PMOS of the 40th NMOS tube respectively
The grid Ng43 of pole Pg40, the 43rd NMOS tube；The source electrode Ns40 of the 40th NMOS tube connects the leakage of the 41st NMOS tube
Pole Nd41；The source electrode Ns41 ground connection of the 41st NMOS tube.
The source electrode Ps40 of the 40th PMOS meets power vd D；The source electrode Ns42 ground connection of the 42nd NMOS tube；41st
The source electrode Ps41 of PMOS meets power vd D；The source electrode Ns43 ground connection of the 43rd NMOS tube；The source electrode of the 42nd PMOS
Ps42 meets power vd D, and drain electrode Pd42 connects the drain electrode Nd44 and the first output end Q of the 44th NMOS tube respectively；44th
The source electrode Ns44 ground connection of NMOS tube.
This is essentially identical with the operation principle of foregoing main latch from latch, will not be repeated here.
Control and clock signal synchronization of the reset signal to circuit output in this patent, when CLK0 is changed into current potential 0 from current potential 1
When, if reset signal R0=1, without homing action, if reset signal R0=0, R01=1, the 23rd in main latch
NMOS tube, the conducting of the 24th NMOS tube, the 23rd NMOS tube, the drain voltage of the 24th NMOS tube are dragged down by ground voltage
It is low potential, and then is set to 0 output signal D02 by feedback control loop.Now, from latch with from latch inputs D4,
Two D5 connected transmission gates are in the conduction state, and then also set to 0 from the output signal of latch outputs Q, so as to complete
The homing action of circuit.
When CLK0 is changed into current potential 1 from current potential 0, if reset signal R0=1, without homing action, if reset signal R0=
0, then R1=1, but now the 15th PMOS and the 15th NMOS tube the 3rd transmission gate of composition, and the 16th in main latch
PMOS and the 16th NMOS tube constitute the 4th transmission gate and are in off state, and now cannot to have influence on circuit defeated for reset signal
Go out the state of signal.Therefore, reset signal is synchronous with clock signal to the control of circuit output.
Primary particle inversion resistant synchronous reset d type flip flop provided in an embodiment of the present invention, compared to prior art, the present invention
Increase buffer circuit by main latch and from before latch, improve the anti-single particle upset energy of synchronous reset d type flip flop
Power, duplication redundancy reinforcing is carried out to main latch and from latch, that is, be separated into the C being mutually redundant2Pull-up in MOS circuits
PMOS and pull-down NMOS pipe, it is to avoid from latch may be by backfeed loop caused by single event transient pulse, to main lock
Storage and the C from latch circuit2MOS circuits are improved, and control of the clock signal to circuit is realized by cmos transmission gate
System, further increases the anti-single particle upset ability of synchronous reset d type flip flop.
It should be noted that for foregoing each method embodiment, in order to simplicity is described, therefore it is all expressed as a series of
Combination of actions, but those skilled in the art should know, the present invention not by described by sequence of movement limited because
According to the present invention, some steps can sequentially or simultaneously be carried out using other.Secondly, those skilled in the art should also know
Know, embodiment described in this description belongs to preferred embodiment, and involved action and module might not all be this hairs
Necessary to bright.
In the above-described embodiments, the description to each embodiment all emphasizes particularly on different fields, and does not have the portion described in detail in certain embodiment
Point, may refer to the associated description of other embodiments.
It is more than the description to primary particle inversion resistant synchronous reset d type flip flop provided by the present invention, for this area
Technical staff, according to the embodiment of the present invention thought, will change in specific embodiments and applications, it is comprehensive
On, this specification content should not be construed as limiting the invention.
Claims (7)
1. a kind of primary particle inversion resistant synchronous reset d type flip flop, it is characterised in that the synchronous reset d type flip flop includes：
Clock signal input circuit, reset signal input circuit, main latch buffer circuit, from latch buffer circuit, main lock
Storage and from latch, the main latch and the latch that duplication redundancy reinforcing is from latch；
The synchronous reset d type flip flop has three inputs and two output ends, and three inputs are respectively clock signal
Input CLK, reset signal input R and data signal input D, two output ends be respectively the first output end Q and
Second output end QN；
The clock signal input circuit respectively with the clock signal input terminal CLK, the reset signal input circuit, described
Main latch and it is described from latch connection；
The reset signal input circuit also respectively with the reset signal input R, the main latch and described from latch
Device is connected；
The main latch buffer circuit is connected with the data signal input D, the main latch respectively；
It is described from latch buffer circuit respectively with the main latch, described be connected from latch；
It is described to be also connected with the first output end Q and the second output end QN from latch.
2. primary particle inversion resistant synchronous reset d type flip flop as claimed in claim 1, it is characterised in that the clock signal
Input circuit has an input and an output end, and an input is the clock signal input terminal CLK, an institute
Output end is stated for CLK1；
The clock signal input circuit is made up of the first PMOS, the second PMOS, the first NMOS tube and the second NMOS tube；
First PMOS, the substrate of second PMOS meet power vd D, first NMOS tube, the 2nd NMOS
The Substrate ground of pipe；
The grid Pg1 of first PMOS connects the clock signal input terminal CLK, and source electrode Ps1 meets power vd D, and drain Pd1
Connect the source electrode Ps2 of second PMOS；The grid Pg2 of second PMOS connects the clock signal input terminal CLK,
Drain electrode Pd2 connections CLK1；The grid Ng1 of first NMOS tube connects the clock signal input terminal CLK, source electrode Ns1 connections
The drain electrode Nd2 of second NMOS tube, drain electrode Nd1 connections CLK1；The grid Ng2 of second NMOS tube connects the clock letter
Number input CLK, source electrode Ns2 ground connection.
3. primary particle inversion resistant synchronous reset d type flip flop as claimed in claim 2, it is characterised in that the reset signal
Input circuit has an input and an output end, and an input is the reset signal input R, described in one
Output end is R1；
The reset signal input circuit is made up of the 3rd PMOS, the 4th PMOS, the 3rd NMOS tube and the 4th NMOS tube；
3rd PMOS, the substrate of the 4th PMOS meet power vd D, the 3rd NMOS tube, the 4th NMOS
The Substrate ground of pipe；
The grid Pg3 of the 3rd PMOS connects the reset signal input R, and source electrode Ps3 meets power vd D, and drain electrode Pd3 connects
Meet the source electrode Ps4 of the 4th PMOS；The grid Pg4 of the 4th PMOS connects the reset signal input R, drain electrode
Pd4 connects R1；The grid Ng3 of the 3rd NMOS tube connects the reset signal input R, source electrode Ns3 connections the described 4th
The drain electrode Nd4 of NMOS tube, drain electrode Nd3 connections R1；The grid Ng4 of the 4th NMOS tube connects the reset signal input R,
Source electrode Ns4 is grounded.
4. primary particle inversion resistant synchronous reset d type flip flop as claimed in claim 3, it is characterised in that the main latch
Buffer circuit has an input and two output ends, and an input is the data signal input D, described in two
Output end is respectively D1 and D2；
The main latch buffer circuit is by the 5th PMOS, the 6th PMOS, the 7th PMOS, the 8th PMOS, the 9th
PMOS, the tenth PMOS, the 11st PMOS, the 12nd PMOS, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube,
8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube, the 11st NMOS tube, the 12nd NMOS tube composition；
5th PMOS, the 6th PMOS, the 7th PMOS, the 8th PMOS, the 9th PMOS
Pipe, the tenth PMOS, the 11st PMOS, the substrate of the 12nd PMOS meet power vd D, the described 5th
NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the described tenth
NMOS tube, the 11st NMOS tube, the Substrate ground of the 12nd NMOS tube；
The grid Pg5 of the 5th PMOS connects the data signal input D, and source electrode Ps5 meets power vd D, Pd5 points of drain electrode
Not Lian Jie the 6th PMOS grid Pg6, the drain electrode Nd5 of the 5th NMOS tube, the grid Ng6 of the 6th NMOS tube；Described 5th
The grid Ng5 of NMOS tube connects the data signal input D, source electrode Ns5 ground connection；The source electrode Ps6 of the 6th PMOS connects
Power vd D, drain electrode Pd6 connects the grid Pg7 of the 7th PMOS, the drain electrode Nd6 of the 6th NMOS tube, the grid of the 7th NMOS tube respectively
Pole Ng7；The 6th NMOS tube source electrode Ns6 ground connection；The source electrode Ps7 of the 7th PMOS meets power vd D, drain electrode Pd7 difference
Connect grid Pg8, the drain electrode Nd7 of the 7th NMOS tube, the grid Ng8 of the 8th NMOS tube of the 8th PMOS；7th NMOS
Pipe source electrode Ns7 is grounded；The source electrode Ps8 of the 8th PMOS meets power vd D, and drain electrode Pd8 connects the leakage of the 8th NMOS tube respectively
Pole Nd8 and D1；The source electrode Ns8 ground connection of the 8th NMOS tube；
The grid Pg9 of the 9th PMOS connects the data signal input D, and source electrode Ps9 meets power vd D, Pd9 points of drain electrode
Grid Pg10, the drain electrode Nd9 of the 9th NMOS tube, the grid of the 12nd NMOS tube of the tenth PMOS are not connected
Ng12；The grid Ng9 of the 9th NMOS tube connects the drain electrode Pd10 of the tenth PMOS, the 11st PMOS respectively
Grid Pg11, the drain electrode Nd10 of the tenth NMOS tube, source electrode Ns9 ground connection；The source electrode Ps10 of the tenth PMOS connects electricity
Source VDD；The grid Ng10 of the tenth NMOS tube connects drain electrode Pd11, the described 12nd of the 11st PMOS respectively
The drain electrode Nd11 of the grid Pg12 of PMOS, the 11st NMOS tube, source electrode Ns10 are grounded；The source of the 11st PMOS
Pole Ps11 meets power vd D；The grid Ng11 of the 11st NMOS tube connect respectively the 12nd PMOS drain electrode Pd12,
The drain electrode Nd12 of the 12nd NMOS tube, data signal input D and D2, source electrode Ns11 ground connection；12nd PMOS
Source electrode Ps12 meet power vd D；The source electrode Ns12 ground connection of the 12nd NMOS tube.
5. primary particle inversion resistant synchronous reset d type flip flop as claimed in claim 4, it is characterised in that the main latch
There are 12 inputs and an output end, wherein, four inputs connect with the clock signal input terminal CLK respectively
Connect, four inputs are connected with CLK1 respectively, two inputs are connected with R1 respectively, an input and D1
Connection a, input is connected with D2；One output end is D3；
The main latch is by the 13rd PMOS, the 14th PMOS, the 15th PMOS, the 16th PMOS, the 17th
PMOS, the 18th PMOS, the 19th PMOS, the 20th PMOS, the 21st PMOS, the 22nd PMOS,
23rd PMOS, the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube, the 16th NMOS tube, the 17th NMOS
Pipe, the 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube, the 21st NMOS tube, the 22nd NMOS tube, second
13 NMOS tubes, the 24th NMOS tube, the 25th NMOS tube composition；
It is 13rd PMOS, the 14th PMOS, the 15th PMOS, the 16th PMOS, described
17th PMOS, the 18th PMOS, the 19th PMOS, the 20th PMOS, the described 21st
PMOS, the 22nd PMOS, the substrate of the 23rd PMOS meet power vd D, the 13rd NMOS tube,
14th NMOS tube, the 15th NMOS tube, the 16th NMOS tube, the 17th NMOS tube, the described tenth
Eight NMOS tubes, the 19th NMOS tube, the 20th NMOS tube, the 21st NMOS tube, the described 22nd
NMOS tube, the 23rd NMOS tube, the 24th NMOS tube, the Substrate ground of the 25th NMOS tube；
Grid Ng13 the connections CLK, source electrode Ns13 of the 13rd NMOS tube connect the source electrode Ps13 of the 13rd PMOS respectively
And D1, drain electrode Nd13 connect drain electrode Pd13, source electrode Ns16, the institute of the 16th NMOS tube of the 13rd PMOS respectively
State source electrode Ps16, the grid Ng17 of the 17th NMOS tube, the grid of the 18th PMOS of the 16th PMOS
Pg18, the grid Ng19 of the 19th NMOS tube, the grid Pg20 of the 20th PMOS；13rd PMOS
Grid Pg13 connects CLK1；Grid Ng14 the connections CLK, source electrode Ns14 of the 14th NMOS tube connect the 14th PMOS respectively
The source electrode Ps14 and D2 of pipe, drain electrode Nd14 connect the drain electrode Pd14 of the 14th PMOS, the 15th NMOS tube respectively
Source electrode Ns15, the source electrode Ps15 of the 15th PMOS, grid Pg17, the described 18th of the 17th PMOS
The grid Ng18 of NMOS tube, the grid Pg19 of the 19th PMOS, the grid Ng20 of the 20th NMOS tube；Described
The grid Pg14 connections CLK1 of 14 PMOSs；
Grid Ng15 the connection CLK1, drain electrode Nd15 of the 15th NMOS tube connect the drain electrode of the 15th PMOS respectively
Pd15, the drain electrode Pd21 of the 21st PMOS, drain electrode Nd21, the described 23rd of the 21st NMOS tube
The drain electrode Nd23 of NMOS tube；The grid Pg15 connections CLK of the 15th PMOS；The grid Ng16 of the 16th NMOS tube
Connection CLK1, drain electrode Nd16 connects drain electrode Pd16, the drain electrode of the 22nd PMOS of the 16th PMOS respectively
Pd22, the drain electrode Nd22 of the 22nd NMOS tube, the drain electrode Nd24 of the 24th NMOS tube；16th PMOS
The grid Pg16 connections CLK of pipe；
The source electrode Ps17 of the 17th PMOS meets power vd D, and drain electrode Pd17 connects the source electrode of the 18th PMOS
Ps18；The drain electrode Pd18 of the 18th PMOS connects drain electrode Nd17, the described 20th of the 17th NMOS tube respectively
The grid Ng21 of one NMOS tube, the grid Pg22 of the 22nd PMOS, the grid Pg23 of the 23rd PMOS,
The grid Ng25 of the 25th NMOS tube；The source electrode Ns17 of the 17th NMOS tube connects the 18th NMOS tube
Drain electrode Nd18；The source electrode Ns18 ground connection of the 18th NMOS tube；The source electrode Ps19 of the 19th PMOS meets power vd D,
Drain electrode Pd19 connects the source electrode Ps20 of the 20th PMOS；The drain electrode Pd20 of the 20th PMOS connects described respectively
The drain electrode Nd19 of the 19th NMOS tube, the grid Pg21 of the 21st PMOS, the grid of the 22nd NMOS tube
Ng22；The source electrode Ns19 of the 19th NMOS tube connects the drain electrode Nd20 of the 20th NMOS tube；20th NMOS
The source electrode Ns20 ground connection of pipe；
The source electrode Ps21 of the 21st PMOS meets power vd D；The source electrode Ns21 ground connection of the 21st NMOS tube；Institute
The source electrode Ps22 for stating the 22nd PMOS meets power vd D；The source electrode Ns22 ground connection of the 22nd NMOS tube；Described second
Grid Ng23 connection R1, source electrode the Ns23 ground connection of 13 NMOS tubes；The grid Ng24 connection R1 of the 24th NMOS tube, source
Pole Ns24 is grounded；The source electrode Ps23 of the 23rd PMOS meets power vd D, and drain electrode Pd23 connects the 25th NMOS respectively
The drain electrode Nd25 and D3 of pipe；The source electrode Ns25 ground connection of the 25th NMOS tube.
6. primary particle inversion resistant synchronous reset d type flip flop as claimed in claim 5, it is characterised in that described from latch
Buffer circuit has an input and two output ends, and an input connection D3, two output ends are respectively D4
And D5；
It is described from latch buffer circuit by the 24th PMOS, the 25th PMOS, the 26th PMOS, the 20th
Seven PMOSs, the 28th PMOS, the 29th PMOS, the 30th PMOS, the 31st PMOS, the 26th
NMOS tube, the 27th NMOS tube, the 28th NMOS tube, the 29th NMOS, the 30th NMOS tube, the 31st NMOS
Pipe, the 32nd NMOS tube, the 33rd NMOS tube composition；
24th PMOS, the 25th PMOS, the 26th PMOS, the 27th PMOS
Pipe, the 28th PMOS, the 29th PMOS, the 30th PMOS, the 31st PMOS
Substrate meet power vd D, it is the 26th NMOS tube, the 27th NMOS tube, the 28th NMOS tube, described
29th NMOS tube, the 30th NMOS tube, the 31st NMOS tube, the 32nd NMOS tube, described
The Substrate ground of 33 NMOS tubes；
Grid Pg24 the connections D3, source electrode Ps24 of the 24th PMOS meet power vd D, and drain electrode Pd24 connects second respectively
The grid Pg25 of 15 PMOSs, the drain electrode Nd26 of the 26th NMOS tube, the grid Ng27 of the 27th NMOS tube；Described
Grid Ng26 connection D3, source electrode the Ns26 ground connection of 26 NMOS tubes；The source electrode Ps25 of the 25th PMOS connects power supply
VDD, drain electrode Pd25 connect the grid Pg26 of the 26th PMOS, the drain electrode Nd27 of the 27th NMOS tube, the respectively
The grid Ng28 of 28 NMOS tubes；The 27th NMOS tube source electrode Ns27 ground connection；The source of the 26th PMOS
Pole Ps26 meets power vd D, and drain electrode Pd26 connects the grid Pg27 of the 27th PMOS, the drain electrode of the 28th NMOS tube respectively
The grid Ng29 of Nd28, the 29th NMOS tube；The 28th NMOS tube source electrode Ns28 ground connection；27th PMOS
The source electrode Ps27 of pipe meets power vd D, and drain electrode Pd27 connects the drain electrode Nd29 and D4 of the 29th NMOS tube respectively；Described 20th
The source electrode Ns29 ground connection of nine NMOS tubes；
Grid Pg28 the connections D3, source electrode Ps28 of the 28th PMOS meet power vd D, and drain electrode Pd28 connects described respectively
The grid Pg29 of the 29th PMOS, the drain electrode Nd30 of the 30th NMOS tube, the grid of the 33rd NMOS tube
Ng33；The grid Ng30 of the 30th NMOS tube connects drain electrode Pd29, the described 3rd of the 29th PMOS respectively
The drain electrode Nd31 of the grid Pg30 of ten PMOSs, the 31st NMOS tube, source electrode Ns30 are grounded；29th PMOS
The source electrode Ps29 of pipe meets power vd D；The grid Ng31 of the 31st NMOS tube connects the 30th PMOS respectively
Drain electrode Pd30, the grid Pg31 of the 31st PMOS, the drain electrode Nd32 of the 32nd NMOS tube, source electrode Ns31 connect
Ground；The source electrode Ps30 of the 30th PMOS meets power vd D；The grid Ng32 of the 32nd NMOS tube connects institute respectively
State drain electrode Pd31, drain electrode Nd33, D3 and D5 of the 33rd NMOS tube of the 31st PMOS, source electrode Ns32 ground connection；
The source electrode Ps31 of the 31st PMOS meets power vd D；The source electrode Ns33 ground connection of the 33rd NMOS tube.
7. primary particle inversion resistant synchronous reset d type flip flop as claimed in claim 6, it is characterised in that described from latch
There are ten inputs and two output ends, wherein, four inputs are connected with the clock signal input terminal CLK respectively,
Four inputs are connected with CLK1 respectively, and an input is connected with D4, and an input is connected with D5；Two
The individual output end is respectively the first output end Q and the second output end QN；
It is described from latch by the 32nd PMOS, the 33rd PMOS, the 34th PMOS, the 35th PMOS
Pipe, the 36th PMOS, the 37th PMOS, the 38th PMOS, the 39th PMOS, the 40th PMOS,
41st PMOS, the 42nd PMOS, the 34th NMOS tube, the 35th NMOS tube, the 36th NMOS tube,
37 NMOS tubes, the 38th NMOS tube, the 39th NMOS tube, the 40th NMOS tube, the 41st NMOS tube, the 40th
Two NMOS tubes, the 43rd NMOS tube, the 44th NMOS tube composition；
32nd PMOS, the 33rd PMOS, the 34th PMOS, the 35th PMOS
Pipe, the 36th PMOS, the 37th PMOS, the 38th PMOS, the 39th PMOS
Pipe, the 40th PMOS, the 41st PMOS, the substrate of the 42nd PMOS meet power vd D, described
It is 34th NMOS tube, the 35th NMOS tube, the 36th NMOS tube, the 37th NMOS tube, described
38th NMOS tube, the 39th NMOS tube, the 40th NMOS tube, the 41st NMOS tube, described
42 NMOS tubes, the 43rd NMOS tube, the Substrate ground of the 44th NMOS tube；
Grid Ng34 the connections CLK1, source electrode Ns34 of the 34th NMOS tube connect the source electrode of the 32nd PMOS respectively
Ps32 and D4, drain electrode Nd34 connects drain electrode Pd32, the source of the 37th NMOS tube of the 32nd PMOS respectively
Pole Ns37, the source electrode Ps35 of the 35th PMOS, grid Ng38, the described 37th of the 38th NMOS tube
The grid Pg37 of PMOS, the grid Ng40 of the 40th NMOS tube, the grid Pg39 of the 39th PMOS；It is described
The grid Pg32 connections CLK of the 32nd PMOS；Grid Ng35 the connections CLK1, source electrode Ns35 of the 35th NMOS tube
The source electrode Ps33 and D5 of the 33rd PMOS are connected respectively, and drain electrode Nd35 connects the drain electrode of the 33rd PMOS respectively
Pd33, the source electrode Ns36 of the 36th NMOS tube, source electrode Ps34, the described 36th of the 34th PMOS
The grid Pg36 of PMOS, the grid Ng39 of the 39th NMOS tube, grid Pg38, the institute of the 38th PMOS
State the grid Ng41 of the 41st NMOS tube；The grid Pg33 connections CLK of the 33rd PMOS；
Grid Ng36 the connection CLK, drain electrode Nd36 of the 36th NMOS tube connect the 34th PMOS respectively
Drain electrode Pd34, the drain electrode Pd40 of the 40th PMOS, the drain electrode Nd42 of the 42nd NMOS tube；Described 34th
The grid Pg34 connections CLK1 of PMOS；The grid Ng37 of the 37th NMOS tube connects CLK, and drain electrode Nd37 is connected respectively
The drain electrode Pd35 of the 35th PMOS, the drain electrode Pd41 of the 41st PMOS, the 43rd NMOS tube
Drain electrode Nd43；The grid Pg35 connections CLK1 of the 35th PMOS；
The source electrode Ps36 of the 36th PMOS meets power vd D, and drain electrode Pd36 connects the source of the 37th PMOS
Pole Ps37；The drain electrode Pd37 of the 37th PMOS connects the drain electrode Nd38 of the 38th NMOS tube, described respectively
The grid Ng42 of the 42nd NMOS tube, the grid Pg41 of the 41st PMOS, the grid of the 42nd PMOS
Pole Pg42, the grid Ng44 of the 44th NMOS tube and the second output end QN；The source of the 38th NMOS tube
Pole Ns38 connects the drain electrode Nd39 of the 39th NMOS tube；The source electrode Ns39 ground connection of the 39th NMOS tube；
The source electrode Ps38 of the 38th PMOS meets power vd D, and drain electrode Pd38 connects the source of the 39th PMOS
Pole Ps39；The drain electrode Pd39 of the 39th PMOS connects the drain electrode Nd40 of the 40th NMOS tube, described respectively
The grid Ng43 of the grid Pg40 of 40 PMOSs, the 43rd NMOS tube；The source electrode Ns40 of the 40th NMOS tube
Connect the drain electrode Nd41 of the 41st NMOS tube；The source electrode Ns41 ground connection of the 41st NMOS tube；
The source electrode Ps40 of the 40th PMOS meets power vd D；The source electrode Ns42 ground connection of the 42nd NMOS tube；It is described
The source electrode Ps41 of the 41st PMOS meets power vd D；The source electrode Ns43 ground connection of the 43rd NMOS tube；Described 40th
The source electrode Ps42 of two PMOSs meets power vd D, and drain electrode Pd42 connects the drain electrode Nd44 and described the of the 44th NMOS tube respectively
One output end Q；The source electrode Ns44 ground connection of the 44th NMOS tube.
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| CN108563463A (en) * | 2018-03-29 | 2018-09-21 | 深圳市国微电子有限公司 | Register and its initial method |
| CN110190833A (en) * | 2019-07-03 | 2019-08-30 | 西安微电子技术研究所 | A kind of primary particle inversion resistant self-test self- recoverage synchronous reset d type flip flop |
| CN110311660A (en) * | 2019-07-03 | 2019-10-08 | 西安微电子技术研究所 | A kind of adaptive primary particle inversion resistant d type flip flop |
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| CN103825584A (en) * | 2013-12-11 | 2014-05-28 | 中国人民解放军国防科学技术大学 | Settable and resettable D trigger resisting single event upset and single event transient |
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| CN104821804A (en) * | 2015-05-27 | 2015-08-05 | 中国电子科技集团公司第四十七研究所 | Delay flip-flop with reset terminal |
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| CN103825584A (en) * | 2013-12-11 | 2014-05-28 | 中国人民解放军国防科学技术大学 | Settable and resettable D trigger resisting single event upset and single event transient |
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| CN108563463A (en) * | 2018-03-29 | 2018-09-21 | 深圳市国微电子有限公司 | Register and its initial method |
| CN110190833A (en) * | 2019-07-03 | 2019-08-30 | 西安微电子技术研究所 | A kind of primary particle inversion resistant self-test self- recoverage synchronous reset d type flip flop |
| CN110311660A (en) * | 2019-07-03 | 2019-10-08 | 西安微电子技术研究所 | A kind of adaptive primary particle inversion resistant d type flip flop |
| CN110190833B (en) * | 2019-07-03 | 2023-02-07 | 西安微电子技术研究所 | Self-detection and self-recovery synchronous reset D trigger resisting single event upset |
| CN110311660B (en) * | 2019-07-03 | 2023-02-24 | 西安微电子技术研究所 | Self-adaptive single event upset resistant D trigger |
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| CN106712743B (en) | 2020-03-20 |
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