CN103825579A - Resettable D trigger resisting single event upset and single event transient - Google Patents

Resettable D trigger resisting single event upset and single event transient Download PDF

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Publication number
CN103825579A
CN103825579A CN201310670222.XA CN201310670222A CN103825579A CN 103825579 A CN103825579 A CN 103825579A CN 201310670222 A CN201310670222 A CN 201310670222A CN 103825579 A CN103825579 A CN 103825579A
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connects
drain electrode
grid
pipe
source electrode
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CN103825579B (en
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陈书明
王崇峰
姚龙
孙永节
梁斌
池雅庆
郭阳
陈建军
刘祥远
许文涛
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National University of Defense Technology
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Abstract

The invention discloses a resettable D trigger resisting single event upset and single event transient, so as to solve the problem of poor ability to resist single event upset and single event transient of the resettable D trigger. According to the invention, the resettable D trigger is composed of a clock circuit, a reset buffer circuit, a master latch, a slave latch, an output buffer circuit and a buffer circuit; the master latch and the slave latch are redundant reinforcement latches; the master latch and the slave latch are orderly connected in series, and are connected with the clock circuit and the reset buffer circuit; the master latch is connected with the buffer circuit; and the slave latch is connected with the output buffer circuit. A pull-up PMOS tube and a pull-down NMOS tube in mutually redundant C2MOS circuits in the master latch and the slave latch are separated, which improves the resettable D trigger's ability to resist single event upset. Through the buffer circuit, an error is avoided under a long-duration single event transient, and the ability to resist single event transient is further improved through a dual mode redundant pathway.

Description

The resetted d type flip flop of anti-single particle overturn and single-ion transient state
Technical field
The present invention relates to a kind of D master-slave flip-flop, particularly the resetted d type flip flop of a kind of anti-single particle overturn (Single Event Upset, SEU) and anti-single particle transient state (Single Event Transient, SET).
Background technology
In cosmic space, there are a large amount of high energy particles (proton, electronics, heavy ion etc.), sequence circuit in integrated circuit is subject to after these high-energy particle bombardments, the state of its maintenance likely overturns, this effect is called single-particle inversion effect, the LET(linear energy transfer of single-particle bombardment integrated circuit) value is higher, more easily produces single-particle inversion effect.Combinational circuit in integrated circuit is subject to after these high-energy particle bombardments, likely produce instantaneous electric pulse, this effect is called single-ion transient state effect, and the LET value of single-particle bombardment integrated circuit is higher, the instantaneous electric pulse duration producing is longer, and electric pulse is more easily gathered by sequence circuit.The upset if the state of sequence circuit makes a mistake, or single-ion transient state effect produce instantaneous electric pulse gathered by sequence circuit mistake, all can cause integrated circuit job insecurity even to produce fatal mistake, this is particularly serious in space flight, military field.Therefore, thus to integrated circuit reinforce reduce single-particle inversion effect and single-ion transient state effect more and more important.
D type flip flop is in integrated circuit, to use one of maximum timing unit, the anti-single particle overturn of the ability of its anti-single particle overturn and single-ion transient state to whole integrated circuit and the ability of single-ion transient state play a crucial role, and d type flip flop is carried out to corresponding reinforcing and can make the anti-single particle overturn of integrated circuit and single-ion transient state ability be improved.
Traditional d type flip flop is D master-slave flip-flop, generally forms by main latch with from level series of latches.Common lock storage is replaced with to DICE(Dual Interlocked Storage Cell, double interlocking memory cell) etc. redundancy ruggedized construction can realize primary particle inversion resistant d type flip flop.Transform on this basis input/output port, can realize anti-single particle overturn and single-ion transient state simultaneously.The people such as M.J.Myjak are at The47 ththe 47th IEEE Circuits and Systems Midwest international conference of IEEE International Midwest Symposium on Circuits and Systems() on " Enhanced Fault-Tolerant CMOS Memory Elements " (the strengthening fault-tolerant cmos memory cell) of delivering (2004, the I-453～I-456 page) on a kind of improved DICE circuit has been proposed, this circuit adopts DICE circuit to carry out anti-single particle overturn reinforcing, and bidirectional data line is divided into two write data lines and two read data lines, by the duplication redundancy of data wire, make at any time the single event transient pulse that propagates into DICE circuit by a certain data wire be difficult to cause the upset of whole circuit state, thereby realize the reinforcing for single-ion transient state.But there is positive feedback loop in the duplication redundancy of data wire, under compared with the single event transient pulse of long duration, can produce latch information upset, anti-single particle transient state ability is not high.
D.G.Mavis etc. are in the international Reliability Physics meeting of IEEE Reliability Physics Symposium() on time sampling d type flip flop circuit has been proposed in " Soft error rate mitigation techniques for modern microcircuits " (reducing the technology of modern microcircuit soft error rate) (2002 the 216th page-225 pages) of delivering.This circuit has been introduced delay and voting circuit in the feedback loop of latch data, thereby has possessed certain anti-single particle overturn and single-ion transient state ability.But voting circuit itself does not possess the ability of anti-single particle transient state, meeting output error data under single event transient pulse, anti-single particle transient state ability is not high.
Application number is the d type flip flop that 200910046337.5 Chinese patent discloses a kind of anti-single particle overturn and single event transient pulse.This invention is the d type flip flop that a kind of structure is similar to time sampling structure, comprises two variable connectors, two delay circuits, two shutter circuit and three inverters, has realized the reinforcing of anti-single particle overturn and the single-ion transient state of d type flip flop.This patent has the ability of anti-single particle transient state, but because the output Q of the 3rd reverser connects the input VIN0 of second variable connector, formed positive feedback loop, under compared with the single event transient pulse of long duration, can produce latch information upset, anti-single particle transient state ability is not high.
Some integrated circuit needs the state of d type flip flop in control integration circuit, forces d type flip flop output high level or low level.On the original architecture basics of d type flip flop, increase reset circuit and reset signal end, can realize the resetting structure of d type flip flop self, and control d type flip flop reset function by reset signal.But the d type flip flop anti-single particle transient state that can reset at present and anti-single particle overturn ability are not high, are unfavorable for using in the integrated circuit (IC) chip in the fields such as Aeronautics and Astronautics.
Application number is that 201110323795.6 Chinese patent discloses a kind of primary particle inversion resistant d type flip flop that resets, as shown in Figure 1, this invention is by clock circuit, reset buffer circuit, main latch, form from latch, output buffer, can be under the single-particle bombardment compared with high LET value normal work and do not produce single-particle inversion.Because this invention does not adopt buffer circuit in clock circuit He before main latch, so do not possess the ability of anti-single particle transient state, and main latch, do not adopt duplication redundancy from latch, in the time that the LET value of single-particle bombardment is higher, the some node upsets on circuit can cause whole circuit to overturn.
Summary of the invention
The technical problem to be solved in the present invention is, for current resetted d type flip flop anti-single particle transient state and the not high problem of anti-single particle overturn ability, to propose the resetted d type flip flop of a kind of anti-single particle overturn and single-ion transient state.
Concretism of the present invention is: carry out duplication redundancy reinforcing to main latch with from latch, and can anti-single particle overturn; In clock circuit He before main latch, add buffer circuit, can anti-single particle transient state; Cut off the positive feedback loop that may be caused by single event transient pulse from latch, can under the anti-single particle transient state compared with long duration, not overturn.
The resetted d type flip flop of anti-single particle overturn of the present invention and single-ion transient state is by clock circuit, reset buffer circuit, main latch, from latch, output buffer and buffer the electric circuit constitute.Main latch and from latch be redundancy reinforce latch.Main latch and from series connection before and after latch, and be all connected with clock circuit and reset buffer circuit.Main latch is also connected with buffer circuits, is also connected with output buffer from latch.
The resetted d type flip flop of anti-single particle overturn of the present invention and anti-single particle transient pulse has three inputs and an output.Three inputs are respectively clock signal input terminal CK, data-signal input D and reset signal input RN; Output is Q.
Clock circuit has an input and four outputs, and input is CK, and output is c1, c2, cn1, cn2.Clock circuit is made up of 12 PMOS and ten four NMOSs, and in circuit, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg43 of the 43 PMOS pipe connects CK, and drain electrode Pd43 connects the drain electrode Nd43 of the 43 NMOS pipe, and source electrode Ps43 connects power vd D; The grid Pg44 of the 44 PMOS pipe connects the drain electrode Pd43 of the 43 PMOS pipe, and drain electrode Pd44 connects the drain electrode Nd44 of the 44 NMOS pipe, and source electrode Ps44 connects power vd D; The grid Pg45 of the 45 PMOS pipe connects the drain electrode Pd44 of the 44 PMOS pipe, and drain electrode Pd45 connects the drain electrode Nd45 of the 45 NMOS pipe, and source electrode Ps45 connects power vd D; The grid Pg46 of the 46 PMOS pipe connects the drain electrode Pd45 of the 45 PMOS pipe, and drain electrode Pd46 connects the drain electrode Nd46 of the 46 NMOS pipe, and source electrode Ps46 connects power vd D; The grid Pg47 of the 47 PMOS pipe connects CK, and drain electrode Pd47 connects the source electrode Ps48 of the 48 PMOS pipe, and source electrode Ps47 connects VDD; The grid Pg48 of the 48 PMOS pipe connects the drain electrode Pd46 of the 46 PMOS pipe, and drain electrode Pd48 connects the drain electrode Nd47 of the 47 NMOS pipe, and as an output cn1 of clock circuit; The grid Pg49 of the 49 PMOS pipe connects CK, and drain electrode Pd49 connects the source electrode Ps50 of the 50 PMOS pipe, and source electrode Ps49 connects VDD; The grid Pg50 of the 50 PMOS pipe connects the drain electrode Pd46 of the 46 PMOS pipe, and drain electrode Pd50 connects the drain electrode Nd49 of the 49 NMOS pipe, and as an output cn2 of clock circuit; The grid Pg51 of the 51 PMOS pipe is as an output c1 of clock circuit, and drain electrode Pd51 connects the drain electrode Pd48 of the 48 PMOS pipe, and source electrode Ps51 connects VDD; The grid Pg52 of the 52 PMOS pipe connects the grid Ng53 of the 53 NMOS pipe an output c2 as clock circuit, and drain electrode Pd52 connects the drain electrode Nd53 of the 53 NMOS pipe and is connected with output cn2, and source electrode Ps52 connects VDD; The grid Pg53 of the 53 PMOS pipe connects output cn1, and drain electrode Pd53 connects output c1, and source electrode Ps53 connects VDD; The grid Pg54 of the 54 PMOS pipe connects output cn2, and drain electrode Pd54 connects output c2, and source electrode Ps54 connects VDD; The grid Ng43 of the 43 NMOS pipe connects CK, and drain electrode Nd43 connects the drain electrode Pd43 of the 43 PMOS pipe; The grid Ng44 of the 44 NMOS pipe connects the drain electrode Nd43 of the 43 NMOS pipe, and drain electrode Nd44 connects the drain electrode Pd44 of the 44 PMOS pipe, and source electrode Ns44 connects VSS; The grid Ng45 of the 45 NMOS pipe connects the drain electrode Nd44 of the 44 NMOS pipe, and drain electrode Nd45 connects the drain electrode Pd45 of the 45 PMOS pipe, and source electrode Ns45 connects VSS; The grid Ng46 of the 46 NMOS pipe connects the drain electrode Nd45 of the 45 NMOS pipe, and drain electrode Nd46 connects the drain electrode Pd46 of the 46 PMOS pipe, and source electrode Ns46 connects VSS; The grid Ng47 of the 47 NMOS pipe connects the drain electrode Nd46 of the 46 NMOS pipe, and source electrode Ns47 connects the drain electrode Nd48 of the 48 NMOS pipe, and drain electrode connects cn1; The grid Ng48 of the 48 NMOS pipe connects CK, and drain electrode Nd48 connects the source electrode Ns47 of the 47 NMOS pipe, and source electrode Ns48 connects VSS; The grid Ng49 of the 49 NMOS pipe connects the drain electrode Nd46 of the 46 NMOS pipe, and source electrode Ns49 connects the drain electrode Nd50 of the 50 NMOS pipe, and drain electrode connects cn2; The grid Ng50 of the 50 NMOS pipe connects CK, and drain electrode Nd50 connects the source electrode Ns49 of the 49 NMOS pipe, and source electrode Ns50 connects VSS; The grid Ng51 of the 51 NMOS pipe connects output c1, and drain electrode Nd51 connects output cn1, and source electrode Ns51 connects the drain electrode Nd52 of the 52 NMOS pipe; The grid Ng52 of the 52 NMOS pipe connects output c1, and drain electrode Nd52 connects the 51 NMOS pipe source electrode Ns51, and source electrode Ns52 connects VSS; The grid Ng53 of the 53 NMOS pipe connects output c2, and drain electrode Nd53 connects output cn2, and source electrode Ns53 connects the 54 NMOS pipe drain electrode Nd54; The grid Ng54 of the 54 NMOS pipe connects output c2, and drain electrode Nd54 connects the 53 NMOS pipe source electrode Ns53, and source electrode Ns54 connects VSS; The grid Ng55 of the 55 NMOS pipe connects output cn1, and drain electrode Nd55 connects output c1, and source electrode Ns55 connects VSS; The grid Ng56 of the 56 NMOS pipe connects output cn2, and drain electrode Nd56 connects output c2, and source electrode Ns56 connects VSS.
Buffer circuits has an input and an output, and input is D, and output is D1.Buffer circuit is made up of eight PMOS pipes and eight NMOS pipes, and in buffer circuit, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg1 of the one PMOS pipe connects input D and is connected with the grid Ng1 of a NMOS pipe, and drain electrode Pd1 connects the drain electrode Ng1 of a NMOS pipe, and source electrode Ps1 connects VDD; The grid Pg2 of the 2nd PMOS pipe connects the drain electrode Pd1 of a PMOS pipe, and drain electrode Pd2 connects the drain electrode Nd2 of the 2nd NMOS pipe, and source electrode Ps2 connects VDD; The grid Pg3 of the 3rd PMOS pipe connects the drain electrode Pd2 of the 2nd PMOS pipe, and drain electrode Pd3 connects the drain electrode Nd3 of the 3rd NMOS pipe, and source electrode Ps3 connects VDD; The grid Pg4 of the 4th PMOS pipe connects the drain electrode Pd3 of the 3rd PMOS pipe, and drain electrode Pd4 connects the drain electrode Nd4 of the 4th NMOS pipe, and source electrode Ps4 connects VDD; The grid Pg5 of the 5th PMOS pipe connects the drain electrode Pd4 of the 4th PMOS pipe, and drain electrode Pd5 connects the drain electrode Nd5 of the 5th NMOS pipe, and source electrode Ps5 connects VDD; The grid Pg6 of the 6th PMOS pipe connects the drain electrode Pd5 of the 5th PMOS pipe, and drain electrode Pd6 connects the drain electrode Nd6 of the 6th NMOS pipe, and source electrode Ps6 connects VDD; The grid Pg7 of the 7th PMOS pipe connects the drain electrode Pd6 of the 6th PMOS pipe, and drain electrode Pd7 connects the drain electrode Nd7 of the 7th NMOS pipe, and source electrode Ps7 connects VDD; The grid Pg8 of the 8th PMOS pipe connects the drain electrode Pd7 of the 7th PMOS pipe, and drain electrode Pd8 connects the drain electrode Nd8 of the 8th NMOS pipe the output D1 as buffer, and source electrode Ps8 connects VDD; The grid Ng1 of the one NMOS pipe connects Pg1, and drain electrode Nd1 connects Pd1, and source electrode Ns1 connects VSS; The grid Ng2 of the 2nd NMOS pipe connects the drain electrode Nd1 of a NMOS pipe, and drain electrode Nd2 connects Pd2, and source electrode Ns2 connects VSS; The grid Ng3 of the 3rd NMOS pipe connects the drain electrode Nd2 of the 2nd NMOS pipe, and drain electrode Nd3 connects Pd3, and source electrode Ns3 connects VSS; The grid Ng4 of the 4th NMOS pipe connects the drain electrode Nd3 of the 3rd NMOS pipe, and drain electrode Nd4 connects Pd4, and source electrode Ns4 connects VSS; The grid Ng5 of the 5th NMOS pipe connects the drain electrode Nd4 of the 4th NMOS pipe, and drain electrode Nd5 connects Pd5, and source electrode Ns5 connects VSS; The grid Ng6 of the 6th NMOS pipe connects the drain electrode Nd5 of the 5th NMOS pipe, and drain electrode Nd6 connects Pd6, and source electrode Ns6 connects VSS; The grid Ng7 of the 7th NMOS pipe connects the drain electrode Nd6 of the 6th NMOS pipe, and drain electrode Nd7 connects Pd7, and source electrode Ns7 connects VSS; The grid Ng8 of the 8th NMOS pipe connects the drain electrode Nd7 of the 7th NMOS pipe, and drain electrode Nd8 connects Pd8, and source electrode Ns8 connects VSS.
Reset buffer circuit has an input and two outputs, and input is RN, and output is _ RN1_, _ RN2_.Reset buffer circuit is made up of 8 NMOS pipes and 8 PMOS pipes, and in reset buffer circuit, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg35 of the 35 PMOS pipe connects RN, and drain electrode Pd35 connects the drain electrode Nd35 of the 35 NMOS pipe, and source electrode Ps35 connects power vd D; The grid Pg36 of the 36 PMOS pipe connects the drain electrode Pd35 of the 35 PMOS pipe, and drain electrode Pd36 connects the drain electrode Nd36 of the 36 NMOS pipe, and source electrode Ps36 connects power vd D; The grid Pg37 of the 37 PMOS pipe connects the drain electrode Pd36 of the 36 PMOS pipe, and drain electrode Pd37 connects the drain electrode Nd37 of the 37 NMOS pipe, and source electrode Ps37 connects power vd D; The grid Pg38 of the 38 PMOS pipe connects the drain electrode Pd37 of the 37 PMOS pipe, and drain electrode Pd38 connects the drain electrode Nd38 of the 38 NMOS pipe, and source electrode Ps38 connects power vd D; The grid Pg39 of the 39 PMOS pipe connects RN, and drain electrode Pd39 connects the source electrode Ps40 of the 40 PMOS pipe, and source electrode Ps39 connects VDD; The grid Pg40 of the 40 PMOS pipe connects the drain electrode Pd38 of the 38 PMOS pipe, and drain electrode Pd40 connects the drain electrode Nd39 of the 39 NMOS pipe, and as an output _ RN1_ of reset buffer circuit, source electrode Ps40 connects Pd39; The grid Pg41 of the 41 PMOS pipe connects RN, and drain electrode Pd41 connects the source electrode Ps42 of the 42 PMOS pipe, and source electrode Ps41 connects VDD; The grid Pg42 of the 42 PMOS pipe connects the drain electrode Pd38 of the 38 PMOS pipe, and drain electrode Pd42 connects the drain electrode Nd41 of the 41 NMOS pipe, and as an output _ RN2_ of reset buffer circuit, source electrode Ps42 connects Pd41; The grid Ng35 of the 35 NMOS pipe connects RN, and drain electrode Nd35 connects the drain electrode Pd35 of the 35 PMOS pipe, and source electrode Ns35 connects VSS; The grid Ng36 of the 36 NMOS pipe connects the drain electrode Nd35 of the 35 NMOS pipe, and drain electrode Nd36 connects the drain electrode Pd36 of the 36 PMOS pipe, and source electrode Ns36 connects VSS; The grid Ng37 of the 37 NMOS pipe connects the drain electrode Nd36 of the 36 NMOS pipe, and drain electrode Nd37 connects the drain electrode Pd37 of the 37 PMOS pipe, and source electrode Ns37 connects VSS; The grid Ng38 of the 38 NMOS pipe connects the drain electrode Nd37 of the 37 NMOS pipe, and drain electrode Nd38 connects the drain electrode Pd38 of the 38 PMOS pipe, and source electrode Ns38 connects VSS; The grid Ng39 of the 39 NMOS pipe connects the drain electrode Nd38 of the 38 NMOS pipe, and source electrode Ns39 connects the drain electrode Nd40 of the 40 NMOS pipe, drain electrode Nd39 connection _ RN1_; The grid Ng40 of the 40 NMOS pipe connects RN, and drain electrode Nd40 connects the source electrode Ns39 of the 39 NMOS pipe, and source electrode Ns40 connects VSS; The grid Ng41 of the 41 NMOS pipe connects the drain electrode Nd38 of the 38 NMOS pipe, and source electrode Ns41 connects the drain electrode Nd42 of the 42 NMOS pipe, drain electrode Nd41 connection _ RN2_; The grid Ng42 of the 42 NMOS pipe connects RN, and drain electrode Nd42 connects the source electrode Ns41 of the 41 NMOS pipe, and source electrode Ns42 connects VSS.
Main latch has eight inputs and two outputs, input and D, and D1, c1, c2, cn1, cn2, _ RN1_, _ RN2_ is connected; Output is m1, m1r.Main latch is made up of 14 PMOS and ten four NMOSs, and in main latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg9 of the 9th PMOS pipe connects D, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS, and source electrode Ps9 connects VDD; The grid Pg10 of the tenth PMOS connects D1, and source electrode Ps10 connects the drain electrode Pd9 of the 9th PMOS pipe, and drain electrode Pd10 connects the source electrode Ps11 of the 11 PMOS pipe; The grid Pg11 of the 11 PMOS pipe connects c1, and source electrode Ps11 connects the drain electrode Pd10 of the tenth PMOS pipe, and drain electrode Pd11 connects the 9th NMOS drain electrode Nd9; The grid Pg12 of the 12 PMOS connects D, and drain electrode connects the source electrode Ps13 of the 13 PMOS, and source electrode Ps12 connects VDD; The grid Pg13 of the 13 PMOS connects D1, and source electrode Ps13 connects the drain electrode Pd12 of the 12 PMOS pipe, and drain electrode Pd13 connects the source electrode Ps14 of the 14 PMOS pipe; The grid Pg14 of the 14 PMOS pipe connects c2, and source electrode Ps14 connects the drain electrode Pd13 of the 13 PMOS pipe, and drain electrode Pd14 connects the 12 NMOS drain electrode Nd12; The grid Pg15 connection _ RN1_ of the 15 PMOS pipe, drain electrode Pd15 connects the source electrode Ps16 of the 16 PMOS pipe, and source electrode Ps15 connects power vd D; The grid Pg16 of the 16 PMOS pipe connects Pd11, and drain electrode Pd16 connects the drain electrode Nd15 of the 15 NMOS pipe the output m1 as main latch, and source electrode Ps16 connects Pd15; The grid Pg17 connection _ RN2_ of the 17 PMOS pipe, drain electrode Pd17 connects Ps18, and source electrode Ps17 connects power vd D; The grid Pg18 of the 18 PMOS pipe connects Pd14, and drain electrode Pd18 connects the drain electrode Nd17 of the 17 NMOS pipe, and source electrode Ps18 connects Pd17; The grid Pg19 of the 19 PMOS pipe connects Pd18, and drain electrode Pd19 connects the source electrode Ps20 of the 20 PMOS pipe, and source electrode Ps19 connects power vd D; The grid Pg20 of the 20 PMOS pipe connects cn1, and drain electrode Pd20 connects drain electrode Nd19 and the 16 gate pmos utmost point Pg16 of the 19 NMOS pipe, and source electrode Ps20 connects Pd19; The grid Pg21 of the 21 PMOS pipe connects Pd16, and drain electrode Pd21 connects the source electrode Ps22 of the 22 PMOS pipe, and source electrode Ps21 connects power vd D; The grid Pg22 of the 22 PMOS pipe connects cn2, and drain electrode Pd22 connects drain electrode Nd21 and the 18 gate pmos utmost point Pg18 of the 21 NMOS pipe, and source electrode Ps22 connects Pd21; The grid Ng9 of the 9th NMOS pipe connects cn1, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe, and drain electrode Nd9 connects the drain electrode Pd11 of the 11 PMOS pipe; The grid Ng10 of the tenth NMOS pipe connects D1, and drain electrode Nd10 connects the source electrode Ns9 of the 9th NMOS pipe, and source electrode Ns10 connects Nd11; The grid Ng11 of the 11 NMOS pipe connects input D, and drain electrode Nd11 connects Ns10, and source electrode Ns11 connects VSS; The grid Ng12 of the 12 NMOS pipe connects cn2, and source electrode Ns12 connects the drain electrode Nd13 of the 13 NMOS pipe, and drain electrode Nd12 connects the drain electrode Pd14 of the 14 PMOS pipe; The grid Ng13 of the 13 NMOS pipe connects D1, and drain electrode Nd13 connects the source electrode Ns12 of the 12 NMOS pipe, and source electrode Ns13 connects Nd14; The grid Ng14 of the 14 NMOS pipe connects input D, and drain electrode Nd14 connects Ns13, and source electrode Ns11 connects VSS; The grid Ng15 of the 15 NMOS pipe connects Pd14, and drain electrode Nd15 connects Pd16, and source electrode Ns15 connects VSS; The grid Ng16 connection _ RN2_ of the 16 NMOS pipe, drain electrode Nd16 connects Pd16, and source electrode Ns16 connects VSS; The grid Ng17 of the 17 NMOS pipe connects Pd11, and drain electrode Nd17 connects Pd18, source electrode Ns17 ground connection VSS; The grid Ng18 connection _ RN1_ of the 18 NMOS pipe, drain electrode Nd18 connects Pd18 and as main latch output m1r, source electrode Ns18 connects VSS; The grid Ng19 of the 19 NMOS pipe connects c1, and drain electrode Nd19 connects Pd20, and source electrode Ns19 connects the drain electrode Nd20 of the 20 NMOS pipe; The grid Ng20 of the 20 NMOS pipe connects Pd16, and drain electrode Nd20 connects Ns19, source electrode Ns20 ground connection VSS; The grid Ng21 of the 21 NMOS pipe connects c2, and drain electrode Nd21 connects Pd22, and source electrode Ns21 connects the drain electrode Nd22 of the 22 NMOS pipe; The grid Ng22 of the 22 NMOS pipe connects Pd18, and drain electrode Nd22 connects Ns21, source electrode Ns22 ground connection VSS.
There are eight inputs and two outputs from latch, input and c1, c2, cn1, cn2, m1, m1r, _ RN1_, _ RN2_ is connected; Output is s1, s1r.Be made up of 12 PMOS pipes and 12 NMOS pipes from latch, from latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg23 of the 23 PMOS pipe connects m1r, and drain electrode Pd23 connects the source electrode Ps24 of the 24 PMOS pipe, and source electrode Ps23 connects power vd D; The grid Pg24 of the 24 PMOS pipe connects cn1, and drain electrode Pd24 connects the drain electrode Nd23 of the 23 NMOS pipe, and source electrode connects Pd23; The grid Pg25 of the 25 PMOS pipe connects m1, and drain electrode Pd25 connects the source electrode Ps26 of the 26 PMOS pipe, and source electrode Ps25 connects power vd D; The grid Pg26 of the 26 PMOS pipe connects cn2, and drain electrode Pd26 connects the drain electrode Nd25 of the 25 NMOS pipe, and source electrode connects Pd25; The grid Pg27 connection _ RN1_ of the 27 PMOS pipe, drain electrode Pd27 connects the source electrode Ps28 of the 28 PMOS pipe, and source electrode Ps27 connects power vd D; The grid Pg28 of the 28 PMOS pipe connects Pd24, and drain electrode Pd28 connects the drain electrode Nd27 of the 27 NMOS pipe the output s1 as main latch, and source electrode Ps28 connects Pd27; The grid Pg29 connection _ RN2_ of the 29 PMOS pipe, drain electrode Pd29 connects the source electrode Ps30 of the 30 PMOS pipe, and source electrode Ps29 connects power vd D; The grid Pg30 of the 30 PMOS pipe connects Pd26, and drain electrode Pd30 connects the drain electrode Nd29 of the 29 NMOS pipe and as the output s1r from latch, source electrode Ps30 connects Pd29; The grid Pg31 of the 31 PMOS pipe connects Pd30, and drain electrode Pd31 connects the source electrode Ps32 of the 32 PMOS pipe, and source electrode Ps31 connects power vd D; The grid Pg32 of the 32 PMOS pipe connects c1, and drain electrode Pd32 connects drain electrode Nd31 and the 28 gate pmos utmost point Pg28 of the 31 NMOS pipe, and source electrode Ps32 connects Pd31; The grid Pg33 of the 33 PMOS pipe connects Pd28, and drain electrode Pd33 connects the source electrode Ps34 of the 34 PMOS pipe, and source electrode Ps33 connects power vd D; The grid Pg34 of the 34 PMOS pipe connects c2, and drain electrode Pd34 connects drain electrode Nd33 and the 30 gate pmos utmost point Pg30 of the 33 NMOS pipe, and source electrode Ps34 connects Pd33; The grid Ng23 of the 23 NMOS pipe connects c1, and drain electrode Nd23 connects Pd24, and source electrode Ns23 connects the drain electrode Nd24 of the 24 NMOS pipe; The grid Ng24 of the 24 NMOS pipe connects m1, and drain electrode Nd24 connects Ns23, source electrode Ns24 ground connection VSS; The grid Ng25 of the 25 NMOS pipe connects c2, and drain electrode Nd25 connects Pd26, and source electrode Ns25 connects the drain electrode Nd26 of the 26 NMOS pipe; The grid Ng26 of the 26 NMOS pipe connects m1r, and drain electrode Nd26 connects Ns25, source electrode Ns26 ground connection VSS; The grid Ng27 of the 27 NMOS pipe connects Pd26, and drain electrode Nd27 connects Pd28, and source electrode Ns27 connects VSS; The grid Ng28 connection _ RN2_ of the 28 NMOS pipe, drain electrode Nd28 connects Pd28, and source electrode Ns28 connects VSS; The grid Ng29 of the 29 NMOS pipe connects Pd24, and drain electrode Nd29 connects Pd30, and source electrode Ns29 connects VSS; The grid Ng30 connection _ RN1_ of the 30 NMOS pipe, drain electrode Nd30 connects Pd30, and source electrode Ns30 connects VSS; The grid Ng31 of the 31 NMOS pipe connects cn1, and drain electrode Nd31 connects Pd32, and source electrode Ns31 connects the drain electrode Nd32 of the 32 NMOS pipe; The grid Ng32 of the 32 NMOS pipe connects Pd28, and drain electrode Nd32 connects Ns31, source electrode Ns32 ground connection VSS; The grid Ng33 of the 33 NMOS pipe connects cn2, and drain electrode Nd33 connects Pd34, and source electrode Ns33 connects the drain electrode Nd34 of the 34 NMOS pipe; The grid Ng34 of the 34 NMOS pipe connects Pd30, and drain electrode Nd34 connects Ns33, source electrode Ns34 ground connection VSS.
Output buffer has two inputs and an output, and input connects s1 and s1r, and output is Q.Output buffer is made up of two PMOS pipes and two NMOS pipes, and in output buffer, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg55 of the 55 PMOS pipe connects s1r, and drain electrode Pd55 connects the drain electrode Nd57 of the 57 NMOS pipe, and source electrode Ps55 connects power vd D; The grid Pg56 of the 56 PMOS pipe connects the drain electrode Pd55 of the 55 PMOS pipe, and drain electrode Pd56 connects the drain electrode Nd58 of the 58 NMOS pipe, and as the output Q of inverter circuit, source electrode Ps56 connects power vd D; The grid Ng57 of the 57 NMOS pipe connects s1, and drain electrode Nd57 connects the drain electrode Pd55 of the 55 PMOS pipe; The grid Ng58 of the 58 NMOS pipe connects the drain electrode Nd57 of the 57 NMOS pipe, and drain electrode Nd58 connects the drain electrode Pd56 of the 56 PMOS pipe, and source electrode Ns58 connects VSS.
The resetted d type flip flop course of work of anti-single particle overturn of the present invention and anti-single particle transient state is as follows:
The resetted d type flip flop of anti-single particle overturn of the present invention and single-ion transient state can reset at any time, and reset function is the control of reset signal input by RN.
In the time that RN is low level, the resetted d type flip flop of anti-single particle overturn of the present invention and single-ion transient state enters reset mode, main latch and from latch all by latching logic " 0 " by force, the output Q of output buffer is low level.
In the time that RN is high level, anti-single particle overturn of the present invention and single-ion transient state reset and reset d type flip flop in normal operating conditions, clock circuit receives CK, after being cushioned, it produces cn1 and the cn2 reverse with CK by the inverter circuit forming in the middle of circuit, inverter circuit by circuit end produces and CK c1 and c2 in the same way, and cn1, cn2, c1 and c2 is passed to main latch and from latch.Buffer circuits receives D, D is postponed to the D1 of rear output and D homophase, be between low period at CK, cn1 and cn2 are that high level, c1 and c2 are low level, and main latch is opened, receive D and D1, and in D and D1 may with single event transient pulse carry out filtering, then export and m1 and the m1r of D homophase by latch, from latch in preservation state, do not receive m1, the m1r of main latch output, but preserve m1, the m1r that a CK trailing edge samples; Be between high period at CK, cn1 and cn2 are that low level, c1 and c2 are high level, main latch is in preservation state, preserve m1 and the m1r of D that previous CK rising edge samples and D1 output and D homophase, open and receive output m1 and the m1r of main latch from latch, to m1 with m1r cushions and s1 and the s1r of output and m1 and m1r homophase.Output buffer all will receive output s1 and the s1r from latch at any time, to the Q of s1 and s1r buffering output and s1 and s1r homophase.
After reset buffer circuit postpones input signal by the C of duplication redundancy 2in MOS structure filtering RN may with single event transient pulse, and by output with RN homophase _ RN1_ and _ RN2_ sends into main latch and from latch, the control of the behavior that resets.
Adopt the present invention can reach following technique effect:
The anti-single particle overturn of the resetted d type flip flop of anti-single particle overturn of the present invention and single-ion transient state and anti-single particle transient state ability are better than the d type flip flop of the unguyed d type flip flop of tradition, time sampling reinforcing and the d type flip flop that traditional duplication redundancy is reinforced.The present invention transforms the unguyed d type flip flop structure of tradition, has all carried out duplication redundancy reinforcing to main latch with from latch, and for main latch and from latch C 2mOS circuit improves, and separates the C of redundancy each other 2on in MOS circuit, draw PMOS pipe and pull-down NMOS pipe, improved the primary particle inversion resistant ability of the present invention.In clock circuit He before main latch, add buffer circuits, the present invention is not made a mistake under long-term single event transient pulse; By well-designed duplication redundancy path, cut off the positive feedback loop that may be caused by single event transient pulse from latch, further increase the ability of anti-single particle transient state.Anti-single particle overturn of the present invention and single-ion transient state reset and reset d type flip flop is suitable for anti-single particle overturn and anti-single particle transient state and reinforces the standard cell lib of integrated circuit, be applied to the fields such as Aeronautics and Astronautics.
Accompanying drawing explanation
Fig. 1 is that application number is 201110323795.6 the primary particle inversion resistant d type flip flop overall logic structural representation that resets
Fig. 2 is the resetted d type flip flop overall logic structural representation of anti-single particle overturn of the present invention and single-ion transient state.
Fig. 3 is the clock circuit structural representation of the resetted d type flip flop of anti-single particle overturn of the present invention and single-ion transient state.
Fig. 4 is buffer circuit configuration schematic diagram in the resetted d type flip flop of anti-single particle overturn of the present invention and single-ion transient state.
Fig. 5 be anti-single particle overturn of the present invention and single-ion transient state can reset flip-flop in the buffer circuit structural representation that resets
Fig. 6 is main latch structural representation in the resetted d type flip flop of anti-single particle overturn of the present invention and single-ion transient state.
Fig. 7 is from latch structure schematic diagram in the resetted d type flip flop of anti-single particle overturn of the present invention and single-ion transient state.
Fig. 8 is output buffer structural representation in the resetted d type flip flop of anti-single particle overturn of the present invention and single-ion transient state.
Embodiment
Fig. 2 is the resetted d type flip flop logical construction schematic diagram of anti-single particle overturn of the present invention and single-ion transient state.The present invention is by clock circuit (as shown in Figure 3), buffer circuits (as shown in Figure 4), reset buffer circuit (as shown in Figure 5), main latch (as shown in Figure 6), form from latch (as shown in Figure 7), output buffer (as shown in Figure 8).The resetted d type flip flop of anti-single particle overturn of the present invention and single-ion transient state has three inputs and an output.Three inputs are respectively that CK is that clock signal input terminal, D are that data-signal input and RN are reset signal input; Output is Q.Clock circuit receives CK, and CK is carried out exporting respectively c1, c2 and cn1, cn2 after buffered.Buffer circuits receives D, and the D1 that it is carried out to output and D homophase after time delay.Main latch receive D and D1, c1, c2 and cn1, cn2 and _ RN1_, _ RN2_, main latch c1, c2 and cn1, cn2 and _ output m1, m1r after D and D1 being carried out to latch under the control of RN1_, _ RN2_ and processing.Receive m1, m1r and c1, c2 and cn1, cn2, _ RN1_, _ RN2_ from latch, export respectively s1, s1r after m1, m1r being carried out to latch processing from latch under the control of c1, c2 and cn1, cn2, _ RN1_, _ RN2_.Output buffer receives s1, s1r, and it is carried out exporting Q after buffered.
As shown in Figure 3, clock circuit has an input and four outputs, and input is CK, and output is c1, c2, cn1, cn2.Clock circuit is made up of 12 PMOS and ten four NMOSs, and in circuit, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg43 of the 43 PMOS pipe connects CK, and drain electrode Pd43 connects the drain electrode Nd43 of the 43 NMOS pipe, and source electrode Ps43 connects power vd D; The grid Pg44 of the 44 PMOS pipe connects the drain electrode Pd43 of the 43 PMOS pipe, and drain electrode Pd44 connects the drain electrode Nd44 of the 44 NMOS pipe, and source electrode Ps44 connects power vd D; The grid Pg45 of the 45 PMOS pipe connects the drain electrode Pd44 of the 44 PMOS pipe, and drain electrode Pd45 connects the drain electrode Nd45 of the 45 NMOS pipe, and source electrode Ps45 connects power vd D; The grid Pg46 of the 46 PMOS pipe connects the drain electrode Pd45 of the 45 PMOS pipe, and drain electrode Pd46 connects the drain electrode Nd46 of the 46 NMOS pipe, and source electrode Ps46 connects power vd D; The grid Pg47 of the 47 PMOS pipe connects CK, and drain electrode Pd47 connects the source electrode Ps48 of the 48 PMOS pipe, and source electrode Ps47 connects VDD; The grid Pg48 of the 48 PMOS pipe connects the drain electrode Pd46 of the 46 PMOS pipe, and drain electrode Pd48 connects the drain electrode Nd47 of the 47 NMOS pipe, and as an output cn1 of clock circuit; The grid Pg49 of the 49 PMOS pipe connects CK, and drain electrode Pd49 connects the source electrode Ps50 of the 50 PMOS pipe, and source electrode Ps49 connects VDD; The grid Pg50 of the 50 PMOS pipe connects the drain electrode Pd46 of the 46 PMOS pipe, and drain electrode Pd50 connects the drain electrode Nd49 of the 49 NMOS pipe, and as an output cn2 of clock circuit; The grid Pg51 of the 51 PMOS pipe is as an output c1 of clock circuit, and drain electrode Pd51 connects the drain electrode Pd48 of the 48 PMOS pipe, and source electrode Ps51 connects VDD; The grid Pg52 of the 52 PMOS pipe connects the grid Ng53 of the 53 NMOS pipe an output c2 as clock circuit, and drain electrode Pd52 connects the drain electrode Nd53 of the 53 NMOS pipe and is connected with output cn2, and source electrode Ps52 connects VDD; The grid Pg53 of the 53 PMOS pipe connects output cn1, and drain electrode Pd53 connects output c1, and source electrode Ps53 connects VDD; The grid Pg54 of the 54 PMOS pipe connects output cn2, and drain electrode Pd54 connects output c2, and source electrode Ps54 connects VDD; The grid Ng43 of the 43 NMOS pipe connects CK, and drain electrode Nd43 connects the drain electrode Pd43 of the 43 PMOS pipe; The grid Ng44 of the 44 NMOS pipe connects the drain electrode Nd43 of the 43 NMOS pipe, and drain electrode Nd44 connects the drain electrode Pd44 of the 44 PMOS pipe, and source electrode Ns44 connects VSS; The grid Ng45 of the 45 NMOS pipe connects the drain electrode Nd44 of the 44 NMOS pipe, and drain electrode Nd45 connects the drain electrode Pd45 of the 45 PMOS pipe, and source electrode Ns45 connects VSS; The grid Ng46 of the 46 NMOS pipe connects the drain electrode Nd45 of the 45 NMOS pipe, and drain electrode Nd46 connects the drain electrode Pd46 of the 46 PMOS pipe, and source electrode Ns46 connects VSS; The grid Ng47 of the 47 NMOS pipe connects the drain electrode Nd46 of the 46 NMOS pipe, and source electrode Ns47 connects the drain electrode Nd48 of the 48 NMOS pipe, and drain electrode connects cn1; The grid Ng48 of the 48 NMOS pipe connects CK, and drain electrode Nd48 connects the source electrode Ns47 of the 47 NMOS pipe, and source electrode Ns48 connects VSS; The grid Ng49 of the 49 NMOS pipe connects the drain electrode Nd46 of the 46 NMOS pipe, and source electrode Ns49 connects the drain electrode Nd50 of the 50 NMOS pipe, and drain electrode connects cn2; The grid Ng50 of the 50 NMOS pipe connects CK, and drain electrode Nd50 connects the source electrode Ns49 of the 49 NMOS pipe, and source electrode Ns50 connects VSS; The grid Ng51 of the 51 NMOS pipe connects output c1, and drain electrode Nd51 connects output cn1, and source electrode Ns51 connects the drain electrode Nd52 of the 52 NMOS pipe; The grid Ng52 of the 52 NMOS pipe connects output c1, and drain electrode Nd52 connects the 51 NMOS pipe source electrode Ns51, and source electrode Ns52 connects VSS; The grid Ng53 of the 53 NMOS pipe connects output c2, and drain electrode Nd53 connects output cn2, and source electrode Ns53 connects the 54 NMOS pipe drain electrode Nd54; The grid Ng54 of the 54 NMOS pipe connects output c2, and drain electrode Nd54 connects the 53 NMOS pipe source electrode Ns53, and source electrode Ns54 connects VSS; The grid Ng55 of the 55 NMOS pipe connects output cn1, and drain electrode Nd55 connects output c1, and source electrode Ns55 connects VSS; The grid Ng56 of the 56 NMOS pipe connects output cn2, and drain electrode Nd56 connects output c2, and source electrode Ns56 connects VSS.
As shown in Figure 4, buffer circuits has an input and an output, and input is D, and output is D1.Buffer circuit is made up of eight PMOS pipes and eight NMOS pipes, and in buffer circuit, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg1 of the one PMOS pipe connects input D and is connected with the grid Ng1 of a NMOS pipe, and drain electrode Pd1 connects the drain electrode Ng1 of a NMOS pipe, and source electrode Ps1 connects VDD; The grid Pg2 of the 2nd PMOS pipe connects the drain electrode Pd1 of a PMOS pipe, and drain electrode Pd2 connects the drain electrode Nd2 of the 2nd NMOS pipe, and source electrode Ps2 connects VDD; The grid Pg3 of the 3rd PMOS pipe connects the drain electrode Pd2 of the 2nd PMOS pipe, and drain electrode Pd3 connects the drain electrode Nd3 of the 3rd NMOS pipe, and source electrode Ps3 connects VDD; The grid Pg4 of the 4th PMOS pipe connects the drain electrode Pd3 of the 3rd PMOS pipe, and drain electrode Pd4 connects the drain electrode Nd4 of the 4th NMOS pipe, and source electrode Ps4 connects VDD; The grid Pg5 of the 5th PMOS pipe connects the drain electrode Pd4 of the 4th PMOS pipe, and drain electrode Pd5 connects the drain electrode Nd5 of the 5th NMOS pipe, and source electrode Ps5 connects VDD; The grid Pg6 of the 6th PMOS pipe connects the drain electrode Pd5 of the 5th PMOS pipe, and drain electrode Pd6 connects the drain electrode Nd6 of the 6th NMOS pipe, and source electrode Ps6 connects VDD; The grid Pg7 of the 7th PMOS pipe connects the drain electrode Pd6 of the 6th PMOS pipe, and drain electrode Pd7 connects the drain electrode Nd7 of the 7th NMOS pipe, and source electrode Ps7 connects VDD; The grid Pg8 of the 8th PMOS pipe connects the drain electrode Pd7 of the 7th PMOS pipe, and drain electrode Pd8 connects the drain electrode Nd8 of the 8th NMOS pipe the output D1 as buffer, and source electrode Ps8 connects VDD; The grid Ng1 of the one NMOS pipe connects Pg1, and drain electrode Nd1 connects Pd1, and source electrode Ns1 connects VSS; The grid Ng2 of the 2nd NMOS pipe connects the drain electrode Nd1 of a NMOS pipe, and drain electrode Nd2 connects Pd2, and source electrode Ns2 connects VSS; The grid Ng3 of the 3rd NMOS pipe connects the drain electrode Nd2 of the 2nd NMOS pipe, and drain electrode Nd3 connects Pd3, and source electrode Ns3 connects VSS; The grid Ng4 of the 4th NMOS pipe connects the drain electrode Nd3 of the 3rd NMOS pipe, and drain electrode Nd4 connects Pd4, and source electrode Ns4 connects VSS; The grid Ng5 of the 5th NMOS pipe connects the drain electrode Nd4 of the 4th NMOS pipe, and drain electrode Nd5 connects Pd5, and source electrode Ns5 connects VSS; The grid Ng6 of the 6th NMOS pipe connects the drain electrode Nd5 of the 5th NMOS pipe, and drain electrode Nd6 connects Pd6, and source electrode Ns6 connects VSS; The grid Ng7 of the 7th NMOS pipe connects the drain electrode Nd6 of the 6th NMOS pipe, and drain electrode Nd7 connects Pd7, and source electrode Ns7 connects VSS; The grid Ng8 of the 8th NMOS pipe connects the drain electrode Nd7 of the 7th NMOS pipe, and drain electrode Nd8 connects Pd8, and source electrode Ns8 connects VSS.
As shown in Figure 5, reset buffer circuit has an input and two outputs, and input is RN, and output is _ RN1_, _ RN2_.Reset buffer circuit is made up of 8 NMOS pipes and 8 PMOS pipes, and in reset buffer circuit, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg35 of the 35 PMOS pipe connects RN, and drain electrode Pd35 connects the drain electrode Nd35 of the 35 NMOS pipe, and source electrode Ps35 connects power vd D; The grid Pg36 of the 36 PMOS pipe connects the drain electrode Pd35 of the 35 PMOS pipe, and drain electrode Pd36 connects the drain electrode Nd36 of the 36 NMOS pipe, and source electrode Ps36 connects power vd D; The grid Pg37 of the 37 PMOS pipe connects the drain electrode Pd36 of the 36 PMOS pipe, and drain electrode Pd37 connects the drain electrode Nd37 of the 37 NMOS pipe, and source electrode Ps37 connects power vd D; The grid Pg38 of the 38 PMOS pipe connects the drain electrode Pd37 of the 37 PMOS pipe, and drain electrode Pd38 connects the drain electrode Nd38 of the 38 NMOS pipe, and source electrode Ps38 connects power vd D; The grid Pg39 of the 39 PMOS pipe connects RN, and drain electrode Pd39 connects the source electrode Ps40 of the 40 PMOS pipe, and source electrode Ps39 connects VDD; The grid Pg40 of the 40 PMOS pipe connects the drain electrode Pd38 of the 38 PMOS pipe, and drain electrode Pd40 connects the drain electrode Nd39 of the 39 NMOS pipe, and as an output _ RN1_ of reset buffer circuit, source electrode Ps40 connects Pd39; The grid Pg41 of the 41 PMOS pipe connects RN, and drain electrode Pd41 connects the source electrode Ps42 of the 42 PMOS pipe, and source electrode Ps41 connects VDD; The grid Pg42 of the 42 PMOS pipe connects the drain electrode Pd38 of the 38 PMOS pipe, and drain electrode Pd42 connects the drain electrode Nd41 of the 41 NMOS pipe, and as an output _ RN2_ of reset buffer circuit, source electrode Ps42 connects Pd41; The grid Ng35 of the 35 NMOS pipe connects RN, and drain electrode Nd35 connects the drain electrode Pd35 of the 35 PMOS pipe, and source electrode Ns35 connects VSS; The grid Ng36 of the 36 NMOS pipe connects the drain electrode Nd35 of the 35 NMOS pipe, and drain electrode Nd36 connects the drain electrode Pd36 of the 36 PMOS pipe, and source electrode Ns36 connects VSS; The grid Ng37 of the 37 NMOS pipe connects the drain electrode Nd36 of the 36 NMOS pipe, and drain electrode Nd37 connects the drain electrode Pd37 of the 37 PMOS pipe, and source electrode Ns37 connects VSS; The grid Ng38 of the 38 NMOS pipe connects the drain electrode Nd37 of the 37 NMOS pipe, and drain electrode Nd38 connects the drain electrode Pd38 of the 38 PMOS pipe, and source electrode Ns38 connects VSS; The grid Ng39 of the 39 NMOS pipe connects the drain electrode Nd38 of the 38 NMOS pipe, and source electrode Ns39 connects the drain electrode Nd40 of the 40 NMOS pipe, drain electrode Nd39 connection _ RN1_; The grid Ng40 of the 40 NMOS pipe connects RN, and drain electrode Nd40 connects the source electrode Ns39 of the 39 NMOS pipe, and source electrode Ns40 connects VSS; The grid Ng41 of the 41 NMOS pipe connects the drain electrode Nd38 of the 38 NMOS pipe, and source electrode Ns41 connects the drain electrode Nd42 of the 42 NMOS pipe, drain electrode Nd41 connection _ RN2_; The grid Ng42 of the 42 NMOS pipe connects RN, and drain electrode Nd42 connects the source electrode Ns41 of the 41 NMOS pipe, and source electrode Ns42 connects VSS.
As shown in Figure 6, main latch has eight inputs and two outputs, input and D, and D1, c1, c2, cn1, cn2, _ RN1_, _ RN2_ is connected; Output is m1, m1r.Main latch is made up of 14 PMOS and ten four NMOSs, and in main latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg9 of the 9th PMOS pipe connects D, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS, and source electrode Ps9 connects VDD; The grid Pg10 of the tenth PMOS connects D1, and source electrode Ps10 connects the drain electrode Pd9 of the 9th PMOS pipe, and drain electrode Pd10 connects the source electrode Ps11 of the 11 PMOS pipe; The grid Pg11 of the 11 PMOS pipe connects c1, and source electrode Ps11 connects the drain electrode Pd10 of the tenth PMOS pipe, and drain electrode Pd11 connects the 9th NMOS drain electrode Nd9; The grid Pg12 of the 12 PMOS connects D, and drain electrode connects the source electrode Ps13 of the 13 PMOS, and source electrode Ps12 connects VDD; The grid Pg13 of the 13 PMOS connects D1, and source electrode Ps13 connects the drain electrode Pd12 of the 12 PMOS pipe, and drain electrode Pd13 connects the source electrode Ps14 of the 14 PMOS pipe; The grid Pg14 of the 14 PMOS pipe connects c2, and source electrode Ps14 connects the drain electrode Pd13 of the 13 PMOS pipe, and drain electrode Pd14 connects the 12 NMOS drain electrode Nd12; The grid Pg15 connection _ RN1_ of the 15 PMOS pipe, drain electrode Pd15 connects the source electrode Ps16 of the 16 PMOS pipe, and source electrode Ps15 connects power vd D; The grid Pg16 of the 16 PMOS pipe connects Pd11, and drain electrode Pd16 connects the drain electrode Nd15 of the 15 NMOS pipe the output m1 as main latch, and source electrode Ps16 connects Pd15; The grid Pg17 connection _ RN2_ of the 17 PMOS pipe, drain electrode Pd17 connects Ps18, and source electrode Ps17 connects power vd D; The grid Pg18 of the 18 PMOS pipe connects Pd14, and drain electrode Pd18 connects the drain electrode Nd17 of the 17 NMOS pipe, and source electrode Ps18 connects Pd17; The grid Pg19 of the 19 PMOS pipe connects Pd18, and drain electrode Pd19 connects the source electrode Ps20 of the 20 PMOS pipe, and source electrode Ps19 connects power vd D; The grid Pg20 of the 20 PMOS pipe connects cn1, and drain electrode Pd20 connects drain electrode Nd19 and the 16 gate pmos utmost point Pg16 of the 19 NMOS pipe, and source electrode Ps20 connects Pd19; The grid Pg21 of the 21 PMOS pipe connects Pd16, and drain electrode Pd21 connects the source electrode Ps22 of the 22 PMOS pipe, and source electrode Ps21 connects power vd D; The grid Pg22 of the 22 PMOS pipe connects cn2, and drain electrode Pd22 connects drain electrode Nd21 and the 18 gate pmos utmost point Pg18 of the 21 NMOS pipe, and source electrode Ps22 connects Pd21; The grid Ng9 of the 9th NMOS pipe connects cn1, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe, and drain electrode Nd9 connects the drain electrode Pd11 of the 11 PMOS pipe; The grid Ng10 of the tenth NMOS pipe connects D1, and drain electrode Nd10 connects the source electrode Ns9 of the 9th NMOS pipe, and source electrode Ns10 connects Nd11; The grid Ng11 of the 11 NMOS pipe connects input D, and drain electrode Nd11 connects Ns10, and source electrode Ns11 connects VSS; The grid Ng12 of the 12 NMOS pipe connects cn2, and source electrode Ns12 connects the drain electrode Nd13 of the 13 NMOS pipe, and drain electrode Nd12 connects the drain electrode Pd14 of the 14 PMOS pipe; The grid Ng13 of the 13 NMOS pipe connects D1, and drain electrode Nd13 connects the source electrode Ns12 of the 12 NMOS pipe, and source electrode Ns13 connects Nd14; The grid Ng14 of the 14 NMOS pipe connects input D, and drain electrode Nd14 connects Ns13, and source electrode Ns11 connects VSS; The grid Ng15 of the 15 NMOS pipe connects Pd14, and drain electrode Nd15 connects Pd16, and source electrode Ns15 connects VSS; The grid Ng16 connection _ RN2_ of the 16 NMOS pipe, drain electrode Nd16 connects Pd16, and source electrode Ns16 connects VSS; The grid Ng17 of the 17 NMOS pipe connects Pd11, and drain electrode Nd17 connects Pd18, source electrode Ns17 ground connection VSS; The grid Ng18 connection _ RN1_ of the 18 NMOS pipe, drain electrode Nd18 connects Pd18 and as main latch output m1r, source electrode Ns18 connects VSS; The grid Ng19 of the 19 NMOS pipe connects c1, and drain electrode Nd19 connects Pd20, and source electrode Ns19 connects the drain electrode Nd20 of the 20 NMOS pipe; The grid Ng20 of the 20 NMOS pipe connects Pd16, and drain electrode Nd20 connects Ns19, source electrode Ns20 ground connection VSS; The grid Ng21 of the 21 NMOS pipe connects c2, and drain electrode Nd21 connects Pd22, and source electrode Ns21 connects the drain electrode Nd22 of the 22 NMOS pipe; The grid Ng22 of the 22 NMOS pipe connects Pd18, and drain electrode Nd22 connects Ns21, source electrode Ns22 ground connection VSS.
As shown in Figure 7, there are eight inputs and two outputs from latch, input and c1, c2, cn1, cn2, m1, m1r, _ RN1_, _ RN2_ is connected; Output is s1, s1r.Be made up of 12 PMOS pipes and 12 NMOS pipes from latch, from latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg23 of the 23 PMOS pipe connects m1r, and drain electrode Pd23 connects the source electrode Ps24 of the 24 PMOS pipe, and source electrode Ps23 connects power vd D; The grid Pg24 of the 24 PMOS pipe connects cn1, and drain electrode Pd24 connects the drain electrode Nd23 of the 23 NMOS pipe, and source electrode connects Pd23; The grid Pg25 of the 25 PMOS pipe connects m1, and drain electrode Pd25 connects the source electrode Ps26 of the 26 PMOS pipe, and source electrode Ps25 connects power vd D; The grid Pg26 of the 26 PMOS pipe connects cn2, and drain electrode Pd26 connects the drain electrode Nd25 of the 25 NMOS pipe, and source electrode connects Pd25; The grid Pg27 connection _ RN1_ of the 27 PMOS pipe, drain electrode Pd27 connects the source electrode Ps28 of the 28 PMOS pipe, and source electrode Ps27 connects power vd D; The grid Pg28 of the 28 PMOS pipe connects Pd24, and drain electrode Pd28 connects the drain electrode Nd27 of the 27 NMOS pipe the output s1 as main latch, and source electrode Ps28 connects Pd27; The grid Pg29 connection _ RN2_ of the 29 PMOS pipe, drain electrode Pd29 connects the source electrode Ps30 of the 30 PMOS pipe, and source electrode Ps29 connects power vd D; The grid Pg30 of the 30 PMOS pipe connects Pd26, and drain electrode Pd30 connects the drain electrode Nd29 of the 29 NMOS pipe and as the output s1r from latch, source electrode Ps30 connects Pd29; The grid Pg31 of the 31 PMOS pipe connects Pd30, and drain electrode Pd31 connects the source electrode Ps32 of the 32 PMOS pipe, and source electrode Ps31 connects power vd D; The grid Pg32 of the 32 PMOS pipe connects c1, and drain electrode Pd32 connects drain electrode Nd31 and the 28 gate pmos utmost point Pg28 of the 31 NMOS pipe, and source electrode Ps32 connects Pd31; The grid Pg33 of the 33 PMOS pipe connects Pd28, and drain electrode Pd33 connects the source electrode Ps34 of the 34 PMOS pipe, and source electrode Ps33 connects power vd D; The grid Pg34 of the 34 PMOS pipe connects c2, and drain electrode Pd34 connects drain electrode Nd33 and the 30 gate pmos utmost point Pg30 of the 33 NMOS pipe, and source electrode Ps34 connects Pd33; The grid Ng23 of the 23 NMOS pipe connects c1, and drain electrode Nd23 connects Pd24, and source electrode Ns23 connects the drain electrode Nd24 of the 24 NMOS pipe; The grid Ng24 of the 24 NMOS pipe connects m1, and drain electrode Nd24 connects Ns23, source electrode Ns24 ground connection VSS; The grid Ng25 of the 25 NMOS pipe connects c2, and drain electrode Nd25 connects Pd26, and source electrode Ns25 connects the drain electrode Nd26 of the 26 NMOS pipe; The grid Ng26 of the 26 NMOS pipe connects m1r, and drain electrode Nd26 connects Ns25, source electrode Ns26 ground connection VSS; The grid Ng27 of the 27 NMOS pipe connects Pd26, and drain electrode Nd27 connects Pd28, and source electrode Ns27 connects VSS; The grid Ng28 connection _ RN2_ of the 28 NMOS pipe, drain electrode Nd28 connects Pd28, and source electrode Ns28 connects VSS; The grid Ng29 of the 29 NMOS pipe connects Pd24, and drain electrode Nd29 connects Pd30, and source electrode Ns29 connects VSS; The grid Ng30 connection _ RN1_ of the 30 NMOS pipe, drain electrode Nd30 connects Pd30, and source electrode Ns30 connects VSS; The grid Ng31 of the 31 NMOS pipe connects cn1, and drain electrode Nd31 connects Pd32, and source electrode Ns31 connects the drain electrode Nd32 of the 32 NMOS pipe; The grid Ng32 of the 32 NMOS pipe connects Pd28, and drain electrode Nd32 connects Ns31, source electrode Ns32 ground connection VSS; The grid Ng33 of the 33 NMOS pipe connects cn2, and drain electrode Nd33 connects Pd34, and source electrode Ns33 connects the drain electrode Nd34 of the 34 NMOS pipe; The grid Ng34 of the 34 NMOS pipe connects Pd30, and drain electrode Nd34 connects Ns33, source electrode Ns34 ground connection VSS.
As shown in Figure 8, output buffer has two inputs and an output, and input connects s1 and s1r, and output is Q.Output buffer is made up of two PMOS pipes and two NMOS pipes, and in output buffer, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg55 of the 55 PMOS pipe connects s1r, and drain electrode Pd55 connects the drain electrode Nd57 of the 57 NMOS pipe, and source electrode Ps55 connects power vd D; The grid Pg56 of the 56 PMOS pipe connects the drain electrode Pd55 of the 55 PMOS pipe, and drain electrode Pd56 connects the drain electrode Nd58 of the 58 NMOS pipe, and as the output Q of inverter circuit, source electrode Ps56 connects power vd D; The grid Ng57 of the 57 NMOS pipe connects s1, and drain electrode Nd57 connects the drain electrode Pd55 of the 55 PMOS pipe; The grid Ng58 of the 58 NMOS pipe connects the drain electrode Nd57 of the 57 NMOS pipe, and drain electrode Nd58 connects the drain electrode Pd56 of the 56 PMOS pipe, and source electrode Ns58 connects VSS.
The H-13 of Beijing Institute of Atomic Energy tandem accelerator can produce LET value and be respectively 2.88MeVcm 2/ mg, 8.62MeVcm 2/ mg, 12.6MeVcm 2/ mg and 17.0MeVcm 2four kinds of ground heavy ion irradiation test environments of/mg.The primary particle inversion resistant d type flip flop that resets that the resetted d type flip flop of reinforcing in unguyed the resetted d type flip flop of the tradition of normal operating conditions, traditional duplication redundancy, resetted d type flip flop that time sampling is reinforced, Chinese patent that application number is 201110323795.6 are proposed is connected respectively the output of 1000 grades of identical reverser chains the clock frequency work with 40MHz with the resetted d type flip flop of anti-single particle overturn of the present invention and single-ion transient state, and the input of 1000 grades of reverser chains connects low level.The LET value that foregoing circuit is placed in to the generation of the H-13 of Beijing Institute of Atomic Energy tandem accelerator is respectively 2.88MeVcm 2/ mg, 8.62MeVcm 2/ mg, 12.6MeVcm 2/ mg and 21.3MeVcm 2in the ground heavy ion irradiation test environment of/mg, add up the make a mistake number of times of output of the d type flip flop that respectively can reset in the heavy ion irradiation process of each LET.The total fluence of heavy ion irradiation of every kind of LET is 10 7ion/cm 2.Primary particle inversion resistant the resetted d type flip flop that resets d type flip flop and anti-single particle overturn of the present invention and single-ion transient state that table 1 test unguyed the resetted d type flip flop of the tradition that obtains, resetted d type flip flop that traditional duplication redundancy is reinforced, resetted d type flip flop that time sampling is reinforced, Chinese patent proposition that application number is 201110323795.6 for the ground heavy particle irradiation that uses the H-13 of Beijing Institute of Atomic Energy tandem accelerator to carry out is respectively 2.88MeVcm in LET value 2/ mg, 8.62MeVcm 2/ mg, 12.6MeVcm 2/ mg and 21.3MeVcm 2the number of times of exporting makes a mistake in the ground heavy ion irradiation process of/mg.The total fluence of heavy ion irradiation of every kind of LET is 10 7ion/cm 2.Can find out from the statistics of table 1, anti-single particle overturn of the present invention and single-ion transient state ability are better than the primary particle inversion resistant d type flip flop that resets that resetted d type flip flop that resetted d type flip flop that unguyed the resetted d type flip flop of tradition, time sampling reinforce and traditional duplication redundancy reinforce, Chinese patent that application number is 201110323795.6 propose, be suitable for anti-single particle overturn and single-ion transient state and reinforce the standard cell lib of integrated circuit, be applied to the fields such as Aeronautics and Astronautics.
Table 1
Figure BDA0000434684370000251
Figure BDA0000434684370000261

Claims (7)

1. the resetted d type flip flop of anti-single particle overturn and single-ion transient state, comprise clock circuit, reset buffer circuit, main latch, from latch, output buffer, it is characterized in that the resetted d type flip flop of anti-single particle overturn and single-ion transient state also comprises buffer circuits; Main latch and from latch be redundancy reinforce latch; Main latch and from series connection before and after latch, and be all connected with clock circuit and reset buffer circuit; Main latch is also connected with buffer circuits, is also connected with output buffer from latch; There are three inputs and an output; Three inputs are respectively clock signal input terminal CK, data-signal input D and reset signal input RN; Output is Q.
2. the resetted d type flip flop of anti-single particle overturn as claimed in claim 1 and single-ion transient state, is characterized in that described clock circuit has an input and four outputs, and input is CK, and output is c1, c2, cn1, cn2; Clock circuit is made up of 12 PMOS and ten four NMOSs, and in circuit, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg43 of the 43 PMOS pipe connects CK, and drain electrode Pd43 connects the drain electrode Nd43 of the 43 NMOS pipe, and source electrode Ps43 connects power vd D; The grid Pg44 of the 44 PMOS pipe connects the drain electrode Pd43 of the 43 PMOS pipe, and drain electrode Pd44 connects the drain electrode Nd44 of the 44 NMOS pipe, and source electrode Ps44 connects power vd D; The grid Pg45 of the 45 PMOS pipe connects the drain electrode Pd44 of the 44 PMOS pipe, and drain electrode Pd45 connects the drain electrode Nd45 of the 45 NMOS pipe, and source electrode Ps45 connects power vd D; The grid Pg46 of the 46 PMOS pipe connects the drain electrode Pd45 of the 45 PMOS pipe, and drain electrode Pd46 connects the drain electrode Nd46 of the 46 NMOS pipe, and source electrode Ps46 connects power vd D; The grid Pg47 of the 47 PMOS pipe connects CK, and drain electrode Pd47 connects the source electrode Ps48 of the 48 PMOS pipe, and source electrode Ps47 connects VDD; The grid Pg48 of the 48 PMOS pipe connects the drain electrode Pd46 of the 46 PMOS pipe, and drain electrode Pd48 connects the drain electrode Nd47 of the 47 NMOS pipe, and as an output cn1 of clock circuit; The grid Pg49 of the 49 PMOS pipe connects CK, and drain electrode Pd49 connects the source electrode Ps50 of the 50 PMOS pipe, and source electrode Ps49 connects VDD; The grid Pg50 of the 50 PMOS pipe connects the drain electrode Pd46 of the 46 PMOS pipe, and drain electrode Pd50 connects the drain electrode Nd49 of the 49 NMOS pipe, and as an output cn2 of clock circuit; The grid Pg51 of the 51 PMOS pipe is as an output c1 of clock circuit, and drain electrode Pd51 connects the drain electrode Pd48 of the 48 PMOS pipe, and source electrode Ps51 connects VDD; The grid Pg52 of the 52 PMOS pipe connects the grid Ng53 of the 53 NMOS pipe an output c2 as clock circuit, and drain electrode Pd52 connects the drain electrode Nd53 of the 53 NMOS pipe and is connected with output cn2, and source electrode Ps52 connects VDD; The grid Pg53 of the 53 PMOS pipe connects output cn1, and drain electrode Pd53 connects output c1, and source electrode Ps53 connects VDD; The grid Pg54 of the 54 PMOS pipe connects output cn2, and drain electrode Pd54 connects output c2, and source electrode Ps54 connects VDD; The grid Ng43 of the 43 NMOS pipe connects CK, and drain electrode Nd43 connects the drain electrode Pd43 of the 43 PMOS pipe; The grid Ng44 of the 44 NMOS pipe connects the drain electrode Nd43 of the 43 NMOS pipe, and drain electrode Nd44 connects the drain electrode Pd44 of the 44 PMOS pipe, and source electrode Ns44 connects VSS; The grid Ng45 of the 45 NMOS pipe connects the drain electrode Nd44 of the 44 NMOS pipe, and drain electrode Nd45 connects the drain electrode Pd45 of the 45 PMOS pipe, and source electrode Ns45 connects VSS; The grid Ng46 of the 46 NMOS pipe connects the drain electrode Nd45 of the 45 NMOS pipe, and drain electrode Nd46 connects the drain electrode Pd46 of the 46 PMOS pipe, and source electrode Ns46 connects VSS; The grid Ng47 of the 47 NMOS pipe connects the drain electrode Nd46 of the 46 NMOS pipe, and source electrode Ns47 connects the drain electrode Nd48 of the 48 NMOS pipe, and drain electrode connects cn1; The grid Ng48 of the 48 NMOS pipe connects CK, and drain electrode Nd48 connects the source electrode Ns47 of the 47 NMOS pipe, and source electrode Ns48 connects VSS; The grid Ng49 of the 49 NMOS pipe connects the drain electrode Nd46 of the 46 NMOS pipe, and source electrode Ns49 connects the drain electrode Nd50 of the 50 NMOS pipe, and drain electrode connects cn2; The grid Ng50 of the 50 NMOS pipe connects CK, and drain electrode Nd50 connects the source electrode Ns49 of the 49 NMOS pipe, and source electrode Ns50 connects VSS; The grid Ng51 of the 51 NMOS pipe connects output c1, and drain electrode Nd51 connects output cn1, and source electrode Ns51 connects the drain electrode Nd52 of the 52 NMOS pipe; The grid Ng52 of the 52 NMOS pipe connects output c1, and drain electrode Nd52 connects the 51 NMOS pipe source electrode Ns51, and source electrode Ns52 connects VSS; The grid Ng53 of the 53 NMOS pipe connects output c2, and drain electrode Nd53 connects output cn2, and source electrode Ns53 connects the 54 NMOS pipe drain electrode Nd54; The grid Ng54 of the 54 NMOS pipe connects output c2, and drain electrode Nd54 connects the 53 NMOS pipe source electrode Ns53, and source electrode Ns54 connects VSS; The grid Ng55 of the 55 NMOS pipe connects output cn1, and drain electrode Nd55 connects output c1, and source electrode Ns55 connects VSS; The grid Ng56 of the 56 NMOS pipe connects output cn2, and drain electrode Nd56 connects output c2, and source electrode Ns56 connects VSS.
3. the resetted d type flip flop of anti-single particle overturn as claimed in claim 1 and single-ion transient state, is characterized in that described buffer circuits has an input and an output, and input is D, and output is D1; Buffer circuit is made up of eight PMOS pipes and eight NMOS pipes, and in buffer circuit, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg1 of the one PMOS pipe connects input D and is connected with the grid Ng1 of a NMOS pipe, and drain electrode Pd1 connects the drain electrode Ng1 of a NMOS pipe, and source electrode Ps1 connects VDD; The grid Pg2 of the 2nd PMOS pipe connects the drain electrode Pd1 of a PMOS pipe, and drain electrode Pd2 connects the drain electrode Nd2 of the 2nd NMOS pipe, and source electrode Ps2 connects VDD; The grid Pg3 of the 3rd PMOS pipe connects the drain electrode Pd2 of the 2nd PMOS pipe, and drain electrode Pd3 connects the drain electrode Nd3 of the 3rd NMOS pipe, and source electrode Ps3 connects VDD; The grid Pg4 of the 4th PMOS pipe connects the drain electrode Pd3 of the 3rd PMOS pipe, and drain electrode Pd4 connects the drain electrode Nd4 of the 4th NMOS pipe, and source electrode Ps4 connects VDD; The grid Pg5 of the 5th PMOS pipe connects the drain electrode Pd4 of the 4th PMOS pipe, and drain electrode Pd5 connects the drain electrode Nd5 of the 5th NMOS pipe, and source electrode Ps5 connects VDD; The grid Pg6 of the 6th PMOS pipe connects the drain electrode Pd5 of the 5th PMOS pipe, and drain electrode Pd6 connects the drain electrode Nd6 of the 6th NMOS pipe, and source electrode Ps6 connects VDD; The grid Pg7 of the 7th PMOS pipe connects the drain electrode Pd6 of the 6th PMOS pipe, and drain electrode Pd7 connects the drain electrode Nd7 of the 7th NMOS pipe, and source electrode Ps7 connects VDD; The grid Pg8 of the 8th PMOS pipe connects the drain electrode Pd7 of the 7th PMOS pipe, and drain electrode Pd8 connects the drain electrode Nd8 of the 8th NMOS pipe the output D1 as buffer, and source electrode Ps8 connects VDD; The grid Ng1 of the one NMOS pipe connects Pg1, and drain electrode Nd1 connects Pd1, and source electrode Ns1 connects VSS; The grid Ng2 of the 2nd NMOS pipe connects the drain electrode Nd1 of a NMOS pipe, and drain electrode Nd2 connects Pd2, and source electrode Ns2 connects VSS; The grid Ng3 of the 3rd NMOS pipe connects the drain electrode Nd2 of the 2nd NMOS pipe, and drain electrode Nd3 connects Pd3, and source electrode Ns3 connects VSS; The grid Ng4 of the 4th NMOS pipe connects the drain electrode Nd3 of the 3rd NMOS pipe, and drain electrode Nd4 connects Pd4, and source electrode Ns4 connects VSS; The grid Ng5 of the 5th NMOS pipe connects the drain electrode Nd4 of the 4th NMOS pipe, and drain electrode Nd5 connects Pd5, and source electrode Ns5 connects VSS; The grid Ng6 of the 6th NMOS pipe connects the drain electrode Nd5 of the 5th NMOS pipe, and drain electrode Nd6 connects Pd6, and source electrode Ns6 connects VSS; The grid Ng7 of the 7th NMOS pipe connects the drain electrode Nd6 of the 6th NMOS pipe, and drain electrode Nd7 connects Pd7, and source electrode Ns7 connects VSS; The grid Ng8 of the 8th NMOS pipe connects the drain electrode Nd7 of the 7th NMOS pipe, and drain electrode Nd8 connects Pd8, and source electrode Ns8 connects VSS.
4. the resetted d type flip flop of anti-single particle overturn as claimed in claim 1 and single-ion transient state, is characterized in that described reset buffer circuit has an input and two outputs, and input is RN, and output is _ RN1_, _ RN2_; Reset buffer circuit is made up of 8 NMOS pipes and 8 PMOS pipes, and in reset buffer circuit, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg35 of the 35 PMOS pipe connects RN, and drain electrode Pd35 connects the drain electrode Nd35 of the 35 NMOS pipe, and source electrode Ps35 connects power vd D; The grid Pg36 of the 36 PMOS pipe connects the drain electrode Pd35 of the 35 PMOS pipe, and drain electrode Pd36 connects the drain electrode Nd36 of the 36 NMOS pipe, and source electrode Ps36 connects power vd D; The grid Pg37 of the 37 PMOS pipe connects the drain electrode Pd36 of the 36 PMOS pipe, and drain electrode Pd37 connects the drain electrode Nd37 of the 37 NMOS pipe, and source electrode Ps37 connects power vd D; The grid Pg38 of the 38 PMOS pipe connects the drain electrode Pd37 of the 37 PMOS pipe, and drain electrode Pd38 connects the drain electrode Nd38 of the 38 NMOS pipe, and source electrode Ps38 connects power vd D; The grid Pg39 of the 39 PMOS pipe connects RN, and drain electrode Pd39 connects the source electrode Ps40 of the 40 PMOS pipe, and source electrode Ps39 connects VDD; The grid Pg40 of the 40 PMOS pipe connects the drain electrode Pd38 of the 38 PMOS pipe, and drain electrode Pd40 connects the drain electrode Nd39 of the 39 NMOS pipe, and as an output _ RN1_ of reset buffer circuit, source electrode Ps40 connects Pd39; The grid Pg41 of the 41 PMOS pipe connects RN, and drain electrode Pd41 connects the source electrode Ps42 of the 42 PMOS pipe, and source electrode Ps41 connects VDD; The grid Pg42 of the 42 PMOS pipe connects the drain electrode Pd38 of the 38 PMOS pipe, and drain electrode Pd42 connects the drain electrode Nd41 of the 41 NMOS pipe, and as an output _ RN2_ of reset buffer circuit, source electrode Ps42 connects Pd41; The grid Ng35 of the 35 NMOS pipe connects RN, and drain electrode Nd35 connects the drain electrode Pd35 of the 35 PMOS pipe, and source electrode Ns35 connects VSS; The grid Ng36 of the 36 NMOS pipe connects the drain electrode Nd35 of the 35 NMOS pipe, and drain electrode Nd36 connects the drain electrode Pd36 of the 36 PMOS pipe, and source electrode Ns36 connects VSS; The grid Ng37 of the 37 NMOS pipe connects the drain electrode Nd36 of the 36 NMOS pipe, and drain electrode Nd37 connects the drain electrode Pd37 of the 37 PMOS pipe, and source electrode Ns37 connects VSS; The grid Ng38 of the 38 NMOS pipe connects the drain electrode Nd37 of the 37 NMOS pipe, and drain electrode Nd38 connects the drain electrode Pd38 of the 38 PMOS pipe, and source electrode Ns38 connects VSS; The grid Ng39 of the 39 NMOS pipe connects the drain electrode Nd38 of the 38 NMOS pipe, and source electrode Ns39 connects the drain electrode Nd40 of the 40 NMOS pipe, drain electrode Nd39 connection _ RN1_; The grid Ng40 of the 40 NMOS pipe connects RN, and drain electrode Nd40 connects the source electrode Ns39 of the 39 NMOS pipe, and source electrode Ns40 connects VSS; The grid Ng41 of the 41 NMOS pipe connects the drain electrode Nd38 of the 38 NMOS pipe, and source electrode Ns41 connects the drain electrode Nd42 of the 42 NMOS pipe, drain electrode Nd41 connection _ RN2_; The grid Ng42 of the 42 NMOS pipe connects RN, and drain electrode Nd42 connects the source electrode Ns41 of the 41 NMOS pipe, and source electrode Ns42 connects VSS.
5. the resetted d type flip flop of anti-single particle overturn as claimed in claim 1 and single-ion transient state, is characterized in that described main latch has eight inputs and two outputs, input and D, and D1, c1, c2, cn1, cn2, _ RN1_, _ RN2_ is connected; Output is m1, m1r; Main latch is made up of 14 PMOS and ten four NMOSs, and in main latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg9 of the 9th PMOS pipe connects D, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS, and source electrode Ps9 connects VDD; The grid Pg10 of the tenth PMOS connects D1, and source electrode Ps10 connects the drain electrode Pd9 of the 9th PMOS pipe, and drain electrode Pd10 connects the source electrode Ps11 of the 11 PMOS pipe; The grid Pg11 of the 11 PMOS pipe connects c1, and source electrode Ps11 connects the drain electrode Pd10 of the tenth PMOS pipe, and drain electrode Pd11 connects the 9th NMOS drain electrode Nd9; The grid Pg12 of the 12 PMOS connects D, and drain electrode connects the source electrode Ps13 of the 13 PMOS, and source electrode Ps12 connects VDD; The grid Pg13 of the 13 PMOS connects D1, and source electrode Ps13 connects the drain electrode Pd12 of the 12 PMOS pipe, and drain electrode Pd13 connects the source electrode Ps14 of the 14 PMOS pipe; The grid Pg14 of the 14 PMOS pipe connects c2, and source electrode Ps14 connects the drain electrode Pd13 of the 13 PMOS pipe, and drain electrode Pd14 connects the 12 NMOS drain electrode Nd12; The grid Pg15 connection _ RN1_ of the 15 PMOS pipe, drain electrode Pd15 connects the source electrode Ps16 of the 16 PMOS pipe, and source electrode Ps15 connects power vd D; The grid Pg16 of the 16 PMOS pipe connects Pd11, and drain electrode Pd16 connects the drain electrode Nd15 of the 15 NMOS pipe the output m1 as main latch, and source electrode Ps16 connects Pd15; The grid Pg17 connection _ RN2_ of the 17 PMOS pipe, drain electrode Pd17 connects Ps18, and source electrode Ps17 connects power vd D; The grid Pg18 of the 18 PMOS pipe connects Pd14, and drain electrode Pd18 connects the drain electrode Nd17 of the 17 NMOS pipe, and source electrode Ps18 connects Pd17; The grid Pg19 of the 19 PMOS pipe connects Pd18, and drain electrode Pd19 connects the source electrode Ps20 of the 20 PMOS pipe, and source electrode Ps19 connects power vd D; The grid Pg20 of the 20 PMOS pipe connects cn1, and drain electrode Pd20 connects drain electrode Nd19 and the 16 gate pmos utmost point Pg16 of the 19 NMOS pipe, and source electrode Ps20 connects Pd19; The grid Pg21 of the 21 PMOS pipe connects Pd16, and drain electrode Pd21 connects the source electrode Ps22 of the 22 PMOS pipe, and source electrode Ps21 connects power vd D; The grid Pg22 of the 22 PMOS pipe connects cn2, and drain electrode Pd22 connects drain electrode Nd21 and the 18 gate pmos utmost point Pg18 of the 21 NMOS pipe, and source electrode Ps22 connects Pd21; The grid Ng9 of the 9th NMOS pipe connects cn1, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe, and drain electrode Nd9 connects the drain electrode Pd11 of the 11 PMOS pipe; The grid Ng10 of the tenth NMOS pipe connects D1, and drain electrode Nd10 connects the source electrode Ns9 of the 9th NMOS pipe, and source electrode Ns10 connects Nd11; The grid Ng11 of the 11 NMOS pipe connects input D, and drain electrode Nd11 connects Ns10, and source electrode Ns11 connects VSS; The grid Ng12 of the 12 NMOS pipe connects cn2, and source electrode Ns12 connects the drain electrode Nd13 of the 13 NMOS pipe, and drain electrode Nd12 connects the drain electrode Pd14 of the 14 PMOS pipe; The grid Ng13 of the 13 NMOS pipe connects D1, and drain electrode Nd13 connects the source electrode Ns12 of the 12 NMOS pipe, and source electrode Ns13 connects Nd14; The grid Ng14 of the 14 NMOS pipe connects input D, and drain electrode Nd14 connects Ns13, and source electrode Ns11 connects VSS; The grid Ng15 of the 15 NMOS pipe connects Pd14, and drain electrode Nd15 connects Pd16, and source electrode Ns15 connects VSS; The grid Ng16 connection _ RN2_ of the 16 NMOS pipe, drain electrode Nd16 connects Pd16, and source electrode Ns16 connects VSS; The grid Ng17 of the 17 NMOS pipe connects Pd11, and drain electrode Nd17 connects Pd18, source electrode Ns17 ground connection VSS; The grid Ng18 connection _ RN1_ of the 18 NMOS pipe, drain electrode Nd18 connects Pd18 and as main latch output m1r, source electrode Ns18 connects VSS; The grid Ng19 of the 19 NMOS pipe connects c1, and drain electrode Nd19 connects Pd20, and source electrode Ns19 connects the drain electrode Nd20 of the 20 NMOS pipe; The grid Ng20 of the 20 NMOS pipe connects Pd16, and drain electrode Nd20 connects Ns19, source electrode Ns20 ground connection VSS; The grid Ng21 of the 21 NMOS pipe connects c2, and drain electrode Nd21 connects Pd22, and source electrode Ns21 connects the drain electrode Nd22 of the 22 NMOS pipe; The grid Ng22 of the 22 NMOS pipe connects Pd18, and drain electrode Nd22 connects Ns21, source electrode Ns22 ground connection VSS.
6. the resetted d type flip flop of anti-single particle overturn as claimed in claim 1 and single-ion transient state, has eight inputs and two outputs from latch described in it is characterized in that, input and c1, and c2, cn1, cn2, m1, m1r, _ RN1_, _ RN2_ is connected; Output is s1, s1r; Be made up of 12 PMOS pipes and 12 NMOS pipes from latch, from latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg23 of the 23 PMOS pipe connects m1r, and drain electrode Pd23 connects the source electrode Ps24 of the 24 PMOS pipe, and source electrode Ps23 connects power vd D; The grid Pg24 of the 24 PMOS pipe connects cn1, and drain electrode Pd24 connects the drain electrode Nd23 of the 23 NMOS pipe, and source electrode connects Pd23; The grid Pg25 of the 25 PMOS pipe connects m1, and drain electrode Pd25 connects the source electrode Ps26 of the 26 PMOS pipe, and source electrode Ps25 connects power vd D; The grid Pg26 of the 26 PMOS pipe connects cn2, and drain electrode Pd26 connects the drain electrode Nd25 of the 25 NMOS pipe, and source electrode connects Pd25; The grid Pg27 connection _ RN1_ of the 27 PMOS pipe, drain electrode Pd27 connects the source electrode Ps28 of the 28 PMOS pipe, and source electrode Ps27 connects power vd D; The grid Pg28 of the 28 PMOS pipe connects Pd24, and drain electrode Pd28 connects the drain electrode Nd27 of the 27 NMOS pipe the output s1 as main latch, and source electrode Ps28 connects Pd27; The grid Pg29 connection _ RN2_ of the 29 PMOS pipe, drain electrode Pd29 connects the source electrode Ps30 of the 30 PMOS pipe, and source electrode Ps29 connects power vd D; The grid Pg30 of the 30 PMOS pipe connects Pd26, and drain electrode Pd30 connects the drain electrode Nd29 of the 29 NMOS pipe and as the output s1r from latch, source electrode Ps30 connects Pd29; The grid Pg31 of the 31 PMOS pipe connects Pd30, and drain electrode Pd31 connects the source electrode Ps32 of the 32 PMOS pipe, and source electrode Ps31 connects power vd D; The grid Pg32 of the 32 PMOS pipe connects c1, and drain electrode Pd32 connects drain electrode Nd31 and the 28 gate pmos utmost point Pg28 of the 31 NMOS pipe, and source electrode Ps32 connects Pd31; The grid Pg33 of the 33 PMOS pipe connects Pd28, and drain electrode Pd33 connects the source electrode Ps34 of the 34 PMOS pipe, and source electrode Ps33 connects power vd D; The grid Pg34 of the 34 PMOS pipe connects c2, and drain electrode Pd34 connects drain electrode Nd33 and the 30 gate pmos utmost point Pg30 of the 33 NMOS pipe, and source electrode Ps34 connects Pd33; The grid Ng23 of the 23 NMOS pipe connects c1, and drain electrode Nd23 connects Pd24, and source electrode Ns23 connects the drain electrode Nd24 of the 24 NMOS pipe; The grid Ng24 of the 24 NMOS pipe connects m1, and drain electrode Nd24 connects Ns23, source electrode Ns24 ground connection VSS; The grid Ng25 of the 25 NMOS pipe connects c2, and drain electrode Nd25 connects Pd26, and source electrode Ns25 connects the drain electrode Nd26 of the 26 NMOS pipe; The grid Ng26 of the 26 NMOS pipe connects m1r, and drain electrode Nd26 connects Ns25, source electrode Ns26 ground connection VSS; The grid Ng27 of the 27 NMOS pipe connects Pd26, and drain electrode Nd27 connects Pd28, and source electrode Ns27 connects VSS; The grid Ng28 connection _ RN2_ of the 28 NMOS pipe, drain electrode Nd28 connects Pd28, and source electrode Ns28 connects VSS; The grid Ng29 of the 29 NMOS pipe connects Pd24, and drain electrode Nd29 connects Pd30, and source electrode Ns29 connects VSS; The grid Ng30 connection _ RN1_ of the 30 NMOS pipe, drain electrode Nd30 connects Pd30, and source electrode Ns30 connects VSS; The grid Ng31 of the 31 NMOS pipe connects cn1, and drain electrode Nd31 connects Pd32, and source electrode Ns31 connects the drain electrode Nd32 of the 32 NMOS pipe; The grid Ng32 of the 32 NMOS pipe connects Pd28, and drain electrode Nd32 connects Ns31, source electrode Ns32 ground connection VSS; The grid Ng33 of the 33 NMOS pipe connects cn2, and drain electrode Nd33 connects Pd34, and source electrode Ns33 connects the drain electrode Nd34 of the 34 NMOS pipe; The grid Ng34 of the 34 NMOS pipe connects Pd30, and drain electrode Nd34 connects Ns33, source electrode Ns34 ground connection VSS.
7. the resetted d type flip flop of anti-single particle overturn as claimed in claim 1 and single-ion transient state, is characterized in that described output buffer has two inputs and an output, and input connects s1 and s1r, and output is Q; Output buffer is made up of two PMOS pipes and two NMOS pipes, and in output buffer, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes; The grid Pg55 of the 55 PMOS pipe connects s1r, and drain electrode Pd55 connects the drain electrode Nd57 of the 57 NMOS pipe, and source electrode Ps55 connects power vd D; The grid Pg56 of the 56 PMOS pipe connects the drain electrode Pd55 of the 55 PMOS pipe, and drain electrode Pd56 connects the drain electrode Nd58 of the 58 NMOS pipe, and as the output Q of inverter circuit, source electrode Ps56 connects power vd D; The grid Ng57 of the 57 NMOS pipe connects s1, and drain electrode Nd57 connects the drain electrode Pd55 of the 55 PMOS pipe; The grid Ng58 of the 58 NMOS pipe connects the drain electrode Nd57 of the 57 NMOS pipe, and drain electrode Nd58 connects the drain electrode Pd56 of the 56 PMOS pipe, and source electrode Ns58 connects VSS.
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CN104363005A (en) * 2014-10-20 2015-02-18 安庆师范学院 Anti-radiation D flip-flop circuit based on three mutual-latching units
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CN106059540A (en) * 2016-05-27 2016-10-26 湖南融创微电子有限公司 D trigger
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CN106712743A (en) * 2017-01-12 2017-05-24 深圳大学 Synchronous reset D trigger for preventing single event upset
CN106788341A (en) * 2017-01-12 2017-05-31 深圳大学 A kind of primary particle inversion resistant asynchronous reset d type flip flop
CN106712743B (en) * 2017-01-12 2020-03-20 深圳大学 Synchronous reset D trigger resisting single event upset
CN106788341B (en) * 2017-01-12 2020-07-10 深圳大学 Asynchronous reset D trigger resisting single event upset

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