CN104617923B - High-speed low-power-consumption multi thresholds D flip-flop - Google Patents

Abstract

The invention discloses a kind of high-speed low-power-consumption multi thresholds D flip-flop, comprising: low power consumpting controling circuit, be used for receiving low power consumption control input signal slp, output signal after buffered is carried out to low power consumption control input signal slp: sleep and nsleep; Main latch, is used for receiving data input signal d, positive input clock signal clk, anti-phase input clock signal nclk and signal sleep and nsleep; Described main latch outputs signal carry out latch process to data input signal d under the control of positive input clock signal clk, anti-phase input clock signal nclk after: qt; From latch, be used for Received signal strength qt and positive input clock signal clk, anti-phase input clock signal nclk; Described from latch under the control of positive input clock signal clk, anti-phase input clock signal nclk to signal qt carry out latch process after export respectively the first output signal q and second output signal nq.The present invention have structure simple, efficiency of transmission can be improved, reduce the advantage such as static leakage current and power consumption.

Description

High-speed low-power-consumption multi thresholds D flip-flop

Technical field

The present invention is mainly concerned with large scale integrated circuit design field, refers in particular to a kind of high-speed low-power-consumption multi thresholds D flip-flop.

Background technology

Along with improving constantly of technology, current VLSI (very large scale integrated circuit) designs has entered the deep-submicron stage.The reduction of characteristic size, will inevitably bring the reduction of the threshold voltage of MOS device, makes the exponentially form rising along with the reduction of characteristic size of the leakage current of circuit, directly causes circuit leakage current power consumption and increase sharply.The quiescent dissipation brought by leakage current can not be out in the cold.

Be operated in the system within the scope of GHz, its power consumption reaches tens w, or even more than hundreds of w.Excessive power consumption brings a series of problem, has become a significant obstacle of very lagre scale integrated circuit (VLSIC) development.High power consumption result in the high temperature of chip temperature.The fault that the rising of working temperature not only makes the various physical imperfections of circuit cause displays, and high working temperature makes the connection resistances of circuit become large, and line time delay increases, and causes serious delay failure.Meanwhile, the rising of working temperature will cause the increase of leakage current, the work of chip internal easily be lost efficacy, the lost of life etc.These reliabilities that finally result in circuit reduce greatly.There are some researches show, temperature often raises 10 ^oc, the failure rate of device just improves 2 times.

Low power design technique is through from system-level to the whole Design of Digital System process of device (technique) level.The level of integrated circuit (IC) design can be divided into following level: system-level, functional level (behavior algorithm level), Method at Register Transfer Level (structural level), gate leve (logic circuit stage), domain level (physical level).

Trigger, latch are the elementary cells forming sequential logical circuit, and the power consumption of trigger, latch consumes accounts for 15% ~ 45% of whole chip.For the phenomenon that present clock frequency is more and more higher, the power dissipation ratio of trigger, latch focuses in whole chip also more and more heavier, reduces the power consumption of trigger, has become the mandatory requirements of whole chip design.

Present process-technology-evolutions is to the deep-submicron stage, and the quiescent dissipation that leakage current brings is own through becoming very important power consumption.Reduce leakage power and will reduce leakage current exactly.Leakage current mainly comprises sub-threshold current leakage, pn ties anti-phase leakage current and breakdown current etc., and sub-threshold current leakage is wherein the main part of leakage current.

In current circuit design, the technology of several reduction leakage current is proposed.

1, sub-threshold leakage current control.Multi thresholds cmos circuit (Multi-thresholdCMOS) in a circuit, applies multiple threshold voltage to control subthreshold current, and namely in circuit, the threshold voltage of pipe has different values.Current application many twoly explains threshold voltage, namely adopts at the path of key and lowly explains value metal-oxide-semiconductor, the performance that can obtain, and adopt high threshold metal-oxide-semiconductor at auxiliary channel, to reduce sub-threshold current leakage.

2, dynamic threshold voltage CMOS (DynamicThresholdVoltageCMOS) controls.Dynamic threshold circuit changes threshold value according to the state of circuit.Be estimated and stable leakage current by the negative-feedback circuit of a self-control threshold voltage the earliest, feedback circuit mainly by regulating underlayer voltage to carry out adjusting threshold voltage, which increasing the area of circuit, too increasing certain power consumption.Subsequently, have again practitioner to propose a kind of dynamically metal-oxide-semiconductor, be connected with input by substrate, such underlayer voltage just becomes along with the change of input voltage, without the need to adjunct circuit.This circuit can reduce certain supply voltage further to reduce power consumption, but leakage current differs and reduces surely, and comparison of technology is high.

3, transistor rearrangement method.Transistor rearrangement method is an input vector of first definition circuit, and this vector can reduce the leakage current of circuit.When each door is in high leakage current time, between power supply and ground or on insert leakage current between pull-up network and pulldown network and control transistor and be used for reducing leakage current.This just needs and calculates a predetermined vector, and reduces leakage current by inserting pipe.Although can reduce certain power consumption, this pipe itself also can consume certain energy, and can increase the area of circuit and increase the complexity of circuit design.

Summary of the invention

The technical problem to be solved in the present invention is just: the technical problem existed for prior art, the invention provides the high-speed low-power-consumption multi thresholds D flip-flop that a kind of structure is simple, with low cost, can improve efficiency of transmission, reduce static leakage current and power consumption.

For solving the problems of the technologies described above, the present invention by the following technical solutions:

A kind of high-speed low-power-consumption multi thresholds D flip-flop, comprising:

Low power consumpting controling circuit, is used for receiving low power consumption control input signal slp, outputs signal respectively: sleep and nsleep to low power consumption control input signal slp after carrying out buffered;

Main latch, is used for receiving data input signal d, positive input clock signal clk, anti-phase input clock signal nclk and signal sleep and nsleep; Described main latch outputs signal carry out latch process to data input signal d under the control of positive input clock signal clk, anti-phase input clock signal nclk after: qt;

From latch, be used for Received signal strength qt and positive input clock signal clk, anti-phase input clock signal nclk; Described from latch under the control of positive input clock signal clk, anti-phase input clock signal nclk to signal qt carry out latch process after export respectively the first output signal q and second output signal nq.

As a further improvement on the present invention: described main latch is when high level is effective, nsleep is the signal of Low level effective receiving sleep, not by the control of positive input clock signal clk, anti-phase input clock signal nclk, described main latch enters sleep state, now clock control parts export positive input clock signal clk is low level " 0 ", and anti-phase input clock signal nclk is high level " 1 ".

As a further improvement on the present invention: described from latch receive sleep be high level effectively, nsleep be Low level effective signal time, not by the control of positive input clock signal clk, anti-phase input clock signal nclk, describedly enter sleep state from latch, now clock control parts export positive input clock signal clk is low level " 0 ", anti-phase input clock signal nclk is high level " 1 ", and output valve first outputs signal q and second output signal nq and remains unchanged.

As a further improvement on the present invention: described low power consumpting controling circuit has an input and two outputs, and input is slp, be low power consumption control signal, effectively high; Output is sleep, nsleep, non-for what sleep and sleep; Described low power consumpting controling circuit has the inverter of a two-stage, and wherein the inverter of the first order is made up of P1PMOS pipe and N1NMOS pipe, and its grid connects slp, exports an output nsleep as low power consumpting controling circuit; The inverter of the second level is managed by P2PMOS and N2NMOS pipe forms, and its grid connects nsleep, exports another output sleep as low power consumpting controling circuit; P1PMOS pipe is connected power supply Vdd with the substrate of P2PMOS pipe, and source electrode connects power supply Vdd; The Substrate ground Vss of N1NMOS pipe and N2NMOS pipe, source electrode connects ground Vss.

As a further improvement on the present invention: described main latch comprises:

G1 circuit is C ²mOS circuit, by high threshold PMOS P9, Low threshold PMOS LP1, Low threshold NMOS tube LN1 and high threshold NMOS tube N9 forms, Low threshold PMOS LP1, the grid connection data d of Low threshold NMOS tube LN1, the grid connection signal sleep of high threshold PMOS P9, source electrode connects the grid connection signal nsleep of Vdd, high threshold NMOS tube N9, and source electrode connects Vss; The output of G1 circuit connects the source electrode of G2CMOS transmission gate;

G2 circuit, by Low threshold PMOS LP2, Low threshold NMOS tube LN2 forms, the grid of Low threshold PMOS LP2 connects non-inverting clock input signal clk, the grid of Low threshold NMOS tube LN2 connects inversion clock input signal nclk, the drain electrode of the cmos transmission gate of G2 circuit and G3 circuit, G4 circuit, G6 circuit is connected;

G3 circuit is C ²mOS circuit, by high threshold PMOS P10, Low threshold PMOS LP3, Low threshold NMOS tube LN3 and high threshold NMOS tube N10 forms, Low threshold PMOS LP3, and the grid of Low threshold NMOS tube LN3 connects the output of the cmos transmission gate drain electrode of G2 circuit, the grid of high threshold PMOS P10 connects sleep, the grid that source electrode connects Vdd, high threshold NMOS tube N10 connects nsleep, and source electrode connects Vss; The output of G3 circuit is signal qt, is connected with the output of G4 circuit and the input of G5 circuit simultaneously;

G4 circuit, G5 circuit, G6 circuit forms a feedback holding circuit, G4 circuit, and G5 circuit is the inverter of high threshold pipe composition, and G6 circuit is the cmos transmission gate of Low threshold pipe composition; The grid input of G4 circuit connects the output of the cmos transmission gate drain electrode of G2 circuit, and the source electrode of high threshold PMOS P11 meets Vdd, and the source electrode of high threshold NMOS tube N11 meets Vss, and the output of G4 circuit is connected with signal qt, and the grid simultaneously as G5 circuit inputs; The grid of G5 circuit connects the output of G4 circuit, and the source electrode of high threshold PMOS P12 meets Vdd, and the source electrode of high threshold NMOS tube N12 meets Vss, and the output of G5 circuit is connected with the source electrode of the cmos transmission gate of G6 circuit; The source electrode of the cmos transmission gate of G6 circuit is connected with the output of G5 circuit, the output that the drain electrode of the cmos transmission gate of G6 circuit drains with the cmos transmission gate of G2 circuit is connected, be connected with the grid of the Low threshold pipe of G3 circuit simultaneously, be connected with the input of G4 circuit again, the grid of Low threshold PMOS LP4 meets inversion clock input signal nclk, and the grid of Low threshold NMOS tube LN4 meets non-inverting clock input signal clk.

As a further improvement on the present invention: describedly to comprise from latch:

G7 circuit is C ²mOS circuit, by high threshold PMOS P13, Low threshold PMOS LP5, Low threshold NMOS tube LN5 and high threshold NMOS tube N13 forms, Low threshold PMOS LP5, the grid connection data qt of Low threshold NMOS tube LN5, the grid of high threshold PMOS P13 connects sleep, the grid that source electrode connects Vdd, high threshold NMOS tube N13 connects nsleep, and source electrode connects Vss; The output of G7 circuit connects the source electrode of the cmos transmission gate of G8 circuit;

G8 circuit, by Low threshold PMOS LP6, Low threshold NMOS tube LN6 forms, the grid of Low threshold PMOS LP6 connects inversion clock input signal nclk, the grid of Low threshold NMOS tube LN6 connects non-inverting clock input signal clk, the drain electrode of the cmos transmission gate of G8 circuit and G9 circuit, G10 circuit, G12 circuit is connected;

G9 circuit is C ²mOS circuit, by high threshold PMOS P14, Low threshold PMOS LP7, Low threshold NMOS tube LN7 and high threshold NMOS tube N14 forms, Low threshold PMOS LP7, and the grid of Low threshold NMOS tube LN7 connects the output of the cmos transmission gate drain electrode of G8 circuit, the grid of high threshold PMOS P14 connects sleep, the grid that source electrode connects Vdd, high threshold NMOS tube N14 connects nsleep, and source electrode connects Vss; The output of G9 circuit is q, is connected with the output of G10 circuit and the input of G11 circuit simultaneously;

G10 circuit, G11 circuit, G12 circuit forms a feedback holding circuit, G10 circuit, and G11 circuit is the inverter of high threshold pipe composition, and G12 circuit is the cmos transmission gate of Low threshold pipe composition; The grid input of G10 circuit connects the output of the cmos transmission gate drain electrode of G8 circuit, and the source electrode of high threshold PMOS P15 meets Vdd, and the source electrode of high threshold NMOS tube N15 meets Vss, and the output of G10 circuit is connected with signal q, and the grid simultaneously as G11 circuit inputs; The grid of G11 circuit connects the output of G10 circuit, and the source electrode of high threshold PMOS P16 meets Vdd, and the source electrode of high threshold NMOS tube N16 meets Vss, and the output of G11 circuit is nq, is connected with the source electrode of the cmos transmission gate of G12 circuit simultaneously; The source electrode of the cmos transmission gate of G12 circuit is connected with the output of G11 circuit, the output that the drain electrode of the cmos transmission gate of G12 circuit drains with the cmos transmission gate of G8 circuit is connected, be connected with the grid of the Low threshold pipe of G9 circuit simultaneously, be connected with the input of G10 circuit again, the grid of Low threshold PMOS LP8 meets non-inverting clock input signal clk, and the grid of Low threshold NMOS tube LN8 meets inversion clock input signal nclk.

Compared with prior art, the invention has the advantages that: high-speed low-power-consumption multi thresholds D flip-flop of the present invention, simple and compact for structure, with low cost, be a kind of multi thresholds high speed, low-power consumption D flip-flop.The data path employing Low threshold device that the present invention is main, improves the speed of circuit.While realizing d type flip flop basic function, adopt the concept of multi thresholds, the data path, clock path of Chief use Low threshold device, improves efficiency of transmission.With high threshold device on non-critical path, reduce static leakage current, reduce power consumption, present invention reduces the voltage magnitude of clock signal clk simultaneously, namely on clock path, adopt Low threshold device, reduce the amplitude of clock voltage, effectively reduce P _swichingpower consumption.

Accompanying drawing explanation

Fig. 1 is topological structure schematic diagram of the present invention.

Fig. 2 is the structural principle schematic diagram of the present invention's low power consumpting controling circuit in embody rule example.

Fig. 3 is the structural principle schematic diagram of the present invention's main latch in embody rule example.

Fig. 4 is the present invention's structural principle schematic diagram from latch in embody rule example.

Embodiment

Below with reference to Figure of description and specific embodiment, the present invention is described in further details.

As shown in Figure 1, high-speed low-power-consumption multi thresholds D flip-flop of the present invention, comprises low power consumpting controling circuit, main latch and from latch.Trigger of the present invention has four inputs and two outputs, four inputs respectively: positive input clock signal clk, anti-phase input clock signal nclk, low power consumption control input signal slp and data input signal d; Two outputs are the first output signal q and second output signal nq respectively, and the first output signal q and second output signal nq is a pair contrary data-signal.Wherein:

Low power consumpting controling circuit, is used for receiving low power consumption control input signal slp, outputs signal respectively: sleep and nsleep to low power consumption control input signal slp after carrying out buffered.

Main latch, is used for receiving data input signal d, positive input clock signal clk, anti-phase input clock signal nclk and signal sleep and nsleep; Main latch outputs signal carry out latch process to data input signal d under the control of positive input clock signal clk, anti-phase input clock signal nclk after: qt.Main latch is to receive sleep(high level effective), nsleep(Low level effective) signal time, not by the control of positive input clock signal clk, anti-phase input clock signal nclk, main latch enters sleep state, now requiring that clock control parts export positive input clock signal clk is low level " 0 ", and anti-phase input clock signal nclk is high level " 1 ".

From latch, be used for Received signal strength qt and positive input clock signal clk, anti-phase input clock signal nclk, after latch carries out latch process to signal qt under the control of positive input clock signal clk, anti-phase input clock signal nclk, export the first output signal q and second output signal nq respectively.From latch to receive sleep(high level effective), nsleep(Low level effective) signal time, not by the control of positive input clock signal clk, anti-phase input clock signal nclk, sleep state is entered from latch, now requiring that clock control parts export positive input clock signal clk is low level " 0 ", anti-phase input clock signal nclk is high level " 1 ", and output valve first outputs signal q and second output signal nq and remains unchanged.

As shown in Figure 2, in the present embodiment, low power consumpting controling circuit has an input and two outputs, and input is slp, is low power consumption control signal, effectively high; Output is sleep, nsleep, non-for what sleep and sleep.Low power consumpting controling circuit has the inverter of a two-stage, and wherein the inverter of the first order is made up of P1PMOS pipe and N1NMOS pipe, and its grid connects slp, exports an output nsleep as low power consumpting controling circuit; The inverter of the second level is managed by P2PMOS and N2NMOS pipe forms, and its grid connects nsleep, exports another output sleep as low power consumpting controling circuit.P1PMOS pipe is connected power supply Vdd with the substrate of P2PMOS pipe, and source electrode connects power supply Vdd; The Substrate ground Vss of N1NMOS pipe and N2NMOS pipe, source electrode connects ground Vss.

As shown in Figure 3, in the present embodiment, main latch has five inputs and an output, and five inputs are d, clk, nclk, sleep, nsleep, and an output is qt.Main latch is made up of eight PMOS and eight NMOS tube, wherein has four Low threshold pipes (LP1, LP2, LP3, LP4) in eight PMOS, four high threshold pipes (P9, P10, P11, P12); Also four Low threshold pipes (LN1, LN2, LN3, LN4) are had, four high threshold pipes (N9, N10, N11, N12) in eight NMOS tube.In main latch, the substrate of all PMOS connects power supply Vdd, the Substrate ground Vss of all NMOS tube.Wherein:

G1 is a C ²mOS circuit, is made up of P9, LP1, LN1 and N9, and the grid of the grid connection data d of LP1, LN1, P9 connects sleep, and the grid that source electrode connects Vdd, N9 connects nsleep, and source electrode connects Vss; The output of G1 connects the source electrode of G2CMOS transmission gate;

G2 is made up of LP2, LN2, and drain electrode and G3, G4, the G6 of grid connection nclk, the G2CMOS transmission gate of grid connection clk, the LN2 of LP2 are connected.

G3 is a C ²mOS circuit, is made up of P10, LP3, LN3 and N10, and the grid of LP3, LN3 connects the output of G2CMOS transmission gate drain electrode, and the grid of P10 connects sleep, and the grid that source electrode connects Vdd, N10 connects nsleep, and source electrode connects Vss; The output of G3 is qt, is connected with the output of G4 and the input of G5 simultaneously.

G4, G5, G6 form a feedback holding circuit, and G4, G5 are the inverters of high threshold pipe composition, and G6 is the cmos transmission gate of Low threshold pipe composition.The grid input of G4 connects the output of G2CMOS transmission gate drain electrode, and the source electrode of P11 meets Vdd, and the source electrode of N11 meets Vss, and the output of G4 is connected with qt, and the grid simultaneously as G5 inputs.The grid of G5 connects the output of G4, and the source electrode of P12 meets Vdd, and the source electrode of N12 meets Vss, and the output of G5 is connected with the source electrode of G6CMOS transmission gate.The source electrode (input) of G6CMOS transmission gate is connected with the output of G5, the output that drain electrode (output) and the G2CMOS transmission gate of G6CMOS transmission gate drain is connected, and is connected simultaneously, is connected again with the input of G4 with the grid of the Low threshold pipe of G3, the grid of LP4 meets nclk, and the grid of LN4 meets clk.

As shown in Figure 4, in the present embodiment, have five inputs and two outputs from latch, five inputs are qt, clk, nclk, sleep, nsleep, and two outputs are q and nq.Be made up of eight PMOS and eight NMOS tube from latch, wherein have four Low threshold pipes (LP5, LP6, LP7, LP8) in eight PMOS, four high threshold pipes (P13, P14, P15, P16); Also four Low threshold pipes (LN5, LN6, LN7, LN8) are had, four high threshold pipes (N13, N14, N15, N16) in eight NMOS tube.From latch, the substrate of all PMOS connects power supply Vdd, the Substrate ground Vss of all NMOS tube.Wherein:

G7 is a C ²mOS circuit, is made up of P13, LP5, LN5 and N13, and the grid of the grid connection data qt of LP5, LN5, P13 connects sleep, and the grid that source electrode connects Vdd, N13 connects nsleep, and source electrode connects Vss; The output of G7 connects the source electrode of G8CMOS transmission gate;

G8 is made up of LP6, LN6, and drain electrode and G9, G10, the G12 of grid connection clk, the G8CMOS transmission gate of grid connection nclk, the LN6 of LP6 are connected.

G9 is a C ²mOS circuit, is made up of P14, LP7, LN7 and N14, and the grid of LP7, LN7 connects the output of G8CMOS transmission gate drain electrode, and the grid of P14 connects sleep, and the grid that source electrode connects Vdd, N14 connects nsleep, and source electrode connects Vss; The output of G9 is q, is connected with the output of G10 and the input of G11 simultaneously.

G10, G11, G12 form a feedback holding circuit, and G10, G11 are the inverters of high threshold pipe composition, and G12 is the cmos transmission gate of Low threshold pipe composition.The grid input of G10 connects the output of G8CMOS transmission gate drain electrode, and the source electrode of P15 meets Vdd, and the source electrode of N15 meets Vss, and the output of G10 is connected with q, and the grid simultaneously as G11 inputs.The grid of G11 connects the output of G10, and the source electrode of P16 meets Vdd, and the source electrode of N16 meets Vss, and the output of G11 is nq, is connected with the source electrode of G12CMOS transmission gate simultaneously.The source electrode (input) of G12CMOS transmission gate is connected with the output of G11, the output that drain electrode (output) and the G8CMOS transmission gate of G12CMOS transmission gate drain is connected, and is connected simultaneously, is connected again with the input of G10 with the grid of the Low threshold pipe of G9, the grid of LP8 meets clk, and the grid of LN8 meets nclk.

The present invention adopts multi thresholds CMOS technology to design a kind of circuit of reduction power consumption newly, especially reduces the quiescent dissipation of its circuit for D flip-flop.The leakage current of Low threshold cmos circuit is comparatively large, can be suppressed by high threshold MOS to the leakage current of Low threshold cmos circuit.In the past in cmos circuit design, often all transistors all adopt a kind of threshold value.From the path analysis to circuit structure and Signal transmissions thereof, find to adopt different threshold voltages to the transistor in different path, effectively can reduce circuit power consumption like this.As to a circuit, adopt dual threshold (dual-thresholdvoltage), namely to the path of some keys, the transistor lower by threshold value realizes, and is used for ensureing the performance of circuit; To general branch road, namely non-critical path, then realize with the transistor that threshold value is higher, to reduce the leakage current of circuit, thus reduce circuit static power consumption.

In sum, high-speed low-power-consumption multi thresholds D flip-flop of the present invention is a kind of multi thresholds high speed, low-power consumption D flip-flop, while realizing d type flip flop basic function, adopt the concept of multi thresholds, the data path, clock path of Chief use Low threshold device, improves efficiency of transmission.With high threshold device on non-critical path, reduce static leakage current, reduce power consumption.The power consumption of clock system accounts for 20% ~ 45% of whole chip power-consumption again.In cmos circuitry, total power consumption can be expressed from the next:

P _total=P _swiching+P _short+P _leakage

=α（C _L·V·V _dd·f _clk）+I _short·V _dd+I _leakage·V _dd

P _swichingswitching power loss, when signal saltus step, to the power consumption that load capacitance discharge and recharge produces.α represents that a clock cycle interior nodes voltage is from 0 to V _ddaverage transition times, C _lfor load capacitance.P _shortbe short circuit current power consumption, when signal is imperfect step, the conducting simultaneously of NMOS tube, PMOS, produces the short circuit current I of power supply to ground _short, cause short-circuit dissipation P _short.P _leakagebe leakage power, owing to there is the leakage currents such as pn junction leakage and sub-threshold value in MOS, form the leakage current from source transistor best ground, the power consumption caused thus is leakage power, also referred to as quiescent dissipation.The present invention, by reducing the voltage magnitude of clock signal clk, effectively can reduce P _swiching, V in the present invention _clk<V _dd.

Below be only the preferred embodiment of the present invention, protection scope of the present invention be not only confined to above-described embodiment, all technical schemes belonged under thinking of the present invention all belong to protection scope of the present invention.It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principles of the present invention, should be considered as protection scope of the present invention.

Claims (5)

1. a high-speed low-power-consumption multi thresholds D flip-flop, is characterized in that, comprising:

Low power consumpting controling circuit, is used for receiving low power consumption control input signal slp, outputs signal respectively: sleep and nsleep to low power consumption control input signal slp after carrying out buffered; Described low power consumpting controling circuit has an input and two outputs, and input is slp, is low power consumption control signal, effectively high; Output is sleep, nsleep, non-for what sleep and sleep; Described low power consumpting controling circuit has the inverter of a two-stage, and wherein the inverter of the first order is made up of P1PMOS pipe and N1NMOS pipe, and its grid connects slp, exports an output nsleep as low power consumpting controling circuit; The inverter of the second level is managed by P2PMOS and N2NMOS pipe forms, and its grid connects nsleep, exports another output sleep as low power consumpting controling circuit; P1PMOS pipe is connected power supply Vdd with the substrate of P2PMOS pipe, and source electrode connects power supply Vdd; The Substrate ground Vss of N1NMOS pipe and N2NMOS pipe, source electrode connects ground Vss;

Main latch, is used for receiving data input signal d, positive input clock signal clk, anti-phase input clock signal nclk and signal sleep and nsleep; Described main latch outputs signal carry out latch process to data input signal d under the control of positive input clock signal clk, anti-phase input clock signal nclk after: qt;

From latch, be used for Received signal strength qt and positive input clock signal clk, anti-phase input clock signal nclk; Described from latch under the control of positive input clock signal clk, anti-phase input clock signal nclk to signal qt carry out latch process after export respectively the first output signal q and second output signal nq.

2. high-speed low-power-consumption multi thresholds D flip-flop according to claim 1, it is characterized in that, described main latch is when high level is effective, nsleep is the signal of Low level effective receiving sleep, not by the control of positive input clock signal clk, anti-phase input clock signal nclk, described main latch enters sleep state, now clock control parts export positive input clock signal clk is low level " 0 ", and anti-phase input clock signal nclk is high level " 1 ".

3. high-speed low-power-consumption multi thresholds D flip-flop according to claim 1, it is characterized in that, described from latch receive sleep be high level effectively, nsleep be Low level effective signal time, not by the control of positive input clock signal clk, anti-phase input clock signal nclk, describedly enter sleep state from latch, now clock control parts export positive input clock signal clk is low level " 0 ", anti-phase input clock signal nclk is high level " 1 ", and output valve first outputs signal q and second output signal nq and remains unchanged.

4. the high-speed low-power-consumption multi thresholds D flip-flop according to claim 1 or 2 or 3, it is characterized in that, described main latch comprises:

G1 circuit is C ²mOS circuit, by high threshold PMOS P9, Low threshold PMOS LP1, Low threshold NMOS tube LN1 and high threshold NMOS tube N9 forms, Low threshold PMOS LP1, the grid connection data d of Low threshold NMOS tube LN1, the grid connection signal sleep of high threshold PMOS P9, source electrode connects the grid connection signal nsleep of Vdd, high threshold NMOS tube N9, and source electrode connects Vss; The output of G1 circuit connects the source electrode of G2CMOS transmission gate;

G2 circuit, by Low threshold PMOS LP2, Low threshold NMOS tube LN2 forms, the grid of Low threshold PMOS LP2 connects non-inverting clock input signal clk, the grid of Low threshold NMOS tube LN2 connects inversion clock input signal nclk, the drain electrode of the cmos transmission gate of G2 circuit and G3 circuit, G4 circuit, G6 circuit is connected;

G3 circuit is C ²mOS circuit, by high threshold PMOS P10, Low threshold PMOS LP3, Low threshold NMOS tube LN3 and high threshold NMOS tube N10 forms, Low threshold PMOS LP3, and the grid of Low threshold NMOS tube LN3 connects the output of the cmos transmission gate drain electrode of G2 circuit, the grid of high threshold PMOS P10 connects sleep, the grid that source electrode connects Vdd, high threshold NMOS tube N10 connects nsleep, and source electrode connects Vss; The output of G3 circuit is signal qt, is connected with the output of G4 circuit and the input of G5 circuit simultaneously;

G4 circuit, G5 circuit, G6 circuit forms a feedback holding circuit, G4 circuit, and G5 circuit is the inverter of high threshold pipe composition, and G6 circuit is the cmos transmission gate of Low threshold pipe composition; The grid input of G4 circuit connects the output of the cmos transmission gate drain electrode of G2 circuit, and the source electrode of high threshold PMOS P11 meets Vdd, and the source electrode of high threshold NMOS tube N11 meets Vss, and the output of G4 circuit is connected with signal qt, and the grid simultaneously as G5 circuit inputs; The grid of G5 circuit connects the output of G4 circuit, and the source electrode of high threshold PMOS P12 meets Vdd, and the source electrode of high threshold NMOS tube N12 meets Vss, and the output of G5 circuit is connected with the source electrode of the cmos transmission gate of G6 circuit; The source electrode of the cmos transmission gate of G6 circuit is connected with the output of G5 circuit, the output that the drain electrode of the cmos transmission gate of G6 circuit drains with the cmos transmission gate of G2 circuit is connected, be connected with the grid of the Low threshold pipe of G3 circuit simultaneously, be connected with the input of G4 circuit again, the grid of Low threshold PMOS LP4 meets inversion clock input signal nclk, and the grid of Low threshold NMOS tube LN4 meets non-inverting clock input signal clk.

5. the high-speed low-power-consumption multi thresholds D flip-flop according to claim 1 or 2 or 3, is characterized in that, describedly comprises from latch:

G7 circuit is C ²mOS circuit, by high threshold PMOS P13, Low threshold PMOS LP5, Low threshold NMOS tube LN5 and high threshold NMOS tube N13 forms, Low threshold PMOS LP5, the grid connection data qt of Low threshold NMOS tube LN5, the grid of high threshold PMOS P13 connects sleep, the grid that source electrode connects Vdd, high threshold NMOS tube N13 connects nsleep, and source electrode connects Vss; The output of G7 circuit connects the source electrode of the cmos transmission gate of G8 circuit;

G8 circuit, by Low threshold PMOS LP6, Low threshold NMOS tube LN6 forms, the grid of Low threshold PMOS LP6 connects inversion clock input signal nclk, the grid of Low threshold NMOS tube LN6 connects non-inverting clock input signal clk, the drain electrode of the cmos transmission gate of G8 circuit and G9 circuit, G10 circuit, G12 circuit is connected;

G9 circuit is C ²mOS circuit, by high threshold PMOS P14, Low threshold PMOS LP7, Low threshold NMOS tube LN7 and high threshold NMOS tube N14 forms, Low threshold PMOS LP7, and the grid of Low threshold NMOS tube LN7 connects the output of the cmos transmission gate drain electrode of G8 circuit, the grid of high threshold PMOS P14 connects sleep, the grid that source electrode connects Vdd, high threshold NMOS tube N14 connects nsleep, and source electrode connects Vss; The output of G9 circuit is q, is connected with the output of G10 circuit and the input of G11 circuit simultaneously;

G10 circuit, G11 circuit, G12 circuit forms a feedback holding circuit, G10 circuit, and G11 circuit is the inverter of high threshold pipe composition, and G12 circuit is the cmos transmission gate of Low threshold pipe composition; The grid input of G10 circuit connects the output of the cmos transmission gate drain electrode of G8 circuit, and the source electrode of high threshold PMOS P15 meets Vdd, and the source electrode of high threshold NMOS tube N15 meets Vss, and the output of G10 circuit is connected with signal q, and the grid simultaneously as G11 circuit inputs; The grid of G11 circuit connects the output of G10 circuit, and the source electrode of high threshold PMOS P16 meets Vdd, and the source electrode of high threshold NMOS tube N16 meets Vss, and the output of G11 circuit is nq, is connected with the source electrode of the cmos transmission gate of G12 circuit simultaneously; The source electrode of the cmos transmission gate of G12 circuit is connected with the output of G11 circuit, the output that the drain electrode of the cmos transmission gate of G12 circuit drains with the cmos transmission gate of G8 circuit is connected, be connected with the grid of the Low threshold pipe of G9 circuit simultaneously, be connected with the input of G10 circuit again, the grid of Low threshold PMOS LP8 meets non-inverting clock input signal clk, and the grid of Low threshold NMOS tube LN8 meets inversion clock input signal nclk.