CN108471303B - Programmable nanosecond timing precision pulse generator based on FPGA - Google Patents
Programmable nanosecond timing precision pulse generator based on FPGA Download PDFInfo
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- CN108471303B CN108471303B CN201810269029.8A CN201810269029A CN108471303B CN 108471303 B CN108471303 B CN 108471303B CN 201810269029 A CN201810269029 A CN 201810269029A CN 108471303 B CN108471303 B CN 108471303B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/64—Generators producing trains of pulses, i.e. finite sequences of pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00234—Layout of the delay element using circuits having two logic levels
- H03K2005/00247—Layout of the delay element using circuits having two logic levels using counters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00234—Layout of the delay element using circuits having two logic levels
- H03K2005/00254—Layout of the delay element using circuits having two logic levels using microprocessors
Abstract
A programmable nanosecond timing precision pulse generator based on an FPGA comprises the FPGA, an upper computer, a crystal oscillator circuit, a pulse amplitude control circuit and a pulse edge conditioning circuit, wherein the upper computer, the crystal oscillator circuit, the pulse amplitude control circuit and the pulse edge conditioning circuit are connected to the periphery of the FPGA, and the FPGA comprises a serial port control module, an instruction analysis module, a timing and pulse string generation module, a clock control module, an SPI control module and an OSERDES control module. The invention uses a piece of FPGA and a small amount of peripheral circuits to realize multi-channel pulse signals with nanosecond timing precision, and realizes a universal asynchronous receiving and transmitting serial port protocol in the FPGA, so that the pulse generator has a programmable control function, the pulse period, the pulse width and the pulse delay can be controlled by serial port programming, and the pulse amplitude is programmable by matching with a pulse amplitude control circuit. The circuit of the invention has small size and simple structure, can work independently and can be integrated into other systems as a modular circuit.
Description
Technical Field
The invention belongs to the technical field of electronics, and relates to a pulse generator, in particular to a programmable multi-channel nanosecond high-precision pulse generator which can output pulse signals with programmable multi-channel pulse amplitude, pulse period, pulse width and pulse delay, wherein the adjustment precision of the period, the pulse width and the pulse delay reaches 1 ns. The pulse signal source can be used as a pulse signal source and applied to the fields of signal acquisition, signal measurement and the like.
Background
The high-precision pulse generation technology has very wide application requirements in the application fields of signal measurement, signal generation, excitation signal generation and the like. In some fields of high-speed signal measurement such as optical pulse signal measurement, a high-precision pulse signal is required to be used as a sampling trigger signal to accurately control the sampling time and the sampling length of an ADC chip. Especially in the field of multi-channel sampling, the delay of multi-channel pulse signals is required to be accurate and controllable. With the increase of signal frequency, the requirements of pulse generation technology on the precision of signal pulse width, period, pulse rising edge, pulse falling edge and the like are gradually increased.
Although many instrument manufacturers provide special instruments such as high-precision pulse generators, the high price and large volume limit the application scenarios. The smaller circuit size and lower production cost have significant practical significance while ensuring high precision of pulse parameters. High-precision timing control is the key of a pulse generation circuit, the pulse time is controlled by mostly adopting a method of realizing a counter by using an MCU (microprogrammed control unit) or an FPGA (field programmable gate array), the pulse time precision is limited by the clock frequency of the counter, and the nanosecond-level timing precision is difficult to realize.
Disclosure of Invention
In order to solve the problems in the prior art, the invention aims to provide a programmable nanosecond timing precision pulse generator based on an FPGA. The invention provides a multi-channel pulse signal generator based on an output serializer/deserializer (OSERDES) technology of an FPGA (field programmable gate array), which realizes a 1ns high-precision pulse time sequence control method, and realizes a Universal Asynchronous Receiver/Transmitter (UART) serial port protocol in the FPGA, so that the pulse generator has a programmable control function, and the pulse period, the pulse width and the pulse delay can be controlled by serial port programming, and the pulse amplitude is programmable by matching with a pulse amplitude control circuit. The pulse generator is a flexible, cheap and man-machine controlled pulse generator scheme, and can expand the application range of the pulse generator and meet the application requirements of various occasions.
In order to realize the purpose of the invention, the invention adopts the following technical scheme to realize:
a programmable nanosecond timing precision pulse generator based on an FPGA comprises the FPGA, an upper computer, a crystal oscillator circuit, a pulse amplitude control circuit and a pulse edge conditioning circuit, wherein the upper computer, the crystal oscillator circuit, the pulse amplitude control circuit and the pulse edge conditioning circuit are connected to the periphery of the FPGA, and the FPGA comprises a serial port control module, an instruction analysis module, a timing and pulse string generation module, a clock control module, an SPI control module and an OSERDES control module.
The upper computer is connected with a serial port control module in the FPGA, the serial port control module is used for receiving a pulse control instruction from the upper computer, and the pulse control instruction comprises pulse amplitude, pulse period, pulse width and pulse delay among channels.
The command analysis module is connected with the serial port control module, the serial port control module outputs the pulse control command of the upper computer to the command analysis module, and the command analysis module is used for analyzing the pulse control command of the upper computer and converting the pulse control command of the upper computer into internal control words comprising pulse amplitude control words and pulse control words.
The timing and pulse train generation module is connected with the instruction analysis module, receives the pulse control words output by the instruction analysis module, and generates a corresponding 8-bit pulse train aiming at each path of pulse. The output of the timing and pulse string generation module is connected with an OSERDES control module, the OSERDES control module receives the 8-bit pulse string output by the timing and pulse string generation module, and the 8-bit pulse string is converted into a serial bit stream under the drive of a high-speed clock and is output to a pulse edge conditioning circuit. The pulse edge conditioning circuit carries out edge conditioning on the serial bit stream output by the FPGA, adjusts the pulse rising time, the pulse falling time and the pulse level and outputs the pulse.
SPI control module is connected with the analysis module of instruction, and the pulse amplitude control word of analysis module output is received to SPI control module, and SPI control module connects pulse amplitude control circuit, and SPI control module passes through SPI agreement control pulse amplitude control circuit's numerical control potentiometre, and then the output amplitude of control pulse. The pulse amplitude control circuit generates corresponding pulse amplitude control voltage under the control of the SPI control module of the FPGA and acts on the pulse edge conditioning circuit.
The crystal oscillator circuit is connected with a clock control module in the FPGA, the crystal oscillator circuit generates a 125MHz clock which is used as a working reference clock of the FPGA, the clock control module in the FPGA is responsible for generating two paths of clocks with frequency multiplication relation, namely a low-speed clock and a high-speed clock, the 1MHz low-speed clock acts on the serial port control module and the instruction analysis module, and the 1GHz high-speed clock acts on the OSERDES control module; the 125MHz clock acts on the timing and burst generation block.
As a preferred technical scheme of the invention, the FPGA with the function of OSERDES is adopted, and the highest serial clock rate of the OSERDES is not less than 1Gbps, such as Spartan 6 series FPGA of Xilinx company.
Compared with the prior art, the method has the following advantages:
(1) the invention uses one FPGA and a small amount of peripheral circuits to realize the multi-channel pulse signals with nanosecond timing precision, and the circuit has small size and simple structure. Can work independently and can be integrated into other systems as a modular circuit.
(2) The FPGA adopted by the invention is a spark 6 series low-performance FPGA, a small amount of peripheral circuit chips are matched, the whole manufacturing cost is low, and the system cost is greatly reduced while the high-precision pulse generation function is realized.
(3) The pulse amplitude, the pulse period, the pulse width and the pulse delay of the invention can be programmed through a UART serial port, the pulse output adjustable range is large, the interface is universal, the protocol is simple, and the invention is convenient for the control of an upper computer.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of the present invention.
FIG. 2 is a flow chart of an implementation of the timing and burst generation module of the present invention.
Fig. 3 is a block diagram of a pulse amplitude control circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a programmable nanosecond timing precision pulse generator based on an FPGA (field programmable gate array), wherein the timing precision of a pulse reaches 1 ns. The structural block diagram is shown in fig. 1.
The FPGA comprises a serial port control module, an instruction analysis module, a timing and pulse string generation module, a clock control module, an SPI control module and an OSERDES (serial-parallel converter) control module.
In this embodiment, the Spartan 6 series adopted by the FPGA is an FPGA with a series of low-end and low-power application scenarios, which is provided by Xilinx, and the model selected is XC6SLX9, and only 1430 clips and 11440 Flip-Flops resources are available. If internal Slices and register resources are directly used for realizing the logic of the timer, the maximum working frequency of the timer is difficult to exceed 200MHz, and the timing precision of 1ns cannot be directly realized. The invention utilizes the serial transceiving function of the OSERDES control module in Spartan 6 and adopts a method of converting parallel pulse into serial bit stream to output high-precision pulse level. The specific implementation is shown in fig. 1.
The upper computer is connected with a serial port control module in the FPGA, the serial port control module is used for receiving a pulse control instruction from the upper computer, and the pulse control instruction comprises pulse amplitude, pulse period, pulse width and pulse delay among channels.
The command analysis module is connected with the serial port control module, the serial port control module outputs the pulse control command of the upper computer to the command analysis module, and the command analysis module is used for analyzing the pulse control command of the upper computer and converting the pulse control command of the upper computer into internal control words comprising pulse amplitude control words and pulse control words.
The timing and pulse train generation module is connected with the instruction analysis module, receives the pulse control words output by the instruction analysis module, and generates a corresponding 8-bit pulse train aiming at each path of pulse. The output of the timing and pulse string generation module is connected with the OSERDES control module. The oserds control module implements a parallel burst to burst bit stream. The OSERDES control module receives the 8-bit pulse string output by the timing and pulse string generation module, converts the 8-bit pulse string into a serial bit stream under the drive of the high-speed clock and outputs the serial bit stream to the pulse edge conditioning circuit. The pulse edge conditioning circuit carries out edge conditioning on the serial bit stream output by the FPGA, adjusts the pulse rising time, the pulse falling time and the pulse level and outputs the pulse.
SPI control module is connected with the analysis module of instruction, and the pulse amplitude control word of analysis module output is received to SPI control module, and SPI control module connects pulse amplitude control circuit, and SPI control module passes through SPI agreement control pulse amplitude control circuit's numerical control potentiometre, and then the output amplitude of control pulse. The pulse amplitude control circuit generates corresponding pulse amplitude control voltage under the control of the SPI control module of the FPGA and acts on the pulse edge conditioning circuit.
The crystal oscillator circuit is connected with a clock control module in the FPGA, the crystal oscillator circuit generates a 125MHz clock which is used as a working reference clock of the FPGA, the clock control module in the FPGA is responsible for generating two paths of clocks with frequency multiplication relation, namely a low-speed clock and a high-speed clock, the 1MHz low-speed clock acts on the serial port control module and the instruction analysis module, and the 1GHz high-speed clock acts on the OSERDES control module; the 125MHz clock acts on the timing and burst generation block.
Control module for OSERDES
The Spartan 6 series FPGA integrates an OSERDES control module, and the OSERDES control module realizes parallel pulse serial pulse bit stream conversion. Wherein each IO block (IOB) comprises a 4-bit output serial-to-parallel converter OSERDES. SerDes resources of two adjacent IO blocks are configured into a master-slave mode and are cascaded to form an 8-bit SerDes, and 8-bit high-speed serial-parallel conversion is realized. A buffer phase-locked loop (BUFPLL) BUFPLL special for OSERDES input and output in the Spartan 6 series FPGA is used for providing a serial-parallel conversion working clock of 1GHz for an IO block of an OSERDES control module.
In this embodiment, an 8:1 parallel-to-serial converter is formed by cascading OSERDES control modules of two adjacent IO blocks of Spartan 6, and converts input 8-bit parallel pulse string data with a clock rate of 125MHz into a serial bit stream with an eighth rate of 1Gbps and outputs the serial bit stream to a pulse edge conditioning circuit. For example, if the input of the oserds control module is the parallel pulse data 00110000 at the clock frequency of 125MHz, the output bit stream after oserds conversion forms a pulse with the pulse width of 2ns, the period of 8ns and the duty ratio of 25%.
About instruction analysis module
The serial port control module receives a pulse control instruction from an upper computer, and the pulse control instruction comprises amplitude A of four paths of pulses1-A4Period of pulse T1-T4Width of pulse W1-W4Four-way relative delay D1-D4。
The instruction analysis module is used for analyzing the pulse control instruction of the upper computer and converting the pulse control instruction of the upper computer into internal control words including pulse amplitude control words and pulse control words.
Specifically, the instruction analysis module controls the pulse amplitude of the four-way pulse to be a word A1-A4Conversion into resistance value control word RW of numerical control potentiometer in pulse amplitude control circuit1-RW4And sending the resistance value control word to the SPI control module. The specific calculation method of the resistance value control word of the numerical control potentiometer is explained in detail in the next subsection with respect to the pulse amplitude control circuit.
The instruction analysis module is also responsible for analyzing the pulse period T1-T4Width of pulse W1-W4Four-way relative delay D1-D4And converting the digital signals into pulse control words inside the FPGA, wherein the pulse control words comprise a pulse channel delay time value PND, a pulse low level time value PNL and a pulse high level time value PNH. PND, PNL and PNH each represent clock count values clocked at 1GHz for respective time periods. For example, the pulse parameter is delay 10ns, pulse period 1ms, and pulse width duty ratio 30%, that is, pulse width 300ns, then PND is 10, PNL is 700, and PNH is 300.
Pulse edge conditioning circuit and pulse amplitude control circuit
The high-speed pulse serial bit stream output from the OSERDES control module of the FPGA is limited by the driving mode and the output capacity of the FPGA IO, the rising edge and the falling edge of a pulse signal are slow, the pulse waveform is not ideal, and a pulse edge conditioning circuit needs to be added to enable the pulse edge to be steeper. In the embodiment, a 74LVC2T45 level conversion chip produced by NXP semiconductor corporation is selected to realize the pulse edge conditioning function, and the chip is a double-bit and double-power-supply tri-state bidirectional level conversion transceiver. The bidirectional power supply supports 1.2V to 5.5V power supply, and the conversion between logic signals with different levels of standards and the highest data rate of 420Mbps can be realized. The high-speed gate circuit integrated in the edge conditioning circuit can realize the edge conditioning function similar to a Schmitt trigger circuit. The bit stream signal output from the OSERDES control module of the FPGA is connected to the A port of the 74LVC2T45 level conversion chip, and the rising edge and the falling edge of the output pulse signal of the B port of the 74LVC2T45 level conversion chip can reach 1.5ns, so that the design requirement of the high-speed pulse generator is met.
The A port of the 74LVC2T45 level conversion chip is connected with the output end of an OSERDES control module of the FPGA, and the driving voltage of the 74LVC2T45 level conversion chip is consistent with the FPGAIO voltage. The level criteria of the output signal are changed by adjusting the supply voltage of its B-port of the 74LVC2T45 level shifting chip. Considering that the output level of the B port of the chip of 74LVC2T45 has about 0.5V voltage drop with the supply voltage of the B port, 2.3V-5.5V adjustable voltage conversion needs to be realized by an on-board power supply system.
The pulse amplitude control circuit generates corresponding pulse amplitude control voltage under the control of the SPI control module of the FPGA and acts on the pulse edge conditioning circuit. The pulse amplitude control circuit is shown in fig. 3 and comprises an LT8335 switching power supply chip and peripheral circuits thereof, and a numerical control potentiometer AD 5160. The peripheral circuit of the LT8335 switching power supply chip is connected according to a single-ended primary winding inductance converter (SEPIC) power supply mode provided by a chip data manual. The SEPIC power mode allows the output voltage to be larger than, smaller than or equal to the input voltage, and can ensure that the LT8335 switching power supply chip always outputs the set voltage when the system input voltage changes in the input range of 3V-12V. An FBX pin of the LT8335 switching power supply chip is connected with a numerical control tap W end of the numerical control potentiometer AD5160, and the resistances from A, B two ports of the numerical control potentiometer AD5160 to the numerical control tap W are respectively RAWAnd RBWThe A port of the numerical control potentiometer AD5160 is connected with a resistor R1 and then connected with the output end V of the pulse amplitude control circuitOUTAnd the port B of the numerical control potentiometer AD5160 is connected with a resistor R2 and then grounded. The SPI control module of FPGA connects numerical control potentiometre AD 5160's SPI interface, and FPGA passes through SPI control module control numerical control potentiometre AD5160, can realize the resistance adjustment function.
In this embodiment, an LT8335 switching power supply chip manufactured by Linear corporation is adopted and configured as a single-ended primary inductance converter (SEPIC) power supply mode. In this mode, the calculation formula of the output voltage is:
resistance R of FBX pin end of LT8335 switching power supply chip1And R2Can change the output voltage of LT8335 switching power supply chip, and the chip manual requires R1、R2Is between 25K omega and 1M omega. This example is shown in FIG. 3 as R1、R2A digital potentiometer chip is added in part of the circuit. 256 digital control potentiometers AD5160 with SPI interfaces are selected for use in the embodiment, the end-to-end resistance is 100K omega at most, and the FPGA controls the digital control potentiometers AD5160 through the SPI control module, so that the resistance adjusting function can be realized. As shown in FIG. 3, assume that the resistances from the A, B terminals of the NC potentiometer AD5160 to the NC tap W are RAWAnd RBWThen the formula is deformed as:
wherein R isAW+RBWTaken as 100K Ω, Ra＝30KΩ，Rb52K Ω, V can be obtained by substituting the formulaOUTThe regulation range of (1.9-5.6) V meets the regulation range of 2.3-5.5V required by the system, and makes the R of the FBX pin of the LT8335 switching power supply chip1、R2The resistance value is always between 25K omega and 1M omega allowed by the chip.
After analyzing the pulse amplitude control word, an instruction analysis module in the FPGA analyzes the pulse amplitude control word according to the output voltage VOUTThe resistance value corresponding to the Vout is calculated by the calculation formula, the resistance value control word corresponding to the numerical control potentiometer is obtained according to the resistance value control calculation mode of the numerical control potentiometer AD5160, and the resistance value control word is sent to the SPI control module. The resistance value control word is converted into serial SPI data by the SPI control module, and the serial SPI data is written into a numerical control potentiometer in the pulse amplitude control circuit, so that the output voltage of the power supply is changed, and the output voltage acts on a pulse level conversion chip 74LVC2T45 of the pulse edge conditioning circuit. The pulse level conversion chip 74LVC2T45 converts the pulse signal level inputted from the A port of the 74LVC2T45 level conversion chip into the level standard input corresponding to the B port of the 74LVC2T45 level conversion chip according to the power supply voltage of the B port of the 74LVC2T45 level conversion chipAnd step adjustment of the pulse output level from 1.5V to 5V is realized.
Module for timing and burst generation
The timing and pulse train generation module mainly generates a parallel 8-bit pulse train meeting the pulse timing requirement according to three input parameters of a pulse period, a pulse width and a pulse delay. As shown in fig. 2, the specific steps are as follows:
initializing a variable delay time count CNDelay, a pulse low level count CNLow and a pulse high level count CNhigh in the FPGA, setting the initialization to be 0, and receiving an input variable transmitted by an instruction analysis module, namely a pulse channel delay time value PND, a pulse low level time value PNL and a pulse high level time value PNH by a timing and pulse train generation module.
And step two, starting to accumulate the delay time count CNDelay, wherein the working frequency of the counter is 125MHz, and the frequency of the output pulse bit stream is 1Gbps, so that each clock period CNDelay is added with 8.
And step three, stopping delay counting at the moment when the delay time counting is equal to or more than the channel delay time value, enabling output, and starting to output the all-zero low-level pulse train 8' b 00000000. Considering the timing accuracy requirement of 1ns, the initial value of the low level time count is equal to the value CNDelay minus the pulse channel delay time value PND of the current delay time counter.
And step four, starting pulse low level count CNLow accumulation, and adding 8 to the pulse low level count CNLow in each clock cycle.
And step five, stopping low level counting at the moment when the pulse low level counting CNLow is equal to or more than the low level time value, and starting to output a high level pulse string, wherein the initial value of the high level time counting is equal to the subtraction of the pulse low level counting CNLow from the pulse low level counting CNLow by the pulse low level time value PNL considering that the timing precision is required to be 1ns, and the pulse string output at the current moment is obtained after the summation or operation of eight bits of all 0 and CNhigh bit of 1 bit. For example, when PNL is 100 and CNLow is 104, the current time is high, the initial value CNHigh is 4, and the parallel burst bit 8' b00001111 is output.
And step six, starting accumulation of the pulse high level count CNhigh, and adding 8 to the pulse high level count CNhigh in each clock period.
And seventhly, stopping high level counting at the moment when the pulse high level counting CNHigh is equal to or more than the high level time value PNH, and starting to output a low level pulse string, wherein the initial value of the low level time counting is equal to the subtraction of the current pulse high level counting CNHigh and the low level time value PNH by considering that the timing precision requirement is 1ns, and the pulse string output at the current moment is obtained by the AND operation of eight bits of all 1 and a CNLow bit of 0. For example, when PNH is 200 and CNHigh is 206, the current time low time count initial value CNLow is 6, and the parallel burst bit 8' b11000000 is output. And returning to the step four, and restarting the pulse low level counting CNLow accumulation.
The pulse generation method can realize single-channel or multi-channel pulse generation, each channel corresponds to a group of OSERDES control modules, an instruction analysis module, a timing and pulse string generation module and a pulse edge conditioning circuit, wherein the OSERDES control modules, the instruction analysis module and the timing and pulse string generation module are instantiated inside the FPGA, under the condition that FPGA resources are met, more pulse channels are realized without increasing the number of the FPGA, and each pulse output is increased by one pulse edge conditioning circuit. If the multi-path pulse voltage is synchronously regulated, the system only needs one LT8335 power supply chip and one AD5160 numerical control potentiometer, and only one 74LVC2T45 is needed to be added for increasing two paths of pulse output.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (10)
1. A programmable nanosecond timing precision pulse generator based on an FPGA is characterized by comprising the FPGA, and an upper computer, a crystal oscillator circuit, a pulse amplitude control circuit and a pulse edge conditioning circuit which are connected to the periphery of the FPGA, wherein the FPGA comprises a serial port control module, an instruction analysis module, a timing and pulse string generation module, a clock control module, an SPI control module and an OSERDES control module;
the upper computer is connected with a serial port control module in the FPGA, the serial port control module is used for receiving a pulse control instruction from the upper computer, and the pulse control instruction comprises pulse amplitude, pulse period, pulse width and pulse delay among channels;
the command analysis module is connected with the serial port control module, the serial port control module outputs the pulse control command of the upper computer to the command analysis module, and the command analysis module is used for analyzing the pulse control command of the upper computer and converting the pulse control command of the upper computer into internal control words comprising pulse amplitude control words and pulse control words;
the timing and pulse train generation module is connected with the instruction analysis module, receives the pulse control words output by the instruction analysis module, and generates a corresponding 8-bit pulse train aiming at each path of pulse; the output of the timing and pulse string generation module is connected with an OSERDES control module, the OSERDES control module receives the 8-bit pulse string output by the timing and pulse string generation module, and the 8-bit pulse string is converted into a serial bit stream under the drive of a high-speed clock and is output to a pulse edge conditioning circuit; the pulse edge conditioning circuit carries out edge conditioning on the serial bit stream output by the FPGA, adjusts the pulse rising time, the pulse falling time and the pulse level and outputs the pulse;
the SPI control module is connected with the command analysis module, receives the pulse amplitude control word output by the command analysis module, is connected with the pulse amplitude control circuit, and controls a numerical control potentiometer of the pulse amplitude control circuit through an SPI protocol so as to control the output amplitude of the pulse; the pulse amplitude control circuit generates corresponding pulse amplitude control voltage under the control of the SPI control module of the FPGA and acts on the pulse edge conditioning circuit;
the crystal oscillator circuit is connected with a clock control module in the FPGA, the crystal oscillator circuit generates a 125MHz clock which is used as a working reference clock of the FPGA, the clock control module in the FPGA is responsible for generating two paths of clocks with frequency multiplication relation, namely a low-speed clock and a high-speed clock, the 1MHz low-speed clock acts on the serial port control module and the instruction analysis module, and the 1GHz high-speed clock acts on the OSERDES control module; the 125MHz clock acts on the timing and burst generation block.
2. The FPGA-based programmable nanosecond timing precision pulse generator of claim 1, wherein the FPGA is implemented as an FPGA with oserds functionality, the oserds having a maximum serial clock rate of no less than 1 Gbps.
3. The FPGA-based programmable nanosecond timing precision pulse generator according to claim 2, wherein the FPGA is a Spartan 6 series FPGA from Xilinx corporation, the Spartan 6 series FPGA integrating an OSERDES control module, and the OSERDES control module realizes parallel pulse-to-serial pulse bit stream.
4. The FPGA-based programmable nanosecond timing precision pulse generator of claim 3, wherein the Spartan 6 series FPGA comprises a 4-bit output serial-to-parallel converter OSERDES per IO block; configuring SerDes resources of two adjacent IO blocks into a master-slave mode, and cascading to form an 8-bit SerDes to realize 8-bit high-speed serial-parallel conversion; a buffer phase-locked loop which is special for OSERDES input and output in a Spartan 6 series FPGA is used for providing a serial-parallel conversion working clock of 1GHz for an IO block of an OSERDES control module.
5. The FPGA-based programmable nanosecond timing precision pulse generator of claim 4, wherein the serial port control module receives a pulse control command from the upper computer, the pulse control command comprising an amplitude A of four pulses1-A4Period of pulse T1-T4Width of pulse W1-W4Four-way relative delay D1-D4(ii) a The instruction analysis module controls a word A of the pulse amplitude of the four paths of pulses1-A4Conversion into resistance value of numerical control potentiometer in pulse amplitude control circuitControl word RW1-RW4And sending the resistance value control word to the SPI control module;
the instruction analysis module is also responsible for analyzing the pulse period T1-T4Width of pulse W1-W4Four-way relative delay D1-D4Converting the digital signals into pulse control words inside the FPGA, wherein the pulse control words comprise a pulse channel delay time value PND, a pulse low level time value PNL and a pulse high level time value PNH; the pulse channel delay time value PND, the pulse low level time value PNL and the pulse high level time value PNH all represent clock count values of clocks with corresponding time lengths of 1 GHz.
6. The FPGA-based programmable nanosecond timing precision pulse generator of claim 4, wherein the pulse edge conditioning circuit is implemented by a 74LVC2T45 level conversion chip manufactured by NXP semiconductor corporation; the bit stream signal output from the OSERDES control module of the FPGA is connected to the A port of a 74LVC2T45 level conversion chip, and the rising edge and the falling edge of the output pulse signal of the B port of the 74LVC2T45 level conversion chip can reach 1.5 ns.
7. The FPGA-based programmable nanosecond timing precision pulse generator according to claim 6, wherein the pulse amplitude control circuit comprises an LT8335 switch power supply chip and peripheral circuits thereof, and a numerical control potentiometer AD5160, wherein the peripheral circuits of the LT8335 switch power supply chip are connected according to a single-ended primary winding inductance transformation power supply mode provided by a chip data manual thereof, the single-ended primary winding inductance transformation power supply mode allows the output voltage to be greater than, less than or equal to the input voltage, and can ensure that the LT8335 switch power supply chip always outputs the set voltage when the system input voltage changes within the input range of 3V-12V;
an FBX pin of the LT8335 switching power supply chip is connected with a numerical control tap W end of the numerical control potentiometer AD5160, and the resistances from A, B two ports of the numerical control potentiometer AD5160 to the numerical control tap W are respectively RAWAnd RBWThe A port of the numerical control potentiometer AD5160 is connected with a resistor R1 and then connected with the output end V of the pulse amplitude control circuitOUTThe port B of the numerical control potentiometer AD5160 is connected with a resistor R2 and then grounded; the SPI control module of FPGA connects numerical control potentiometre AD 5160's SPI interface, and FPGA passes through SPI control module control numerical control potentiometre AD5160, can realize the resistance adjustment function.
8. The FPGA-based programmable nanosecond timing precision pulse generator of claim 7, wherein the resistances from A, B two ports of the NC potentiometer AD5160 to the NC tap W are assumed to be R respectivelyAWAnd RBWOutput voltage VOUTThe calculation formula of (2) is as follows:
wherein R isAW+RBWTaken as 100K Ω, Ra＝30KΩ，Rb52K Ω, V can be obtained by substituting the formulaOUTThe regulation range of (1.9-5.6) V meets the regulation range of 2.3-5.5V required by the system, and makes the R of the FBX pin of the LT8335 switching power supply chip1、R2The resistance value is always between 25K omega-1M omega allowed by the LT8335 switching power supply chip.
9. The FPGA-based programmable nanosecond timing precision pulse generator of claim 8, wherein the command parsing module in the FPGA parses a pulse amplitude control word according to the output voltage VOUTThe resistance value corresponding to Vout is calculated by the calculation formula, the resistance value control word corresponding to the numerical control potentiometer is obtained according to the resistance value control calculation mode of the numerical control potentiometer AD5160, and the resistance value control word is sent to the SPI control module; the SPI control module converts the resistance value control word into serial SPI data, writes the serial SPI data into a numerical control potentiometer in the pulse amplitude control circuit, further causes the output voltage of the power supply to change, and the output voltage acts on a pulse level conversion chip 74LVC2T45 of the pulse edge conditioning circuit; the pulse level conversion chip 74LVC2T45 converts the 74LVC2T45 level into the chip A according to the supply voltage of the chip B port of 74LVC2T45 level conversionThe level of a pulse signal input by a port is converted into a level standard output corresponding to a B port of a 74LVC2T45 level conversion chip, and the step adjustment of the pulse output level from 1.5V to 5V is realized.
10. The FPGA-based programmable nanosecond timing precision pulse generator of claim 9, wherein the timing and burst generation module has a workflow of:
initializing a variable delay time count CNDelay, a pulse low level count CNLow and a pulse high level count CNhigh in an FPGA, setting the initialization to be 0, and receiving an input variable transmitted by an instruction analysis module, namely a pulse channel delay time value PND, a pulse low level time value PNL and a pulse high level time value PNH by a timing and pulse train generation module;
step two, starting to delay time counting CNDelay accumulation, wherein the working frequency of the counter is 125MHz, and the frequency of the output pulse bit stream is 1Gbps, so that each clock period CNDelay is added by 8;
stopping delay counting at the moment when the delay time counting is equal to or larger than the channel delay time value, enabling output, and starting to output a low-level pulse train 8' b00000000 of all zeros; considering that the timing precision is required to be 1ns, the initial value of the low-level time counting is equal to the value CNDelay of the current delay time counter minus the pulse channel delay time value PND;
step four, starting pulse low level counting CNLow accumulation, and adding 8 to the pulse low level counting CNLow in each clock period;
step five, stopping low level counting at the moment when the pulse low level counting CNLow is equal to or more than the low level time value, and starting to output a high level pulse string, wherein the initial value of the high level time counting is equal to the subtraction of the pulse low level counting CNLow from the current pulse low level counting CNLow by the pulse low level time value PNL considering that the timing precision is required to be 1ns, and the pulse string output at the current moment is obtained after the calculation or operation of eight bits of all 0 and CNhigh bit of 1 bit;
step six, starting pulse high level count CNhigh accumulation, and adding 8 to the pulse high level count CNhigh in each clock period;
step seven, stopping high level counting at the moment when the pulse high level counting CNHigh is equal to or more than the high level time value PNH, and starting to output a low level pulse string, wherein the initial value of the low level time counting is equal to the subtraction of the current pulse high level counting CNHigh and the low level time value PNH when the timing precision requirement is 1ns, and the pulse string output at the current moment is obtained after the summation operation of eight bits of all 1 and a CNLow bit of 0; and returning to the step four, and restarting the pulse low level counting CNLow accumulation.
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| CN111277248B (en) * | 2020-04-03 | 2023-09-19 | 中国科学院近代物理研究所 | Synchronous pulse generating device with multiple working modes and working method thereof |
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