CN101777891A - Ultrafast edge step pulse generating method and generator thereof - Google Patents

Abstract

The invention relates to the technical field of electrical equipment and in particular relates to an ultrafast edge step pulse generating method and a generator thereof. In the invention, a high-precision clock reference source is used for generating a clock excitation signal exciting a high-speed comparator to generate a pulse signal of a faster edge, and a pulse amplitude adjustment circuit is used for amplifying and pre-shaping the amplitude of the pulse signal of the faster edge; then the pulse signal enters a pulse rising edge accelerating circuit, and the rising edge of the pulse signal after amplitude adjustment is further accelerated by utilizing the step recovery effect of a step recovery diode; meanwhile, the waveform of the output pulse signal is subjected to shaping and amplitude control so as to meet the requirements on the rising time, the amplitude and the overshoot pulse of a characteristic impedance tester; and finally, the pulse signal is output by using a pulse output interface. The output pulse rising time is 150ps, the amplitude is larger than 500mV, the overshoot pulse is smaller than 10 percent, and the prepulse can be ignored. The invention can discover or sense smaller impedance discontinuous distances.

Description

Ultrafast edge step pulse generating method and generator thereof

Technical field:

The present invention relates to the electric equipment technical field, particularly a kind of Ultrafast edge step pulse generating method and generator thereof that is used for the characteristic impedance tester.

Background technology:

Domain reflectometer (Time Domain Reflectometer, TDR) be a kind of important time domain tester, typical TDR equipment is made up of the external high speed step pulse generator of wide-band sampling oscillograph, has been widely used in field tests such as PCB, IC, cable and connector.At the circuit board industry, TDR detects the main the testing equipment whether characteristic impedance of PCB cabling adheres to specification, and is commonly called the characteristic impedance tester.The topmost performance index of TDR equipment are the rise time T of system _Sys, on behalf of TDR equipment, it can find or the ability of the discontinuous distance of impedance of the minimum (promptly the shortest) of perception.System's rise time (reflection rise time) was determined jointly by the rise time (incident rise time) of step pulse and the rise time (oscilloscope rise time) of sampling gate:

$T_{\mathrm{sys}}=\sqrt{{\mathrm{<figure-callout\; id="2"\; label="T\; incident"\; filenames="H200910213961XE00011.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{incident}}^{}+T_{\mathrm{scope}}^2}---\left(1\right)$

Wherein: T _SysThe expression TDR reflection rise time, i.e. TDR system rise time, the rise time of oscilloscope actual measurement just; T _IncidentExpression TDR incident rise time, the i.e. rise time of step pulse; T _ScopeThe expression TDR oscilloscope rise time.

TDR is by measuring indirect measuring distance two-way time of pulse signal, can be provided by following formula:

$L=\frac{1}{2}{V}_p\&times;T=\frac{1}{2}\frac{c}{\sqrt{{\mathrm{\&epsiv;}}_r}}\&times;T---\left(2\right)$

$V_p=\frac{c}{\sqrt{{\mathrm{\&epsiv;}}_r}}---\left(3\right)$

In the formula: T=TDR Measuring Time, the distance of L=range pulse launch point, V _pThe transmission rate of=the signal of telecommunication in medium, ε _r=pcb board material dielectric constant, the light velocity in the c=vacuum

With system's rise time substitution formula (2), can obtain the promptly I of TDR equipment minimum range resolution and survey length and be

$L_{\min }=\frac{1}{2}{V}_p\&times;T=\frac{1}{2}\frac{c}{\sqrt{{\mathrm{\&epsiv;}}_r}}\&times;T_{\mathrm{sys}}---\left(4\right)$

According to the signal integrity theory, if signal of telecommunication is from being transmitted into the rise time less than incident signal of telecommunication time interval of reflecting via the impedance discontinuity point, the reflected signal of this part incoming signal that will risen is fallen into oblivion so, TDR also just can't differentiate reflected signal like this, that is to say that TDR equipment can't differentiate this impedance discontinuity point.So can differentiate the discontinuous distance of impedance of the minimum of (or being called perception) when a step signal is transmitted on measured piece is the distance that the signal of telecommunication transmitted on measured piece in the rise time of this step signal.

In embodiments of the present invention, the rise time T of system _SysLess than 200ps, obtain at the theoretical minimum range resolving power of TDR equipment of the present invention be

$L_{\mathrm{Min}}=\frac{1}{2}\frac{C\&times;T_{\mathrm{sys}}}{\sqrt{\mathrm{\&epsiv;}}}=\frac{1}{2}\frac{200\mathrm{ps}\&times;3\&times;{10}^{8}m/s}{\sqrt{\mathrm{\&epsiv;}}}=\frac{30}{\sqrt{\mathrm{\&epsiv;}}}\mathrm{mm}---\left(5\right)$

The minimum length that the characteristic impedance tester can be surveyed in air (ε=1.0006) is

The characteristic impedance tester in the last minimum length of surveying of common FR4 (ε=4) PCB is

${\mathrm{<figure-callout\; id="4"\; label="L\; FR"\; filenames="H200910213961XE00011.png"\; state="\{\{state\}\}">L</figure-callout>}}_{\mathrm{FR}}=\frac{30}{\sqrt{4}}\mathrm{mm}=15\mathrm{mm}---\left(7\right)$

In embodiments of the present invention, T _ScopeBe about 120ps after measured, for making T _SysLess than 200ps, then require T _IncidentLess than 160ps.

Except the rise time, the distortion in advance of step pulse (pre-dashing) also may obviously influence the resolution of TDR system, generally requires the distortion in advance of step pulse as much as possible little.

The amplitude of incident pulse is the most important parameter of influencing characterisitic impedance measurement precision, and amplitude is high more, and the signal to noise ratio of measurement is just high more, and the amplitude of general TDR incident pulse all is hundreds of millivolts.

To sum up analyze, require the Ultrafast edge step pulse that a kind of amplitude is higher, pulse distortion is less, the rise time is exceedingly fast generator can be provided based on the characteristic impedance tester of TDR technology.

Summary of the invention:

The objective of the invention is at existing characteristic impedance test request, a kind of new Ultrafast edge step pulse generating method that can satisfy TDR incident pulse semaphore request is provided, a kind of Ultrafast edge step pulse generator that adopts this method also is provided, make its rise time less than 160ps, amplitude greater than 500mV, overshoot less than 10%.

For achieving the above object, the present invention adopts following technical scheme:

Ultrafast edge step pulse generating method, it may further comprise the steps:

A, high accuracy clock a reference source are through producing pulse excitation signal after the frequency division;

B, excitation signal energizes high-speed comparator produce the pulse signal at a very fast edge;

C, the amplitude of the pulse signal at very fast edge is amplified and pre-shaping;

D, utilize the step-recovery effect of step recovery diode, to further quickening along doing through the rising edge of pulse signal after the amplitude adjustment.

E, the waveform of output pulse signal is carried out shaping and amplitude control;

F, pulse signal is exported.

Wherein, the source of clock reference described in the steps A is that the clock that provides of outside or the high stability crystal oscillator that carries with clock are as clock.

High-speed comparator described in the step B once quickens the pumping signal edge, with the rising/trailing edge of pumping signal along quickening to be shaped into nanosecond.

Utilize the step-recovery effect of step recovery diode among the step D, to further quickening along doing through the rising edge of pulse signal after the amplitude adjustment, with the rising/trailing edge of pumping signal along quickening to be shaped into picosecond.

Wherein, high-speed comparator described in the step B carries out time delay when producing pulse signal, so that notify sampling head to take a sample to finish equivalent sampling after time of delay.

Wherein, utilize Schottky diode that the waveform of output pulse signal is carried out shaping in the step e.

The invention also discloses the Ultrafast edge step pulse generator, it includes the clock reference source of the generation clock drive signal that connects successively, produce the high-speed comparator of very fast edge pulse signal, very fast edge pulse amplitude is amplified and the pulse amplitude of pre-shaping is adjusted circuit, pulse rising edge accelerating circuit and pulse output interface, described pulse rising edge accelerating circuit utilizes the step-recovery effect of step recovery diode, rising edge through pulse signal after the amplitude adjustment is further quickened along work, and the waveform to output pulse signal carries out shaping and amplitude control simultaneously.

Described clock reference source and high-speed comparator are connected with the analog switch that is used to control generation of control impuls source and stop pulse.

The output of described high-speed comparator is connected with delay chip.

Described pulse amplitude is adjusted circuit and is included amplification grade circuit, and two inputs of amplification grade circuit connect two outputs of high-speed comparator respectively by transmission line, and amplification grade circuit connects constant-current source.This differential amplifier utilizes a current source to setover, and its advantage is that the value of the terminating resistor of emitter current and β and base stage has nothing to do, so the size of the terminating resistor of base stage can not influence the stability of bias point.This constant-current source is made up of integrated operational amplifier U, triode Q3, capacitor C 1, resistance R 13, R14, R15, R16.

Described pulse rising edge accelerating circuit includes triode Q4, step recovery diode SRD, resistance R 19, capacitor C, Transient Suppression Diode D0, diode D1, D2, D3, D4, the negative electrode of SRD connects the emitter of Q4, the anode of SRD connects an end of resistance R 19 and an end of capacitor C respectively, the other end of resistance R 19 connects power end+Vss, the other end ground connection of capacitor C; D1, D2, D3, D4 are connected between the emitter and pulse output interface of Q4, and D0 is in parallel with the pulse output interface.

Beneficial effect of the present invention is: the present invention produces the clock drive signal by high accuracy clock a reference source, the clock drive signal enters after the clock, the excitation high-speed comparator produces the pulse signal at a very fast edge, adjusting circuit by pulse amplitude amplifies the amplitude of the pulse signal at very fast edge and shaping in advance, enter the pulse rising edge accelerating circuit then, utilize the step-recovery effect of step recovery diode, rising edge through pulse signal after the amplitude adjustment is further quickened along work, waveform to output pulse signal carries out shaping and amplitude control simultaneously, to reach of the requirement of characteristic impedance tester to rise time and amplitude and overshoot, export by the pulse output interface at last, be about 150ps the pulse rise time of output, amplitude is greater than 500mV, overshoot is less than 10%, pre-dashing can be ignored, and can find or the discontinuous distance of impedance that perception is less.

Description of drawings:

Fig. 1 is the theory diagram of Ultrafast edge step pulse generator of the present invention;

Fig. 2 is an exciting signal source input circuit theory diagram of the present invention;

Fig. 3 is high-speed comparator of the present invention and peripheral circuit schematic diagram thereof;

Fig. 4 is the amplification grade circuit schematic diagram of clock of the present invention;

Fig. 5 is a continuous current source circuit schematic diagram of the present invention;

Fig. 6 is a step recovery diode pulse rising edge accelerating circuit schematic diagram of the present invention;

Fig. 7 is the pulse output waveform of clock of the present invention.

Embodiment:

The present invention is further illustrated below in conjunction with accompanying drawing, Ultrafast edge step pulse generating method, and it may further comprise the steps:

A, produce the clock drive signal by high accuracy clock a reference source 1; The pumping signal of clock is from clock reference source 1, and this clock reference source 1 can be the clock that the outside provides, and also can be that the high stability crystal oscillator that carries on the clock is exported as clock.In the selection of high stability crystal oscillator clock reference, present embodiment is a clock of directly introducing 100KHz from the outside, can certainly be the clock of adorning a 20M onboard obtains 100KHz through frequency division clock.

B, clock drive signal enter after the clock, and excitation signal energizes high-speed comparator 3 produces the pulse signal at a very fast edge; Between high-speed comparator 3 and clock output, designed an analog switch 2 here, so just can come the control impuls source by the button on the panel, when produce pulse.High-speed comparator 3 is the equal of that pulse signals is carried out the first time and quickened, and along quickening to be shaped into nanosecond, the output rise time, amplitude was the square-wave signal of 800mV about 1ns with the rising/trailing edge of pumping signal.High-speed comparator 3 carries out time delay when producing pulse signal, so that notify sampling head to take a sample to finish equivalent sampling after time of delay.

C, the amplitude of the pulse signal at very fast edge is amplified and pre-shaping; The square-wave signal of high-speed comparator 3 outputs will enter pulse amplitude and adjust circuit 4, and the amplitude of paired pulses is amplified and pre-shaping, and its amplitude is enlarged into 3.5V.

D, the pulse signal that has passed through after the amplitude adjustment will enter the porch accelerating circuit, utilize the step-recovery effect of step recovery diode, rising edge through pulse signal after the amplitude adjustment is further quickened along work, utilize Schottky diode that the waveform of output pulse signal is carried out shaping and amplitude control simultaneously, to reach of the requirement of characteristic impedance tester, export as pulse output interface 6 by the radio frequency connector sub-miniature A connector at last rise time and amplitude and overshoot.The pulse rise time of output be 150ps, amplitude greater than 500mV, overshoot less than 10%, in advance towards little, resolution is high, can find or the discontinuous distance of impedance that perception is less.

See shown in Figure 1ly, adopt the Ultrafast edge step pulse generator of said method, it includes the clock reference source 1, high-speed comparator 3, the pulse amplitude that connect successively and adjusts circuit 4, pulse rising edge accelerating circuit 5 and pulse output interface 6.

See shown in Figure 2, if the pumping signal of clock from external clock, can utilize the equipment of sub-miniature A connector by the output of coaxial cable and clock on the pulse source plate to link to each other so.Simultaneously, this clock has considered also that in design the mode that can utilize clock obtains the pumping signal of clock.The crystal oscillator that present embodiment is selected for use is temperature compensating crystal oscillator TCXO, and temperature compensating crystal oscillator connects the input of isolation protective circuit, and the output of isolation protective circuit connects analog switch 2, and analog switch 2 is connected to high-speed comparator 3.Because temperature compensating crystal oscillator is to adjust the output frequency of crystal oscillator by its temperature sensor, so the stability and the accuracy of the output of its frequency are higher, performance exceeds 20 times than the performance of common crystal oscillator.

Signal must pass through an analog switch 2 before preparing to enter high-speed comparator 3.The effect of this analog switch 2 is when the control impuls source produces pulse.When needs are measured, just can make analog switch 2 conductings by button above the panel or pedal switch, allow clock export pulse, when not needing to measure, then analog switch 2 can be disconnected, allow clock stop to export pulse.

Fig. 3 is high-speed comparator 3 and peripheral circuit schematic diagram thereof, and the effect of high-speed comparator 3 mainly is that the signal edge is once quickened, with the rising/trailing edge of pumping signal along quickening to be shaped into nanosecond.Because what follow-up circuit all was to use is the PECL level, and the termination voltage of PECL is+1.3V, so add terminating resistor R1 and R2 respectively on output line.According to TDR complete machine scheme, need clock when sending pulse, to remove to notify delay chip 7, inform that delay chip 7 pulses send, delay chip 7 is done the regular hour delay according to the field programmable gate array preset delay time again, so that notify sampling head to take a sample to finish equivalent sampling after time of delay.So will be divided into two-way from the pulse signal of high-speed comparator 3 output: the one tunnel will directly enter back one-level circuit as the back one-level circuits for triggering of accelerating module again, and time-delay is then gone to trigger as the triggering signal of delay chip 7 in another road.Because signal elevating time is very fast, shake very for a short time, the high speed triggering signal of low jitter can be provided for sampling gate.Because the output resistance of high-speed comparator 3 is 50 Ω, so in order to guarantee signal transmission quality, reduce the ring that signal reflex brings, avoid false triggering, on transmission line, to add some terminating resistor R3, R4, R5 and R6 and do impedance matching, make signal on through path, keep impedance constant.

Fig. 4 is the amplification grade circuit schematic diagram of clock.Because the pulse signal that comes out from high-speed comparator 3 is the PECL level, high level is 2.2V～2.49V, low level is 1.35V～1.76V, its pressure reduction is about 800mV, such pressure reduction can't allow step recovery diode SRD obtain reverse current, so that can't in follow-up circuit, make the back the porch accelerating module---step recovery diode produces quick step, therefore need amplify this signal.Because the signal of the output of high-speed comparator 3 is PECL level, is differential signal, the while is the voltage drift in order to suppress to bring owing to variations in temperature also, so amplifying stage has been designed to the form of differential amplifier.Because the input signal of amplifying stage is a high-speed differential signal, so will utilize R7, R8 and RD to form π type termination at the signal input port place, allows signal wave be absorbed by terminating resistor, and can not cause ring by reflected back source end.

Pulse amplitude is adjusted circuit 4 and is included amplification grade circuit, amplification grade circuit is made up of triode Q1, Q2 and the resistance R 9, R10, R11, the R12 that are connected between Q1, the Q2, two inputs of amplification grade circuit connect two outputs of high-speed comparator 3 respectively by transmission line, amplification grade circuit connects current source, be connected with resistance R D between two signal input parts of amplification grade circuit, be connected with resistance R 7, R8 respectively between two signal input parts and the earth terminal, R7, R8 and RD have formed π type termination.Fig. 5 is a continuous current source circuit schematic diagram, and this differential amplifier utilizes a current source to setover.The advantage of utilizing constant-current source to setover is that the value of the terminating resistor of emitter current and β and base stage has nothing to do, so the size of the terminating resistor of base stage can not influence the stability of bias point.This constant-current source is made up of integrated operational amplifier U, triode Q3, capacitor C 1, resistance R 13, R14, R15, R16, because it is little that integrated transporting discharging has temperature drift, advantages such as open-loop gain is big, so, the constant-current source that utilizes integrated transporting discharging to form can reduce noise greatly and significantly improve temperature performance, integrated transporting discharging common-mode rejection ratio height has very significant inhibitory effect to the current ripples that causes because of input voltage fluctuation simultaneously.Wherein can regulate the size that R16 changes current source current, utilize C1 to be used for carrying out phase compensation.

Fig. 6 is a step recovery diode porch accelerating circuit schematic diagram, and pulse is through after the amplification of amplification grade circuit, and becoming the voltage amplitude difference is 3.5V, and the edge rise time is the pulse signal of nanosecond.Next, just this pulse signal shaping need be become amplitude greater than 500mV, the edge rise time is the quick step pulse signal of 150ps.See shown in Figure 6, pulse rising edge accelerating circuit 5 includes triode Q4, step recovery diode SRD, resistance R 0, R17, R18, R19, capacitor C, Transient Suppression Diode D0, diode D1, D2, D3, D4, the negative electrode of SRD connects the emitter of Q4, the anode of SRD connects an end of resistance R 19 and an end of capacitor C respectively, the other end of resistance R 19 connects power end+Vss, the other end ground connection of capacitor C; D1, D2, D3, D4 are connected between the emitter and pulse output interface 6 of Q4, and D0 is in parallel with pulse output interface 6.When pulse signal is low level, step recovery diode SRD forward conduction, resistance R 18, R19 and+Vss formed the direct current biasing to SRD.The size of at this time regulating R2 and R3 can guarantee do not have electric current to flow through on diode D1～D4 when low level, just guaranteed that so also sub-miniature A connector is output as 0 level.When pulse signal was converted to high level, because SRD begins the memory time that reverse-conducting enters SRD, the A point voltage still can significantly not raise, and does not still have electric current to flow through on diode D1, D2, D3, the D4.In order to shorten the memory time of SRD, need to increase reverse current, if but the impedance of SRD front end is reduced, promptly reduce R18 and can cause again the forward bias of SRD is changed, can increase design difficulty like this.So just the Node B at the SRD front end has added a shunt capacitance C on circuit design, reverse current just can flow on the earth terminal by this electric capacity, and the impedance on the direction path that had both reduced like this can guarantee that again the forward bias of SRD is not changed.After finishing memory time, SRD ends immediately, and this moment, the A point voltage also just raise rapidly, had produced a quick step pulse.At this moment, diode D1, D2, D3, D4 also begin conducting, and sub-miniature A connector is just exported the step pulse signal at a fast edge.Regulate the size of R17 and R18 and R19, except the forward bias that can regulate SRD, the size of all right regulating impulse output amplitude, and the overshoot of waveform and rise time.

The junction capacitance of general-purpose diode is too big, generally at dozens or even hundreds of pF, can't well decay to this step signal, so will utilize the very little Schottky diode of junction capacitance to come the pulse base shaping is carried out in the output pulse.Because the reverse breakdown voltage of Schottky diode is 30V; the puncture voltage of SRD is 40V; in order to prevent that the static spike from entering from sub-miniature A connector element is caused damage; so go out and met a Transient Suppression Diode D0 at sub-miniature A connector; can come interim in the static spike; this part energy is shorted to ground, with the circuit element of protection clock.

Fig. 7 is the pulse output waveform of clock of the present invention, generator circuit of the present invention, passed through after the dependence test, the wave-shape amplitude of the pulse output of its clock is 673.82mV, rise time is 153.70ps, 7.67% overshoot is only arranged, almost do not dash in advance, can reach the requirement of characteristic impedance test fully driving pulse.

The above only is preferred embodiment of the present invention, so all equivalences of doing according to the described structure of patent claim of the present invention, feature and principle change or modify, is included in the patent claim of the present invention.

Claims (10)

1. Ultrafast edge step pulse generating method is characterized in that, it may further comprise the steps:

A, produce the clock drive signal by high accuracy clock a reference source;

B, excitation signal energizes high-speed comparator produce the pulse signal at a very fast edge;

C, the amplitude of the pulse signal at very fast edge is amplified and pre-shaping;

D, utilize the step-recovery effect of step recovery diode, to further quickening along doing through the rising edge of pulse signal after the amplitude adjustment;

E, the waveform of output pulse signal is carried out shaping and amplitude control;

F, pulse signal is exported.

2. Ultrafast edge step pulse generating method according to claim 1 is characterized in that: high-speed comparator described in the step B once quickens the pumping signal edge, with the rising/trailing edge of pumping signal along quickening to be shaped into nanosecond.

3. Ultrafast edge step pulse generating method according to claim 1, it is characterized in that: the step-recovery effect of utilizing step recovery diode among the step D, to further quickening along doing through the rising edge of pulse signal after the amplitude adjustment, with the rising/trailing edge of pumping signal along quickening to be shaped into picosecond.

4. Ultrafast edge step pulse generating method according to claim 1, it is characterized in that: high-speed comparator described in the step B carries out time delay when producing pulse signal, so that notify sampling head to take a sample to finish equivalent sampling after time of delay.

5. according to any described Ultrafast edge step pulse generating method of claim 1-4, it is characterized in that: utilize Schottky diode that the waveform of output pulse signal is carried out shaping and amplitude control in the step e.

6. Ultrafast edge step pulse generator, it is characterized in that: it includes the clock reference source of the generation clock drive signal that connects successively, produce the high-speed comparator of very fast edge pulse signal, very fast edge pulse amplitude is amplified and the pulse amplitude of pre-shaping is adjusted circuit, pulse rising edge accelerating circuit and pulse output interface, described pulse rising edge accelerating circuit utilizes the step-recovery effect of step recovery diode, rising edge through pulse signal after the amplitude adjustment is further quickened along work, and the waveform to output pulse signal carries out shaping and amplitude control simultaneously.

7. Ultrafast edge step pulse generator according to claim 6 is characterized in that: described clock reference source and high-speed comparator are connected with the analog switch that is used to control generation of control impuls source and stop pulse.

8. Ultrafast edge step pulse generator according to claim 6 is characterized in that: the output of described high-speed comparator is connected with delay chip, and low jitter high speed triggering signal is provided.

9. Ultrafast edge step pulse generator according to claim 6, it is characterized in that: described pulse amplitude is adjusted circuit and is included the amplification grade circuit that suppresses temperature drift, two inputs of amplification grade circuit adopt the π type termination of suppressed ringing, connect two outputs of high-speed comparator then respectively by transmission line, amplification grade circuit connects current source.

10. according to any described Ultrafast edge step pulse generator of claim 6-9, it is characterized in that: described pulse rising edge accelerating circuit includes triode Q4, step recovery diode SRD, resistance R 19, capacitor C, Transient Suppression Diode D0, diode D1, D2, D3, D4, the negative electrode of SRD connects the emitter of Q4, the anode of SRD connects an end of resistance R 19 and an end of capacitor C respectively, the other end of resistance R 19 connects power end+Vss, the other end ground connection of capacitor C; D1, D2, D3, D4 are connected between the emitter and pulse output interface of Q4, and D0 is in parallel with the pulse output interface.

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