CN108471303A - Programmable nanosecond timing precision pulse generator based on FPGA - Google Patents
Programmable nanosecond timing precision pulse generator based on FPGA Download PDFInfo
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- CN108471303A CN108471303A CN201810269029.8A CN201810269029A CN108471303A CN 108471303 A CN108471303 A CN 108471303A CN 201810269029 A CN201810269029 A CN 201810269029A CN 108471303 A CN108471303 A CN 108471303A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/64—Generators producing trains of pulses, i.e. finite sequences of pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00234—Layout of the delay element using circuits having two logic levels
- H03K2005/00247—Layout of the delay element using circuits having two logic levels using counters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00234—Layout of the delay element using circuits having two logic levels
- H03K2005/00254—Layout of the delay element using circuits having two logic levels using microprocessors
Abstract
A programmable nanosecond timing precision pulse generator based on an FPGA comprises the FPGA, an upper computer, a crystal oscillator circuit, a pulse amplitude control circuit and a pulse edge conditioning circuit, wherein the upper computer, the crystal oscillator circuit, the pulse amplitude control circuit and the pulse edge conditioning circuit are connected to the periphery of the FPGA, and the FPGA comprises a serial port control module, an instruction analysis module, a timing and pulse string generation module, a clock control module, an SPI control module and an OSERDES control module. The invention uses a piece of FPGA and a small amount of peripheral circuits to realize multi-channel pulse signals with nanosecond timing precision, and realizes a universal asynchronous receiving and transmitting serial port protocol in the FPGA, so that the pulse generator has a programmable control function, the pulse period, the pulse width and the pulse delay can be controlled by serial port programming, and the pulse amplitude is programmable by matching with a pulse amplitude control circuit. The circuit of the invention has small size and simple structure, can work independently and can be integrated into other systems as a modular circuit.
Description
Technical field
The invention belongs to electronic technology fields, are related to a kind of impulse generator, refer specifically to a kind of programmable multichannel and receive
Second grade high-precision pulse generator, can output multi-channel impulse amplitude, pulse period, pulse width and pulse delay it is programmable
Pulse signal, the Adjustment precision in period, pulsewidth and delay reaches 1ns.It can be adopted as pulse signal source applied to signal
The fields such as collection and signal measurement.
Background technology
High-precision pulse generation technique has very in application fields such as signal measurement, signal generation, pumping signal generations
It is widely applied demand.Such as light pulse signal fields of measurement is measured in some high speed signals, needs to utilize high-precision pulse signal
As sampling trigger signal, the sampling instant and sampling length of ADC chips are accurately controlled.Especially in multi-channel sampling
Field, it is desirable that the delay controllable precise of multiplex pulse signal.With the raising of signal frequency, pulse generation technology is to signal arteries and veins
Wide, period and pulse up and down require increasingly to improve along equally accurate.
Although many apparatus manufactures provide the special instruments such as high-precision pulse generator, fancy price and larger
Volumetric constraint its application scenarios.Ensuring that pulse parameter is high-precision simultaneously, the volume of smaller circuit and lower life
Producing cost has significant practical significance.High precision timing control is the key that pulse-generating circuit, and existing scheme mostly uses greatly
MCU or FPGA realizes the method for counter to control the burst length, and burst length precision is limited to counter clock frequency, difficult
To realize the timing accuracy of nanosecond.
Invention content
Of the existing technology in order to solve the problems, such as, present invention aims at provide a kind of programmable nanosecond based on FPGA
Grade timing accuracy impulse generator.The present invention is based on output serializer/de-serializers (OSERDES) technologies of FPGA, propose a kind of
Multichannel pulse signal generator realizes the high-precision pulse sequential control method of 1ns, and realizes inside FPGA universal asynchronous
Transmitting-receiving transmission (Universal Asynchronous Receiver/Transmitter, UART) serial port protocol, makes pulse generation
Device has programmable control function, and pulse period, pulse width and pulse delay can be controlled by serial port programming, pulse of arranging in pairs or groups
Amplitude control circuit keeps impulse amplitude programmable.The present invention is as a kind of flexible, cheap, convenient pulse generation of Human-machine Control
Device scheme can expand the application range of impulse generator, meet the application demand of a variety of occasions.
Purpose to realize the present invention, the present invention is achieved by the following scheme：
A kind of programmable nanosecond timing accuracy impulse generator based on FPGA, including FPGA and be connected to outside FPGA
Host computer, crystal oscillating circuit, impulse amplitude control circuit and the porch modulate circuit enclosed, FPGA include serial ports control module,
Periodically with train of pulse module, clock control module, SPI control modules and OSERDES control modules occur for command analysis module.
The host computer is connect with the serial ports control module in FPGA, and serial ports control module is for receiving from host computer
Pulse Width Control instructs, and Pulse Width Control instruction includes the pulse delay of impulse amplitude, pulse period, pulse width and interchannel.
Command analysis module is connect with serial ports control module, and the Pulse Width Control of host computer is instructed output by serial ports control module
To command analysis module, command analysis module is used to parse the Pulse Width Control instruction of host computer, and the Pulse Width Control of host computer is referred to
Order is converted to internal control word, including impulse amplitude control word and Pulse Width Control word.
Timing is connect with pulse series generator with command analysis module, and instruction parsing mould is periodically received with pulse series generator
The Pulse Width Control word of block output, for the train of pulse for generating corresponding 8bit per pulse all the way.Timing and pulse series generator
Output connection OSERDES control modules, OSERDES control modules receive the pulse of timing and the 8bit of pulse series generator output
8bit trains of pulse are converted to serial bit stream and exported and give porch modulate circuit by string under the driving of high-frequency clock.Arteries and veins
The serial bit stream that trimming exports FPGA along modulate circuit carries out edge conditioning, adjustment pulse rise time, fall time and
Impulse level simultaneously exports away pulse.
SPI control modules are connect with command analysis module, and SPI control modules receive the pulse width of command analysis module output
Control word is spent, SPI control modules connect impulse amplitude control circuit, and SPI control modules control impulse amplitude control by SPI protocol
The digital potentiometer of circuit processed, and then control the output amplitude of pulse.SPI control module of the impulse amplitude control circuit in FPGA
Under control, corresponding impulse amplitude control voltage is generated, porch modulate circuit is acted on.
Crystal oscillating circuit is connect with the clock control module in FPGA, and crystal oscillating circuit generates 125MHz clocks, as FPGA's
Working standard clock, the clock control module in FPGA are responsible for generating two-way clock i.e. low-speed clock and height with frequency multiplication relationship
Fast clock, 1MHz low-speed clocks act on serial ports control module and command analysis module, and the high-frequency clock of 1GHz acts on
OSERDES control modules；125MHz clocks act on timing and module occur with train of pulse.
As the preferred technical solution of the present invention, the FPGA uses the FPGA with OSERDES functions, OSERDES's
Highest serial clock rate is not less than 1Gbps, such as 6 Series FPGAs of Spartan of Xilinx companies.
Compared with prior art, this method has the following advantages：
(1) present invention realizes that the multichannel pulse of nanosecond timing accuracy is believed using a piece of FPGA and a small amount of peripheral circuit
Number, circuit size is small, simple in structure.It can work independently, and can be integrated into other systems as modularized circuit.
(2) for the FPGA that the present invention uses for the serial low performance FPGA of Spartan 6, a small amount of peripheral circuit chip of arranging in pairs or groups is whole
Body is cheap, and system cost is greatly reduced while realizing that function occurs for high-precision pulse.
(3) impulse amplitude, pulse period, pulse width and pulse delay of the invention can be compiled by UART serial ports
Journey, pulse output adjustable extent is big, and Universal joint, agreement is simple, is convenient for PC control.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention without having to pay creative labor, may be used also for those of ordinary skill in the art
With obtain other attached drawings according to these attached drawings.
Fig. 1 is the structural diagram of the present invention.
Fig. 2 is that the implementing procedure figure of module occurs with train of pulse for the timing of the present invention.
Fig. 3 is the structure chart of impulse amplitude control circuit.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described example is only a part of the embodiment of the present invention, instead of all the embodiments.Based on this
Embodiment in invention, the every other reality that those of ordinary skill in the art are obtained without creative efforts
Example is applied, shall fall within the protection scope of the present invention.
The present invention proposes a kind of programmable nanosecond timing accuracy impulse generator based on FPGA, the wherein timing of pulse
Precision reaches 1ns.Its structure diagram is as shown in Figure 1.
Including FPGA and it is connected to host computer, crystal oscillating circuit, impulse amplitude control circuit and the edge of pulse of the peripheries FPGA
Along modulate circuit, FPGA include serial ports control module, command analysis module, periodically with train of pulse occur module, clock control mould
Block, SPI control modules and OSERDES (deserializer) control module.
In the present embodiment, 6 series of Spartan that FPGA is used is a series of positioning low sides, low that Xilinx companies release
The FPGA of power consumption application scenarios, selected model XC6SLX9, only 1430 Slices and 11440 Flip-Flops resources.
If its internal Slices and register resources is directly used to realize timer logic, maximum operation frequency is difficult to be more than
200MHz can not be directly realized by the timing accuracy of 1ns.The present invention utilizes the string of the OSERDES control modules inside Spartan 6
Row transmission-receiving function turns the method for serial bit stream using parallel pulse string, exports high-precision pulse level.Specific implementation is such as
Shown in Fig. 1.
The host computer is connect with the serial ports control module in FPGA, and serial ports control module is for receiving from host computer
Pulse Width Control instructs, and Pulse Width Control instruction includes the pulse delay of impulse amplitude, pulse period, pulse width and interchannel.
Command analysis module is connect with serial ports control module, and the Pulse Width Control of host computer is instructed output by serial ports control module
To command analysis module, command analysis module is used to parse the Pulse Width Control instruction of host computer, and the Pulse Width Control of host computer is referred to
Order is converted to internal control word, including impulse amplitude control word and Pulse Width Control word.
Timing is connect with pulse series generator with command analysis module, and instruction parsing mould is periodically received with pulse series generator
The Pulse Width Control word of block output, for the train of pulse for generating corresponding 8bit per pulse all the way.Timing and pulse series generator
Output connection OSERDES control modules.OSERDES control modules realize that parallel pulse string turns pulse bit stream.OSERDES is controlled
Module receives the train of pulse of timing and the 8bit of pulse series generator output, turns 8bit trains of pulse under the driving of high-frequency clock
It is changed to serial bit stream and exports and give porch modulate circuit.The serial bit stream that porch modulate circuit exports FPGA
Edge conditioning is carried out, adjustment pulse rise time, fall time and impulse level simultaneously export away pulse.
SPI control modules are connect with command analysis module, and SPI control modules receive the pulse width of command analysis module output
Control word is spent, SPI control modules connect impulse amplitude control circuit, and SPI control modules control impulse amplitude control by SPI protocol
The digital potentiometer of circuit processed, and then control the output amplitude of pulse.SPI control module of the impulse amplitude control circuit in FPGA
Under control, corresponding impulse amplitude control voltage is generated, porch modulate circuit is acted on.
Crystal oscillating circuit is connect with the clock control module in FPGA, and crystal oscillating circuit generates 125MHz clocks, as FPGA's
Working standard clock, the clock control module in FPGA are responsible for generating two-way clock i.e. low-speed clock and height with frequency multiplication relationship
Fast clock, 1MHz low-speed clocks act on serial ports control module and command analysis module, and the high-frequency clock of 1GHz acts on
OSERDES control modules；125MHz clocks act on timing and module occur with train of pulse.
About OSERDES control modules
6 Series FPGAs of Spartan are integrated with OSERDES control modules, and OSERDES control modules realize parallel pulse string
Turn pulse bit stream.In wherein each I/O block (IOB, input/output block) serioparallel exchange is exported comprising a 4-bit
Device OSERDES.It is master-slave mode by the SerDes resource distributions of two neighboring I/O block, cascade constitutes a 8-bit SerDes,
Realize 8 high speed serial parallel exchanges.Using 6 Series FPGA internal proprietaries of Spartan in the buffering locking phase of OSERDES input and output
Ring (BUFPLL) BUFPLL can provide the serioparallel exchange work clock of 1GHz for OSERDES control modules its I/O blocks.
The present embodiment constitutes 8 using the OSERDES control modules cascade of 6 two adjacent I/O blocks of Spartan:1 parallel-serial conversion
8 parallel-by-bit pulse series datas of the 125MHz clock rates of input are changed into the serial bit stream of octuple rate 1Gbps and defeated by device
Go out and gives porch modulate circuit.For example, if the input of OSERDES control modules is the parallel arteries and veins under 125MHz clock frequencies
Data 00110000 are rushed, then the bit stream exported after OSERDES is converted forms a pulsewidth 2ns, period 8ns, duty ratio
25% pulse.
About command analysis module
Serial ports control module receives the Pulse Width Control instruction from host computer, and Pulse Width Control instructs the width for including four tunnel pulses
Spend A1-A4, pulse period T1-T4, pulse width W1-W4, four road relative time delay D1-D4。
Command analysis module is used to parse the Pulse Width Control instruction of host computer, and the Pulse Width Control instruction of host computer is converted to
Internal control word, including impulse amplitude control word and Pulse Width Control word.
Specifically, command analysis module is by the impulse amplitude control word A of four tunnel pulses1-A4It is scaled impulse amplitude control electricity
The resistance value control word RW of digital potentiometer in road1-RW4, and resistance value control word is sent to SPI control modules.About numerical control current potential
The circular of the resistance value control word of device gives in next trifle is about impulse amplitude control circuit and explains in detail.
Command analysis module is also responsible for pulse period T1-T4, pulse width W1-W4, four road relative time delay D1-D4It is converted to
Pulse Width Control word inside FPGA, including pulse passage delay time value PND, pulses low time value PNL and the high electricity of pulse
Flat time value PNH.PND, PNL and PNH indicate corresponding time span 1GHz clocks clock count values.Such as pulse ginseng
It is delay 10ns, pulse period 1ms to count, pulse duty cycle 30%, i.e. pulse width 300ns, then PND=10, PNL=700,
PNH=300.
About porch modulate circuit and impulse amplitude control circuit
The high-speed pulse serial bit stream exported from the OSERDES control modules of FPGA, is limited to the driving side of FPGAIO
Formula and fan-out capability, the rising edge and failing edge of pulse signal are slower, and impulse waveform is undesirable, need to increase porch
Modulate circuit makes pulse along more precipitous.The present embodiment selects the 74LVC2T45 electrical level transferring chips of NXP semiconductor companies production real
Existing porch conditioning functions, which is the tri-state two-way level converting transceiver of a dibit, dual power supply.It is two-way
It supports 1.2V to 5.5V power supplies, turn between the logical signal of highest 420Mbps data transfer rate varying level standards may be implemented
It changes.The edge conditioning functions similar to Schmitt trigger circuit may be implemented in its high speed gate circuit being internally integrated.It will be from
The Bitstream signal of the OSERDES control modules output of FPGA is connected to the ports A of 74LVC2T45 electrical level transferring chips,
The output pulse signal rising edge and failing edge of the ports B of 74LVC2T45 electrical level transferring chips can reach 1.5ns, to
Meet the design requirement of High speed pulse generator.
The output end of the OSERDES control modules of the ports the A connection FPGA of 74LVC2T45 electrical level transferring chips,
The driving voltage of 74LVC2T45 electrical level transferring chips is consistent with FPGA IO voltages.By adjusting 74LVC2T45 level conversion cores
The supply voltage of its port B of piece changes the level standard of output signal.Consider 74LVC2T45 chip B port output levels and B
It holds supply voltage to there is about 0.5V pressure drops, needs onboard power-supply system realization 2.3V-5.5V adjustable voltages conversion.
Impulse amplitude control circuit generates corresponding impulse amplitude control voltage under the SPI control modules control of FPGA,
Act on porch modulate circuit.Impulse amplitude control circuit is as shown in figure 3, including LT8335 switching power source chips and its outside
Enclose circuit, digital potentiometer AD5160.The peripheral circuit of LT8335 switching power source chips is provided according to its chip data handbook
Single-ended primary winding inductance converts (single-ended primary inductance converter, SEPIC) electric source modes
Connection.SEPIC electric source modes allow output voltage to be more than, are less than or equal to input voltage, it can be ensured that system input voltage
When changing in the input range of 3V-12V, LT8335 switching power source chips export the voltage of setting always.LT8335 switch electricity
The ends numerical control tap W of source chip its FBX pin termination digital potentiometer AD5160, A, B two-port of digital potentiometer AD5160
Resistance to numerical control tap W is respectively RAWAnd RBW, the ports the A connecting resistance R1 of digital potentiometer AD5160 is followed by impulse amplitude control
The output end V of circuit processedOUT, it is grounded after the ports the A connecting resistance R2 of digital potentiometer AD5160.The SPI control modules of FPGA connect
The SPI interface of digital potentiometer AD5160, FPGA control digital potentiometer AD5160 by SPI control modules, electricity may be implemented
Resistance adjustment function.
The present embodiment use Linear companies production LT8335 switching power source chips, and be configured as single-ended primary around
Group inductive transduction (single-ended primary inductance converter, SEPIC) electric source modes.In the pattern
Under, the calculation formula of output voltage is：
Adjust the resistance R of its FBX pin end of LT8335 switching power source chips1And R2Proportionate relationship can change LT8335
Switching power source chip output voltage, in addition chip handbook require R1、R2Resistance value between 25K Ω -1M Ω.The present embodiment is in Fig. 3
Shown in R1、R2Increase digital potentiometer chip in partial circuit.The present embodiment selects 256 digital potentiometers of SPI interface
AD5160, end-to-end resistance maximum 100K Ω, FPGA control digital potentiometer AD5160 by SPI control modules, may be implemented
Resistance adjusts function.As shown in Figure 3, it is assumed that the resistance of digital potentiometer AD5160 its A, B two-port to numerical control tap W is respectively
RAWAnd RBW, then formula be deformed into：
Wherein, RAW+RBW=100K Ω, take Ra=30K Ω, Rb=52K Ω, substituting into formula can obtain, VOUTAdjusting model
It encloses for 1.9V-5.6V, meets the adjustable range of 2.3V-5.5V needed for system, and make its FBX of LT8335 switching power source chips
The R of pin1、R2Resistance value is between the 25K Ω -1M Ω that chip allows always.
Command analysis module in FPGA is after being resolved to impulse amplitude control word, according to output voltage VOUTCalculating it is public
Formula calculates the corresponding resistance values of Vout, and controls calculation according to the resistance value of digital potentiometer AD5160 and be digitally controlled potentiometer
Resistance value control word is sent to SPI control modules by corresponding resistance value control word.SPI control modules are converted to resistance value control word
Serial SPI data, the digital potentiometer in write pulse amplitude control circuit, and then electric power output voltage is caused to change,
Output voltage acts on the impulse level conversion chip 74LVC2T45 of porch modulate circuit.Impulse level conversion chip
74LVC2T45 according to the supply voltage of its port B of 74LVC2T45 electrical level transferring chips, by 74LVC2T45 electrical level transferring chips its
The pulse signal level of the ports A input is converted to the corresponding level standard output in its port B of 74LVC2T45 electrical level transferring chips,
Realize step-by-step adjustment of the pulse output level from 1.5V to 5V.
Module occurs about timing and train of pulse
Timing occurs module with train of pulse and mainly completes according to three pulse period, pulsewidth and pulse delay input parameters,
Generate the parallel 8bit trains of pulse of coincidence pulse timing demands.As shown in Fig. 2, being as follows：
Step 1, initialization FPGA built-in variable delay times count CNDelay, pulses low counts CNLow and arteries and veins
Level of leaping high counts CNHigh, and initialization is set as 0, and module periodically occurs with train of pulse and receives what command analysis module passed over
Input variable, that is, pulse passage delay time value PND, pulses low time value PNL and pulse high level time value PNH.
Step 2, trigger time counting CNDelay is cumulative, because counter works frequency is 125MHz, and exports
Pulse bit stream frequency is 1Gbps, therefore each clock cycle CNDelay adds 8.
Step 3 stops time delay count at the time of delay time is counted equal to or more than communication channel delay time value, enables
Output, starts to export complete zero 8 ' b00000000 of low level pulse string.In view of timing accuracy requires 1ns, low level time meter
The value CNDelay that several initial values is equal to current delay time counter subtracts pulse passage delay time value PND.
Step 4 starts low level counting CNLow and adds up, and each clock cycle CNLow adds 8.
Step 5 stops low level and counts, start defeated at the time of low level is counted equal to or more than low level time value
Go out high level pulse string, it is contemplated that timing accuracy requires 1ns, the initial value that high level time counts to be equal to current low level time
The value CNLow of counter subtracts pulses low time value PNL, the train of pulse of current time output should be equal to eight full 0s with
CNHigh 1bit are asked or operation obtains later.For example, work as PNL=100, CNLow=104, then current time high level time
Count initial value CNHigh=4,8 ' b00001111 of output parallel pulse displacement.
Step 6 starts high level counting CNHigh and adds up, and each clock cycle CNHigh adds 8.
Step 7 stops high level meter at the time of high level counts CNHigh equal to or more than high level time value PNH
Number starts to export low level pulse string, it is contemplated that timing accuracy requires 1ns, the initial value that low level time counts to be equal to current
The value CNHigh of high level time counter subtracts low level time value PNH, and the train of pulse of current time output should be equal to eight
It asks with the positions CNLow 0 and is obtained after operation in position complete 1.For example, work as PNH=200, CNHigh=206, then current time low level
Time counting initial value CNLow=6,8 ' b11000000 of output parallel pulse displacement.Step 4 is returned to, low level is restarted
It counts cumulative.
Single channel or multichannel pulse generation may be implemented in the pulse generation method of the present invention, and each channel corresponds to one group
Command analysis module, periodically with train of pulse module and porch modulate circuit all the way occur for OSERDES control modules, wherein
Command analysis module, module exampleization realization inside FPGA periodically occurs with train of pulse for OSERDES control modules, in FPGA
In the case that resource meets, realize that more pulse passage quantity need not increase FPGA quantity, often increasing the output of pulse all the way needs
Increase set of pulses edge modulate circuit.If multiplex pulse voltage synchronous is adjusted, system only needs a piece of LT8335 electricity
Source chip and a piece of AD5160 digital potentiometers often increase two-way pulse output and only need to increase a piece of 74LVC2T45.
The above is only a preferred embodiment of the present invention, protection scope of the present invention is not limited to above-mentioned implementation
Example, all technical solutions belonged under thinking of the present invention all belong to the scope of protection of the present invention.It should be pointed out that for the art
Those of ordinary skill for, several improvements and modifications without departing from the principles of the present invention, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of programmable nanosecond timing accuracy impulse generator based on FPGA, which is characterized in that including FPGA and company
It is connected on host computer, crystal oscillating circuit, impulse amplitude control circuit and the porch modulate circuit of the peripheries FPGA, FPGA includes serial ports
Command analysis module, periodically with train of pulse module, clock control module, SPI control modules and OSERDES occur for control module
Control module；
The host computer is connect with the serial ports control module in FPGA, and serial ports control module is for receiving the pulse from host computer
Control instruction, Pulse Width Control instruction include the pulse delay of impulse amplitude, pulse period, pulse width and interchannel；
Command analysis module is connect with serial ports control module, and serial ports control module is by the Pulse Width Control instruction output of host computer to finger
It enables parsing module, command analysis module be used to parse the Pulse Width Control instruction of host computer, the Pulse Width Control instruction of host computer is turned
It is changed to internal control word, including impulse amplitude control word and Pulse Width Control word；
Timing is connect with pulse series generator with command analysis module, and it is defeated periodically to receive command analysis module with pulse series generator
The Pulse Width Control word gone out, for the train of pulse for generating corresponding 8bit per pulse all the way；The output of timing and pulse series generator
OSERDES control modules are connected, OSERDES control modules receive the train of pulse of timing and the 8bit of pulse series generator output,
8bit trains of pulse are converted to serial bit stream and exported under the driving of high-frequency clock and give porch modulate circuit；The edge of pulse
Edge conditioning, adjustment pulse rise time, fall time and pulse are carried out to the serial bit stream that FPGA is exported along modulate circuit
Level simultaneously exports away pulse；
SPI control modules are connect with command analysis module, and SPI control modules receive the impulse amplitude control of command analysis module output
Word processed, SPI control modules connect impulse amplitude control circuit, and SPI control modules control impulse amplitude control electricity by SPI protocol
The digital potentiometer on road, and then control the output amplitude of pulse；SPI control module of the impulse amplitude control circuit in FPGA controls
Under, corresponding impulse amplitude control voltage is generated, porch modulate circuit is acted on；
Crystal oscillating circuit is connect with the clock control module in FPGA, and crystal oscillating circuit generates 125MHz clocks, the work as FPGA
Reference clock, when the clock control module in FPGA is responsible for generating the two-way clock i.e. low-speed clock and high speed with frequency multiplication relationship
Clock, 1MHz low-speed clocks act on serial ports control module and command analysis module, and the high-frequency clock of 1GHz acts on OSERDES controls
Molding block；125MHz clocks act on timing and module occur with train of pulse.
2. the programmable nanosecond timing accuracy impulse generator according to claim 1 based on FPGA, which is characterized in that
FPGA uses the FPGA with OSERDES functions, the highest serial clock rate of OSERDES to be not less than 1Gbps.
3. the programmable nanosecond timing accuracy impulse generator according to claim 2 based on FPGA, which is characterized in that
FPGA uses 6 Series FPGAs of Spartan of Xilinx companies, 6 Series FPGAs of Spartan to be integrated with OSERDES control modules,
OSERDES control modules realize that parallel pulse string turns pulse bit stream.
4. the programmable nanosecond timing accuracy impulse generator according to claim 3 based on FPGA, which is characterized in that
In 6 Series FPGA each of which I/O blocks of Spartan deserializer OSERDES is exported comprising a 4-bit；By two neighboring IO
The SerDes resource distributions of block are master-slave mode, and cascade constitutes a 8-bit SerDes, realizes 8 high speed serial parallel exchanges；Profit
With 6 Series FPGA internal proprietaries of Spartan in the buffering phaselocked loop of OSERDES input and output be its IO of OSERDES control modules
Block provides the serioparallel exchange work clock of 1GHz.
5. the programmable nanosecond timing accuracy impulse generator according to claim 4 based on FPGA, which is characterized in that
Serial ports control module receives the Pulse Width Control instruction from host computer, and Pulse Width Control instructs the amplitude A for including four tunnel pulses1-A4,
Pulse period T1-T4, pulse width W1-W4, four road relative time delay D1-D4；Command analysis module is by the impulse amplitude of four tunnel pulses
Control word A1-A4It is scaled the resistance value control word RW of digital potentiometer in impulse amplitude control circuit1-RW4, and resistance value is controlled
Word is sent to SPI control modules；
Command analysis module is also responsible for pulse period T1-T4, pulse width W1-W4, four road relative time delay D1-D4Be converted to FPGA
Internal Pulse Width Control word, including when pulse passage delay time value PND, pulses low time value PNL and pulse high level
Between value PNH；Pulse passage delay time value PND, pulses low time value PNL and pulse high level time value PNH are indicated
Clock count value of the corresponding time span in 1GHz clocks.
6. the programmable nanosecond timing accuracy impulse generator according to claim 4 based on FPGA, which is characterized in that
Porch modulate circuit selects the 74LVC2T45 electrical level transferring chips of NXP semiconductor companies production to realize porch conditioning
Function；.The Bitstream signal exported from the OSERDES control modules of FPGA is connected to the A of 74LVC2T45 electrical level transferring chips
Port, the output pulse signal rising edge and failing edge of the ports B of 74LVC2T45 electrical level transferring chips can reach 1.5ns.
7. the programmable nanosecond timing accuracy impulse generator according to claim 6 based on FPGA, which is characterized in that
Impulse amplitude control circuit includes LT8335 switching power source chips and its peripheral circuit, digital potentiometer AD5160, and LT8335 is opened
The single-ended primary winding inductance converting power source pattern connection that the peripheral circuit of powered-down source chip is provided according to its chip data handbook,
Single-ended primary winding inductance converting power source pattern allows output voltage to be more than, is less than or equal to input voltage, it can be ensured that is
When system input voltage changes in the input range of 3V-12V, LT8335 switching power source chips export the voltage of setting always；
The ends numerical control tap W of LT8335 switching power source chips its FBX pin termination digital potentiometer AD5160, digital potentiometer
The resistance of A, B two-port of AD5160 to numerical control tap W are respectively RAWAnd RBW, the ports the A connecting resistance of digital potentiometer AD5160
R1 is followed by the output end V of impulse amplitude control circuitOUT, it is grounded after the ports the A connecting resistance R2 of digital potentiometer AD5160；FPGA
SPI control modules connection digital potentiometer AD5160 SPI interface, FPGA passes through SPI control modules and controls digital potentiometer
Resistance adjustment function may be implemented in AD5160.
8. the programmable nanosecond timing accuracy impulse generator according to claim 7 based on FPGA, which is characterized in that
Assuming that the resistance of digital potentiometer AD5160 its A, B two-port to numerical control tap W are respectively RAWAnd RBW, output voltage VOUTMeter
Calculating formula is：
Wherein, RAW+RBW=100K Ω, take Ra=30K Ω, Rb=52K Ω, substituting into formula can obtain, VOUTAdjustable range be
1.9V-5.6V meets the adjustable range of 2.3V-5.5V needed for system, and makes its FBX pin of LT8335 switching power source chips
R1、R2Resistance value is between the 25K Ω -1M Ω that LT8335 switching power source chips allow always.
9. the programmable nanosecond timing accuracy impulse generator according to claim 8 based on FPGA, which is characterized in that
Command analysis module in FPGA is after being resolved to impulse amplitude control word, according to output voltage VOUTCalculation formula calculate
The corresponding resistance values of Vout, and calculation is controlled according to the resistance value of digital potentiometer AD5160 and is digitally controlled the corresponding resistance of potentiometer
It is worth control word, resistance value control word is sent to SPI control modules；Resistance value control word is converted to serial SPI numbers by SPI control modules
According to, the digital potentiometer in write pulse amplitude control circuit, and then electric power output voltage is caused to change, output voltage is made
Impulse level conversion chip 74LVC2T45 for porch modulate circuit；Impulse level conversion chip 74LVC2T45 according to
The supply voltage of its port B of 74LVC2T45 electrical level transferring chips, the arteries and veins that its port A of 74LVC2T45 electrical level transferring chips is inputted
It rushes signal level and is converted to the corresponding level standard output in its port B of 74LVC2T45 electrical level transferring chips, realize pulse output electricity
The flat step-by-step adjustment from 1.5V to 5V.
10. the programmable nanosecond timing accuracy impulse generator according to claim 9 based on FPGA, feature exist
In the workflow of module periodically occurs with train of pulse is：
Step 1, initialization FPGA built-in variable delay times count CNDelay, pulses low counts CNLow and pulse is high
Level counts CNHigh, and initialization is set as 0, is periodically passed over train of pulse generation module reception command analysis module defeated
Enter variable i.e. pulse passage delay time value PND, pulses low time value PNL and pulse high level time value PNH；
Step 2, trigger time counting CNDelay is cumulative, because counter works frequency is 125MHz, and exports pulse
Bitstream frequency is 1Gbps, therefore each clock cycle CNDelay adds 8；
Step 3 stops time delay count at the time of delay time is counted equal to or more than communication channel delay time value, enables defeated
Go out, starts to export complete zero 8 ' b00000000 of low level pulse string；In view of timing accuracy requires 1ns, low level time to count
Initial value be equal to current delay time counter value CNDelay subtract pulse passage delay time value PND；
Step 4 starts low level counting CNLow and adds up, and each clock cycle CNLow adds 8；
Step 5 stops low level and counts, it is high to start output at the time of low level is counted equal to or more than low level time value
Level pulse string, it is contemplated that timing accuracy requires 1ns, the initial value that high level time counts to be counted equal to current low level time
The value CNLow of device subtracts pulses low time value PNL, the train of pulse of current time output should be equal to eight full 0s with
CNHigh 1bit are asked or operation obtains later；
Step 6 starts high level counting CNHigh and adds up, and each clock cycle CNHigh adds 8；
Step 7 stops high level and counts at the time of high level counts CNHigh equal to or more than high level time value PNH,
Start to export low level pulse string, it is contemplated that timing accuracy requires 1ns, the initial value that low level time counts to be equal to current high electricity
The value CNHigh of flat time counter subtracts low level time value PNH, and the train of pulse of current time output should be equal to eight complete 1
It asks with the positions CNLow 0 and is obtained after operation；Step 4 is returned to, it is cumulative to restart low level counting.
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