CN207625572U - One kind being used for Ethernet pattern configurations time-sharing multiplex interface circuit - Google Patents
One kind being used for Ethernet pattern configurations time-sharing multiplex interface circuit Download PDFInfo
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Abstract
The utility model discloses one kind being used for Ethernet pattern configurations time-sharing multiplex interface circuit, including sequential control circuit, output time-sharing multiplex port circuit, input configuration port circuit.Wherein time-sequence control module acts on output time-sharing multiplex port circuit, is used for output port function switch for generating pattern switching control signal SWITCH and count value, pattern switching control signal SWITCH；When SWITCH is low, the count value that output time-sharing multiplex port circuit export sequential control circuit generates into row decoding and can configure the timing waveform of N-bit register and be simultaneously sent to output port, the waveform is for the configuration of Ethernet operating mode；When pattern switching control signal SWITCH is high, externally input signal is sent to output port, function module 1 is that LCD is exported or other Digital Logic export；Input configuration port circuit mouth is used to acquire the timing waveform of input port, and collected numerical value is written in ethernet PHY piece internal schema configuration register, completes the configuration of Ethernet operating mode.
Description
Technical field
The invention belongs to integrated circuit fields, are related to Ethernet pattern configurations time-sharing multiplex interface circuit.
Background technology
Ethernet PHY piece work networking environment is complicated, in order to adapt to different network environments, is needed before communicating to Ethernet
PHY pieces carry out corresponding hardware configuration, such as speed, interface mode, principal and subordinate, duplex etc..Traditional ethernet PHY pieces are specified specific
Pin is used for configuration ethernet operating mode, and the program needs more number of pins and is difficult all patterns of covering, not covered
Pattern then needs to configure corresponding registers according to certain timing requirements by special serial ports, makes troubles to user's use.
Invention content
The technology of the present invention solves the problems, such as：It overcomes the deficiencies of the prior art and provide a kind of for Ethernet pattern configurations
Time-sharing multiplex interface circuit is suitable for Ethernet chip, and the pattern configurations of ethernet PHY piece are completed with less multiplexing pins,
Cost is reduced, it is user-friendly.
Technical solution of the invention is：One kind being used for Ethernet pattern configurations time-sharing multiplex interface circuit, the interface
Circuit includes：Sequential control circuit, output time-sharing multiplex port circuit, input configuration port circuit, wherein：
Sequential control circuit receives externally input reset signal RESET and clock signal clk, right after reset
Externally input clock signal clk is counted, and count value is exported to output time-sharing multiplex port circuit and input and is configured
Port circuit；Output port pattern switching control signal SWITCH is generated to output time-sharing multiplex port electricity according to count value simultaneously
Road；
Time-sharing multiplex port circuit is exported, including 2N- 2 road output ports export N bit timing waveforms per road output port,
2N- 2 tunnels export, in addition digital power, digitally, whole 2 needed for covering configuration N-bit registerNKind situation, when SWITCH is low
When, timing waveform is generated into row decoding, and according to decoding value to the count value of sequential control circuit output, and pass through output port
By timing waveform Serial output；When SWITCH is high, externally input signal is sent to output port, N >=1；
Input configuration port circuit connects defeated including the roads M input port and the roads M configure input circuit per input port all the way
Go out the output wherein all the way of time-sharing multiplex port circuit or be directly connected with digital power, digitally, per configuration input electricity all the way
Road is according to the count value of sequential control circuit Counter using time-multiplexed mode to accessing the defeated of the configuration input circuit
The timing waveform of inbound port is sampled, and sampled result is serially written in ethernet PHY piece internal configuration registers, configuration
Ethernet operating mode.
The sequential control circuit includes counter, the first CL Compare Logic, the first d type flip flop and two inputs or door；
Externally input reset signal RESET and clock signal clk are separately connected the reset terminal and clock end of counter, meter
The data output end of number device is divided into three tunnels, and the data terminal of first via feedback link to counter is loaded into for data；Second tunnel connects
The input terminal for connecing the first CL Compare Logic is compared in the first CL Compare Logic with the first default value；Third road export to point
When multiplexing port circuit and input configuration port circuit；The output of first CL Compare Logic is divided into two-way, all the way connect two input or
One input terminal of door, another way connect the data terminal of the first d type flip flop；Two inputs or another input terminal connection of door reset letter
The output end feedback link counter of number RESET, two inputs or door is loaded into control terminal, for carrying the numerical value at counter data end
Enter in counter, the first d type flip flop clock end connects clock signal clk, the first d type flip flop output mode switch-over control signal
SWITCH is to time-sharing multiplex port circuit.
The output time-sharing multiplex port circuit includes 2N- 2 road timing waveform generation circuits, 2N- 2 road output ports, per road
Timing waveform generation circuit can configure N-bit register, include per road timing waveform generation circuit combinational logic, the second d type flip flop,
First alternative logic circuit, wherein connect sequential control circuit per the input terminal of road timing waveform generation circuit combinational logic
The count value of output, each road timing waveform generation circuit combinational logic respectively translate the count value of sequential control circuit output
Code, obtains 2 other than full 0 and complete 1N- 2 kinds of different timing waveforms, full 0 and complete 1 are used digitally and digital power respectively
Instead of the output end of combinational logic connects the data terminal of the second d type flip flop, and the clock end of the second d type flip flop connects clock signal
CLK, the output end of the second d type flip flop connect an input terminal of the first alternative logic circuit, the first alternative logic circuit
Another input terminal external signal output, the output end of the first alternative logic circuit is connected to output time-sharing multiplex port
The output port of circuit, the pattern switching control letter of the selection end connection sequential control circuit output of the first alternative logic circuit
Number SWITCH.
The configuration input circuit includes N number of waveform sampling circuit, and each waveform sampling circuit compares including 1 second patrols
It collects, 1 the second alternative logic circuit and 1 third d type flip flop, the count value of sequential control circuit output compare second
It is compared with default value in logic, the output end of the second CL Compare Logic connects the second alternative logic circuit gated end, N number of
One of second alternative logic circuit of waveform sampling circuit input terminal is connected in parallel 1 tunnel configuration input port, output
The clock end of the data input pin of end connection third d type flip flop, third d type flip flop connects externally input clock signal clk, the
The output end of 3d flip-flop is divided into two-way, feeds back to another input terminal of the second alternative logic circuit all the way, and another way is defeated
Go out to the configuration register in ethernet PHY card.
The default value of CL Compare Logic corresponds to the counting of timing waveform intermediate time in the input configuration port circuit
Device numerical value.
The present invention has the advantages that compared with prior art：
(1), Ethernet pattern configurations time-sharing multiplex interface circuit structure of the invention is simple, and area is small, low in energy consumption, is easy to
Extension, convenient for being realized on chip.
(2), the present invention has carried out innovative design to Ethernet pattern configurations interface circuit structure, and single pin is configurable more
A register completes Ethernet pattern configurations with less multiplexing pins, saves pin resource, reduces chip cost, facilitate use
Family uses.
Description of the drawings
Fig. 1 is Ethernet pattern configurations time-sharing multiplex interface circuit structure block diagram of the present invention；
Fig. 2 is sequential control circuit structural schematic diagram of the present invention；
Fig. 3 is present invention output time-sharing multiplex port circuit structural schematic diagram；
Fig. 4 is that present invention input configures port circuit structural schematic diagram.
Fig. 5 is eDRAM of the present invention.
Specific implementation mode
The present invention is described in further detail in the following with reference to the drawings and specific embodiments：
One kind provided by the invention for Ethernet pattern configurations time-sharing multiplex interface circuit includes：Sequential control circuit,
Time-sharing multiplex port circuit, input configuration port circuit are exported, wherein：
Sequential control circuit receives externally input reset signal RESET and clock signal clk, right after reset
Externally input clock signal clk is counted, and count value is exported to output time-sharing multiplex port circuit and input and is configured
Port circuit；Output port pattern switching control signal SWITCH is generated to output time-sharing multiplex port electricity according to count value simultaneously
Road；
Time-sharing multiplex port circuit is exported, including 2N- 2 road output ports, per the fixed N bit timing waves of road output port output
Shape, 2NThe output of -2 tunnels adds digital power, digitally, whole 2 needed for covering configuration N-bit registerNKind situation, when SWITCH is
When low, timing waveform is generated into row decoding, and according to decoding value to the count value of sequential control circuit output, and pass through output end
Mouthful by timing waveform Serial output；When SWITCH is high, externally input signal is sent to output port；
Input configuration port circuit connects defeated including the roads M input port and the roads M configure input circuit per input port all the way
Go out the output wherein all the way of time-sharing multiplex port circuit or be directly connected with digital power, digitally, per configuration input electricity all the way
Road is according to the count value of sequential control circuit Counter using time-multiplexed mode to accessing the defeated of the configuration input circuit
The timing waveform of inbound port is sampled, and sampled result is serially written in ethernet PHY piece internal configuration registers, configuration
Ethernet operating mode.
The sequential control circuit includes counter, the first CL Compare Logic, the first d type flip flop and two inputs or door；It is external
The reset signal RESET and clock signal clk of input are separately connected the reset terminal and clock end of counter, and the data of counter are defeated
Outlet is divided into three tunnels, and the data terminal of first via feedback link to counter is loaded into for data；Second tunnel connection first, which is compared, patrols
The input terminal collected, is compared in the first CL Compare Logic with the first default value；Third road is exported to time-sharing multiplex port electricity
Road and input configuration port circuit；The output of first CL Compare Logic is divided into two-way, connects two inputs or an input of door all the way
End, another way connect the data terminal of the first d type flip flop；Another input terminal of two inputs or door connects reset signal RESET, and two is defeated
Enter or the output end feedback link counter of door is loaded into control terminal, for the numerical value at counter data end to be loaded into counter,
First d type flip flop clock end connects clock signal clk, the first d type flip flop output mode switch-over control signal SWITCH to timesharing
Multiplexing port circuit.
The output time-sharing multiplex port circuit includes 2N- 2 road timing waveform generation circuits, 2N- 2 road output ports, per road
Timing waveform generation circuit can configure N-bit register, include per road timing waveform generation circuit combinational logic, the second d type flip flop,
First alternative logic circuit, wherein connect sequential control circuit per the input terminal of road timing waveform generation circuit combinational logic
The count value of output, each road timing waveform generation circuit combinational logic respectively translate the count value of sequential control circuit output
Code, obtains 2 other than full 0 and complete 1N- 2 kinds of different timing waveforms, full 0 and complete 1 are used digitally and digital power respectively
Instead of the output end of combinational logic connects the data terminal of the second d type flip flop, and the clock end of the second d type flip flop connects clock signal
CLK, the output end of the second d type flip flop connect an input terminal of the first alternative logic circuit, the first alternative logic circuit
Another input terminal external signal output, the output end of the first alternative logic circuit is connected to output time-sharing multiplex port
The output port of circuit, the pattern switching control letter of the selection end connection sequential control circuit output of the first alternative logic circuit
Number SWITCH.
The configuration input circuit includes N number of waveform sampling circuit, and each waveform sampling circuit compares including 1 second patrols
It collects, 1 the second alternative logic circuit and 1 third d type flip flop, the count value of sequential control circuit output compare second
It is compared with default value in logic, the output end of the second CL Compare Logic connects the second alternative logic circuit gated end, N number of
One of second alternative logic circuit of waveform sampling circuit input terminal is connected in parallel 1 tunnel configuration input port, output
The clock end of the data input pin of end connection third d type flip flop, third d type flip flop connects externally input clock signal clk, the
The output end of 3d flip-flop is divided into two-way, feeds back to another input terminal of the second alternative logic circuit all the way, and another way is defeated
Go out to the configuration register in ethernet PHY card.
Input configuration port circuit mouth is used to acquire the timing waveform of input port, and ether is written in collected numerical value
It nets in PHY piece internal schema configuration registers, completes the configuration of Ethernet operating mode.Therefore, the input configures port circuit
The default value of middle CL Compare Logic corresponds to the counter values of timing waveform intermediate time, and guarantee is accurately sampled.
Embodiment：
As shown in Figure 1 is Ethernet pattern configurations time-sharing multiplex interface circuit structure block diagram of the present invention, as seen from the figure this hair
Bright Ethernet pattern configurations time-sharing multiplex interface circuit is configured by sequential control circuit, output time-sharing multiplex port circuit, input
Port circuit forms.
Sequential control circuit starts counting up after reset, exports 6 count values and pattern switching controls signal
SWITCH, the waveform that pattern switching controls signal SWITCH are as shown in Figure 5.Pattern switching control signal SWITCH connects output timesharing
The ends SEL of multiplexing port circuit carry out function switch for exporting time-sharing multiplex port circuit.Sequential control circuit counter is defeated
Go out and divide two-way, output all the way connects output time-sharing multiplex port circuit, connects input configuration port circuit all the way.Export time-sharing multiplex end
The output of mouth circuit connects the output port of ethernet PHY piece, and the input of input configuration port circuit terminates the defeated of ethernet PHY piece
Inbound port.User will export the input of the output and input configuration port circuit of time-sharing multiplex port circuit according to service condition
By PCB lines in external interconnections.After chip reset, output time-sharing multiplex port circuit generates timing waveform, and input is matched
It sets port circuit and data sampling is carried out to timing waveform, and sampled result is sent into configuration register, complete hardware configuration, meter
Control mode switch controls signal SWITCH signal saltus steps, output time-sharing multiplex port circuit switching after number device meter to certain numerical value
For the output of function module 1.
Sequential control circuit specific work process is as follows：
When chip is in reset state, RESET pins export high level, counter O reset.After reset, RESET
Pin becomes low level, and counter is started to work, and when count value is equal to 63, comparison circuit 0 exports high electricity, and two or door export high
Level, counter loading signal is effective, i.e., numerical value 63 is inputted in counter and remained unchanged.D type flip flop dff_1 is to comparison circuit
0 output is sampled, output mode switch-over control signal SWITH.
It is illustrated in figure 2 sequential control circuit structural schematic diagram of the present invention, forming and connecting by figure sequential control circuit
Relationship is as follows：
Reset signal RESET connects the reset terminal of counter and the input terminal of two or door or2_1, clock signal clk connect counting
The clock end of device and the clock end of d type flip flop dff_1.Counter exports 6 count values and is divided into 3 tunnels, and the first via connects counter
Data terminal DATAIN [5:0], data are used to be loaded into；Second tunnel connects decoding circuit 0, and signal is controlled for generating pattern switching；The
Three tunnels act on output time-sharing multiplex port circuit and input configuration port circuit.The output of CL Compare Logic 0 divides two-way, connects two all the way
Or door or2_1, the data terminal of d type flip flop dff_1 is connect all the way, the output of two or door or2_1 connects counter and is loaded into control terminal LOAD,
For being loaded into counter data end DATAIN [5:0] data in.D type flip flop dff_1 output mode switch-over control signals
SWITCH, for exporting time-sharing multiplex port circuit function switch.
It is as follows to export time-sharing multiplex port circuit specific work process：
Combinational logic three progress logical operation high to counter, and result is stored in d type flip flop.The choosing of alternative
It selects end S to be controlled by SEL signals, SEL signals meet sequential control circuit pattern switching control signal SWITCH.It is selected when SEL is 1
The A0 input terminals of alternative select the A1 input terminals of alternative when SEL is 0.SEL signals meet the SWITCH of sequential control circuit
End.When after chip reset, the SWITCH of sequential control circuit exports low level, and SEL signals are 0, output time-sharing multiplex end
Timing waveform of the mouth circuit selection output for hardware configuration.When the counter counts in sequential control circuit are to 63, SWITCH
Signal is got higher, and SEL signals are 1, and output port selects the output function of output function module 1.Export time-sharing multiplex port circuit
Per configurable 3 registers all the way.3 registers share 8 kinds of states, respectively：000,001,010,011,100,101,
110,111.As shown in Figure 5：OUT1 is for generating configuration waveform 011；OUT2 is for generating configuration waveform 101；OUT3 is for producing
Raw configuration waveform 001；OUT4 is for generating configuration waveform 110；OUT5 is for generating configuration waveform 010；OUT6 matches for generating
Set waveform 100；State 111 is overall height level, can be generated by digital power；State 000 is full low level, can be by digital real estate
It is raw.OUT1 to OUT6, and digital power and can digitally traverse configuration 3 registers all 8 kinds of states.
It is illustrated in figure 3 present invention output time-sharing multiplex port circuit structural schematic diagram, exports time-sharing multiplex as seen from the figure
The composition and connection relation of port circuit are as follows：
The expression formula of combinational logic 1 is:It is three high that input connects counter, and output connects D triggerings
The data input pin of device dff_2, dff_2 export the A1 input terminals for meeting alternative mux2_2, are exported for hardware configuration waveform, two choosings
The output of the A0 input termination internal logics of one mux2_2, for normally exporting logic function.The expression formula of combinational logic 2 is:Input connects that counter is three high, and output connects the data input pin of d type flip flop dff_3, dff_3 outputs
The A1 input terminals of alternative mux2_3 are connect, are exported for hardware configuration waveform, the A0 input termination internal logics of alternative mux2_3
Output, for normally export logic function.The expression formula of combinational logic 3 is:It is defeated
Enter to connect that counter is three high, output connects the data input pin of d type flip flop dff_4, and the A1 that dff_4 outputs meet alternative mux2_4 is defeated
Enter end, is exported for hardware configuration waveform, the output of the A0 input termination internal logics of alternative mux2_4, for normally exporting
Logic function.The expression formula of combinational logic 4 is:It is three high that input connects counter, and output connects D triggerings
The data input pin of device dff_5, dff_5 export the A1 input terminals for meeting alternative mux2_5, are exported for hardware configuration waveform, two
The A0 of a mux2_5 is selected to input the output of termination internal logic, for normally exporting logic function.The expression formula of combinational logic 5
For: Input connects that counter is three high, and output connects the data input pin of d type flip flop dff_6, dff_6 outputs
The A1 input terminals of alternative mux2_6 are connect, are exported for hardware configuration waveform, the A0 input terminations of alternative mux2_6 are internal to patrol
The output collected, for normally exporting logic function.The expression formula of combinational logic 6 is:Input connects counting
Device is three high, and output connects the data input pin of d type flip flop dff_7, and dff_7 exports the A1 input terminals for meeting alternative mux2_7, uses
It is exported in hardware configuration waveform, the output of the A0 input termination internal logics of alternative mux2_7, for normally exporting logic work(
Energy.
The specific work process of input configuration port circuit is as follows：
CL Compare Logic, which connects, is compared count value, when reaching regulation count value, exports high level pulse, which uses
In the selection end of control alternative circuit.When alternative circuit select end for high level when, by the collected electricity of input port
It is flat to be sent into d type flip flop and preserve, complete the sampling to input data.The output of alternative circuit is sent in configuration register.
CL Compare Logic has at three, for being sampled to the waveform of output time-sharing multiplex port output in three different moments.Compare and patrols
1 is collected as when Counter Value is 12, output SI is high level, remaining moment exports low level；CL Compare Logic 2 is to work as Counter Value
When being 20, output S2 is high level, remaining moment exports low level；CL Compare Logic 3 is when Counter Value is 28, and output S3 is
High level, remaining moment export low level；The output waveform of S1, S2, S3 enter shown in Fig. 5.
It is illustrated in figure 4 present invention input configuration port circuit structural schematic diagram, as seen from the figure input configuration port circuit
Composition and connection relation it is as follows：
The input termination counter output of CL Compare Logic 1, the output termination alternative mux2_8 control terminal S of CL Compare Logic 1,
Mux2_8 input terminals A0 connects input port, is used for acquisition hardware configuration information, and mux2_8 input terminals A1 connects d type flip flop dff_8's
Output end Q.The output Q of the data terminal D, dff_8 of mux2_8 output terminations dff_8 are divided into two-way, connect mux2_8 input terminals all the way
A1 is output to configuration register all the way.
The input termination counter output of CL Compare Logic 2, the output termination alternative mux2_9 control terminal S of CL Compare Logic 2,
Mux2_9 input terminals A0 connects input port, is used for acquisition hardware configuration information, and mux2_9 input terminals A1 connects d type flip flop dff_9's
Output end Q.The output Q of the data terminal D, dff_9 of mux2_9 output terminations dff_9 are divided into two-way, connect mux2_9 input terminals all the way
A1 is output to configuration register all the way.
The input termination counter output of CL Compare Logic 3, the output termination alternative mux2_10 control terminal S of CL Compare Logic 3,
Mux2_10 input terminals A0 connects input port, is used for acquisition hardware configuration information, and mux2_10 input terminals A1 meets d type flip flop dff_10
Output end Q.The output Q of the data terminal D, dff_10 of mux2_10 output terminations dff_10 are divided into two-way, meet mux2_10 all the way
Input terminal A1, is output to configuration register all the way.
The above, best specific implementation mode only of the invention, but scope of protection of the present invention is not limited thereto,
Any one skilled in the art in the technical scope disclosed by the present invention, the change or replacement that can be readily occurred in,
It should be covered by the protection scope of the present invention.
The content that description in the present invention is not described in detail belongs to the known technology of professional and technical personnel in the field.
Claims (5)
1. one kind being used for Ethernet pattern configurations time-sharing multiplex interface circuit, it is characterised in that including：Sequential control circuit, output
Time-sharing multiplex port circuit, input configuration port circuit, wherein：
Sequential control circuit receives externally input reset signal RESET and clock signal clk, after reset, to outside
The clock signal clk of input is counted, and count value is exported to output time-sharing multiplex port circuit and input configuration port
Circuit；Output port pattern switching control signal SWITCH is generated to output time-sharing multiplex port circuit according to count value simultaneously；
Time-sharing multiplex port circuit is exported, including 2N- 2 road output ports, per road output port output N bit timing waveforms, 2N- 2 tunnels
Output, in addition digital power, digitally, whole 2 needed for covering configuration N-bit registerNKind situation is right when SWITCH is low
Sequential control circuit output count value into row decoding, and according to decoding value generate timing waveform, and by output port by when
Sequence waveform Serial output；When SWITCH is high, externally input signal is sent to output port, N >=1；
Input configuration port circuit connects output point including the roads M input port and the roads M configure input circuit per input port all the way
When the output wherein all the way of multiplexing port circuit or be directly connected with digital power, digitally, per configuring input circuit root all the way
According to the count value of sequential control circuit Counter using time-multiplexed mode to accessing the input terminal of the configuration input circuit
The timing waveform of mouth is sampled, and sampled result is serially written in ethernet PHY piece internal configuration registers, configures ether
Net operating mode.
2. according to claim 1 a kind of for Ethernet pattern configurations time-sharing multiplex interface circuit, it is characterised in that：Institute
It includes counter, the first CL Compare Logic, the first d type flip flop and two inputs or door to state sequential control circuit；
Externally input reset signal RESET and clock signal clk are separately connected the reset terminal and clock end of counter, counter
Data output end be divided into three tunnels, the data terminal of first via feedback link to counter is loaded into for data；Second tunnel connection the
The input terminal of one CL Compare Logic is compared in the first CL Compare Logic with the first default value；Third road exports multiple to timesharing
With port circuit and input configuration port circuit；The output of first CL Compare Logic is divided into two-way, connects two inputs or door all the way
One input terminal, another way connect the data terminal of the first d type flip flop；Another input terminal of two inputs or door connects reset signal
The output end feedback link counter of RESET, two inputs or door is loaded into control terminal, for the numerical value at counter data end to be loaded into
In counter, the first d type flip flop clock end connects clock signal clk, the first d type flip flop output mode switch-over control signal
SWITCH is to time-sharing multiplex port circuit.
3. according to claim 1 a kind of for Ethernet pattern configurations time-sharing multiplex interface circuit, it is characterised in that：Institute
It includes 2 to state output time-sharing multiplex port circuitN- 2 road timing waveform generation circuits, 2N- 2 road output ports, per the production of road timing waveform
Raw circuit can configure N-bit register, include combinational logic, the second d type flip flop, the first alternative per road timing waveform generation circuit
Logic circuit, wherein the counting of sequential control circuit output is connect per the input terminal of road timing waveform generation circuit combinational logic
Value, each road timing waveform generation circuit combinational logic are removed respectively to the count value of sequential control circuit output into row decoding
2 except full 0 and complete 1N- 2 kinds of different timing waveforms, full 0 and complete 1 combine respectively with digitally being replaced with digital power
The output end of logic connects the data terminal of the second d type flip flop, and the clock end of the second d type flip flop connects clock signal clk, the 2nd D
The output end of trigger connects an input terminal of the first alternative logic circuit, and another of the first alternative logic circuit is defeated
Enter to hold the output of external signal, the output end of the first alternative logic circuit is connected to the output of output time-sharing multiplex port circuit
Port, the pattern switching control signal SWITCH of the selection end connection sequential control circuit output of the first alternative logic circuit.
4. according to claim 1 a kind of for Ethernet pattern configurations time-sharing multiplex interface circuit, it is characterised in that：Institute
It includes N number of waveform sampling circuit to state configuration input circuit, each waveform sampling circuit include 1 the second CL Compare Logic, 1 second
Alternative logic circuit and 1 third d type flip flop, the count value of sequential control circuit output are in the second CL Compare Logic and pre-
If numerical value is compared, the output end of the second CL Compare Logic connects the second alternative logic circuit gated end, N number of waveform sampling electricity
One of the second alternative logic circuit on road input terminal is connected in parallel 1 tunnel configuration input port, and output end connects the 3rd D
The clock end of the data input pin of trigger, third d type flip flop connects externally input clock signal clk, third d type flip flop
Output end is divided into two-way, feeds back to another input terminal of the second alternative logic circuit all the way, and another way is output to Ethernet
Configuration register in PHY cards.
5. according to claim 1 a kind of for Ethernet pattern configurations time-sharing multiplex interface circuit, it is characterised in that：Institute
The default value for stating CL Compare Logic in input configuration port circuit corresponds to the counter values of timing waveform intermediate time.
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| CN110705192B (en) * | 2019-09-20 | 2022-03-22 | 浪潮(北京)电子信息产业有限公司 | Output power consumption configuration circuit and system of FPGA and FPGA |
| CN110855916A (en) * | 2019-11-22 | 2020-02-28 | 中国电子科技集团公司第四十四研究所 | Analog signal reading circuit array with variable output channel number and reading method |
| CN110855916B (en) * | 2019-11-22 | 2021-12-24 | 中国电子科技集团公司第四十四研究所 | Analog signal reading circuit array with variable output channel number and reading method |
| CN112071219A (en) * | 2020-09-18 | 2020-12-11 | 深圳市奥拓电子股份有限公司 | Adapter plate, LED display box body and LED display screen |
| CN112071219B (en) * | 2020-09-18 | 2022-08-26 | 深圳市奥拓电子股份有限公司 | Adapter plate, LED display box body and LED display screen |
| CN113704157A (en) * | 2021-08-04 | 2021-11-26 | 威创集团股份有限公司 | System for controlling multipath different-level reset signals based on bus |
| CN113704157B (en) * | 2021-08-04 | 2024-04-02 | 威创集团股份有限公司 | System for controlling multipath reset signals with different levels based on bus |
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