CN113704157A - System for controlling multipath different-level reset signals based on bus - Google Patents
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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Abstract
The invention provides a system for controlling multi-channel different-level reset signals based on a bus, which comprises a control unit and at least one extension unit, wherein the control unit is used for controlling the extension unit to extend the extension unit; the extension unit is provided with a plurality of reset signal output interfaces; the control unit is connected with the extension unit through a bus and used for controlling the extension unit to output a reset signal; the extension unit is connected with an external system through the reset signal output interface and is used for outputting the reset signal to the external system through the reset signal output interface under the control of the control unit so as to reset the external system according to the reset signal. The control unit is connected with the plurality of extension units by adopting the bus, so that the output of multiple paths of different reset signals can be realized without occupying a plurality of IO interfaces of the control unit.
Description
Technical Field
The invention relates to the field of port expansion, in particular to a system for controlling multiple paths of reset signals with different levels based on a bus.
Background
With the gradual improvement of the system integration level, the number of external chips to be controlled in the system is increasing, so that the number of resets of the external chips to be controlled is also increasing.
At present, in order to realize the expansion of the I/O port of the main processing chip, a plurality of expansion circuits are usually realized by additionally arranging a complex peripheral circuit, which not only increases the production cost, but also occupies a larger space of a PCB circuit, makes the circuit design complex and is not beneficial to the miniaturization of products. There may be some prior arts that the reset circuit is expanded by using a decoder, for example, a 38 decoder is used to realize that 3 GPIO ports drive 8-way reset signal output, but the expansion of the reset circuit by using the decoder needs to occupy 3 GPIO ports of the main processing chip, and the number of the expansion is limited, and only 8 bits can be expanded.
Disclosure of Invention
The present invention is directed to overcome at least one of the above-mentioned drawbacks of the prior art, and provides a system for controlling multiple paths of different level reset signals based on a bus, so as to implement extension of multiple paths of different level reset signals.
The scheme adopted by the invention is as follows:
the system for controlling a plurality of paths of reset signals with different levels based on a bus comprises a control unit and at least one extension unit;
the extension unit is provided with a plurality of reset signal output interfaces;
the control unit is connected with the extension unit through a bus and used for controlling the extension unit to output a reset signal;
the extension unit is connected with an external system through the reset signal output interface and is used for outputting the reset signal to the external system through the reset signal output interface under the control of the control unit so as to reset the external system according to the reset signal.
The control unit is connected with the expansion unit by adopting a bus, the control unit can control the expansion unit by the bus, and the number of control unit ports occupied by the connection of the expansion unit and the control unit can be reduced; the control unit is connected with the extension unit provided with a plurality of reset signal output interfaces through a bus, and can simultaneously control the output of multiple paths of different reset signals to realize the extension of the reset signals.
Furthermore, the expansion unit is provided with a register and a plurality of IO interfaces, the working states of the IO interfaces comprise an input state and an output state, and the register is connected with the control unit;
the control unit is further configured to write the configuration information into the register, where the configuration information is used to set a working state of an IO interface to be configured as the reset signal output interface to an output state;
and the extension unit is further used for configuring the working state of the IO interface according to the configuration information.
The expansion unit sets the working state of the IO interface to be configured as the reset signal output interface as the output state according to the configuration information written into the register by the control unit, so that the subsequent control unit controls the expansion unit to output the reset signal through the reset signal output interface, and the output of multiple paths of different reset signals is realized.
Furthermore, the extension unit is provided with a register, and the register is connected with the control unit;
the control unit is used for controlling the extension unit to output a reset signal, and specifically comprises:
the control unit is used for writing control information into the register;
the extension unit is used for outputting the reset signal to an external system through the reset signal output interface under the control of the control unit, and specifically comprises:
and the extension unit is used for outputting a reset signal to an external system through a reset signal output interface according to the control information.
The control unit writes control information into a register of the extension unit through the bus, so that the extension unit can output a reset signal to an external system through the reset signal output interface according to the control information written by the control unit, and output of multiple paths of different reset signals is realized.
Further, the control unit is configured to write control information to the register, specifically:
the control unit is used for writing 0 or 1 into the register;
the extension unit is used for outputting a reset signal to an external system through the reset signal output interface according to the control information, and specifically comprises:
the extension unit is used for controlling the reset signal output interface to output a low-level reset signal or a high-level reset signal according to the value of 0 or 1 written in the register.
The control unit writes 0 or 1 into the register through the bus, the extension unit controls the reset signal output interface to output a low-level reset signal or a high-level reset signal according to the 0 or 1 written into the register, and the extension unit is suitable for an external system which resets after receiving the low-level reset signal and can also be suitable for an external system which resets after receiving the high-level reset signal, so that the universality of different external systems is improved.
Furthermore, the extension unit is further provided with an address configuration interface, the address configuration interface is used for setting address information of the extension unit, and different extension units correspond to different address information;
the control unit is used for controlling the extension unit to output a reset signal, and specifically comprises:
and the control unit is used for controlling the corresponding expansion unit according to the address information so as to enable the corresponding expansion unit to output a reset signal.
The control unit finds the corresponding extension unit to be controlled according to the address of the extension unit, the control unit can write the control information into the register of the corresponding extension unit according to the corresponding address information, and the extension unit can control the reset signal output interface to output the reset signal according to the control information written by the control unit.
Furthermore, the system also comprises a plurality of level conversion units, wherein the input end of one level conversion unit is correspondingly connected with one reset signal output interface, and the output end of the level conversion unit is connected with the external system;
the level conversion unit is used for converting the reset signal into a voltage signal.
The reset signal output interface is connected with an external system through the level conversion unit, and the level conversion unit converts the reset signal into a voltage signal, so that the expansion unit can be connected with a plurality of external systems which need different voltages to realize resetting.
Further, the level conversion unit comprises a power supply, an N-channel MOS tube, a capacitor and a first resistor;
the drain electrode of the N-channel MOS tube is connected with the reset signal output interface, the grid electrode of the N-channel MOS tube is connected with the power supply, the source electrode of the N-channel MOS tube is respectively connected with the external system, one end of the first resistor and one end of the capacitor, the other end of the first resistor is connected with the power supply, and the other end of the capacitor is connected with the ground end.
The power supply, the N-channel MOS tube, the capacitor and the first resistor form a level conversion unit, so that the aim of converting a reset signal into a voltage signal required by an external system is fulfilled, the circuit structure is simple, and the cost is reduced; in addition, the voltage of the power supply can be set according to different external systems, and the application range is wide.
Furthermore, the level conversion unit further comprises a second resistor, and the drain of the N-channel MOS transistor is connected to the reset signal output interface through the second resistor.
Furthermore, the level conversion unit further comprises a third resistor, and the source electrode of the N-channel MOS transistor is connected to the external system through the third resistor.
Further, the control unit is connected with the expansion unit through an I2C bus.
The connection between the control unit and the expansion units is realized by adopting I2C, and the I2C can realize the control of a plurality of expansion units by only occupying two ports of the control unit, so that the output of a plurality of paths of reset signals can be controlled.
Compared with the prior art, the invention has the beneficial effects that: the control unit is connected with the expansion unit by adopting the bus, and can control the expansion unit by the control unit through the bus, so that the number of control unit ports occupied by the connection of the expansion unit and the control unit can be reduced; the control unit is connected with the extension unit provided with a plurality of reset signal output interfaces through a bus, so that the control unit can simultaneously control the output of a plurality of paths of different reset signals through the bus, and the extension of the reset signals is realized.
Drawings
FIG. 1 is a block diagram of a system according to an embodiment;
fig. 2 is a circuit diagram of a level shift unit according to an embodiment.
Detailed Description
The drawings are only for purposes of illustration and are not to be construed as limiting the invention. For a better understanding of the following embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise explicitly specified or limited, terms such as "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
As shown in fig. 1, in one embodiment, a system for controlling multiple different level reset signals based on a bus is provided, which includes a control unit and at least one extension unit;
the extension unit is provided with a plurality of reset signal output interfaces;
the control unit is connected with the extension unit through a bus and used for controlling the extension unit to output a reset signal;
the extension unit is connected with an external system through the reset signal output interface and is used for outputting the reset signal to the external system through the reset signal output interface under the control of the control unit so as to reset the external system according to the reset signal.
In one embodiment, the control unit is connected to the expansion unit via an I2C bus.
Specifically, the control unit may be connected to the expansion unit through an I2C bus, or may be connected to the expansion unit through an SMBUS bus; the control unit is connected with a plurality of extension units through a bus, the types of m extension units can be the same or not completely the same, wherein m is the number of the extension units, and the number of the extension units can be set according to an external system to be connected, and is not limited herein; the expansion units can be IO expansion chips with the models of PCA9555 and TCA9539, each expansion unit is provided with n reset signal output interfaces, the number of the reset signal output interfaces arranged on different expansion units can be different or the same, wherein n is the number of the reset signal output interfaces; the control chip can be MCU/CPU/FPGA or the like; preferably, the control unit is connected with the expansion unit through an I2C bus, the expansion unit adopts an IO expansion chip with a model of PCA9555, an SDA interface of the control unit is connected with an SDA interface of the expansion unit through an I2C bus, and an SCL interface of the control unit is connected with an SCL interface of the expansion unit through an I2C bus; and the power supply port of the expansion unit is also connected with a 5V direct-current power supply to ensure the normal work of the expansion unit.
The control unit is connected with the expansion unit by adopting a bus, the control unit can control the expansion unit by the bus, and the number of control unit ports occupied by the connection of the expansion chip and the control unit can be reduced; the control unit is connected with the extension unit provided with a plurality of reset signal output interfaces through a bus, and can control the output of multiple paths of different reset signals to realize the extension of the reset signals.
In one embodiment, the expansion unit is provided with a register and a plurality of IO interfaces, the operating states of the IO interfaces include an input state and an output state, and the register is connected with the control unit;
the control unit is further configured to write the configuration information into the register, where the configuration information is used to set a working state of an IO interface to be configured as the reset signal output interface to an output state;
and the extension unit is further configured to configure the working state of the IO interface according to the configuration information.
In one embodiment, the extension unit is further provided with an address configuration interface, the address configuration interface is used for setting address information of the extension unit, and different extension units correspond to different address information;
the control unit is used for controlling the extension unit to output a reset signal, and specifically comprises:
and the control unit is used for controlling the corresponding expansion unit according to the address information so as to enable the corresponding expansion unit to output a reset signal.
Specifically, three address configuration interfaces of the expansion unit are connected with a 5V direct-current power supply through an external pull-up resistor or pull-down resistor, the address configuration interfaces of the expansion unit are three, the address information of the expansion unit is set through the pull-up resistor or the pull-down resistor connected with each address configuration interface, and different expansion units correspond to different address information; after the address configuration interface sets the address information of the extension unit, the address information is transmitted to a register to be stored; the method comprises the steps that a plurality of IO interfaces of an extension unit can be configured to be in an input state or an output state, each IO interface is preset with an interface number, when the IO interfaces are not set to be in the input state or the output state, the IO interfaces are in a high-resistance state in a default mode, a control unit reads address information and configuration information stored in a register through a bus, and then the working state of the IO interfaces, serving as reset signal output interfaces, of the extension unit corresponding to the address information is set to be in the output state according to the address information and the configuration information.
The control unit writes configuration information into a register of the extension unit, and the extension unit sets the working state of an IO interface to be configured as a reset signal output interface as an output state according to the configuration information, so that a subsequent control unit controls the extension unit to output a reset signal through the reset signal output interface, and output of multiple paths of different reset signals is realized; the control unit controls the corresponding extension unit according to the address of the extension unit, the control unit can write control information into a register of the corresponding extension unit according to the corresponding address information, and the extension unit can output a reset signal through the reset signal output interface according to the control information written by the control unit, so that the output of multiple paths of different reset signals is realized.
In one embodiment, the extension unit is provided with a register, and the register is connected with the control unit;
the control unit is used for controlling the extension unit to output a reset signal, and specifically comprises:
the control unit is used for writing control information into the register;
the extension unit is used for outputting the reset signal to an external system through the reset signal output interface under the control of the control unit, and specifically comprises:
and the extension unit is used for outputting a reset signal to an external system through the reset signal output interface according to the control information.
The control unit writes control information into a register of the extension unit through the bus, so that the extension unit can output a reset signal through the reset signal output interface according to the control information written by the control unit, and output of multiple paths of different reset signals is realized.
In one embodiment, the control unit is configured to write control information to the register, and specifically includes:
the control unit is used for writing 0 or 1 into the register;
the extension unit is used for outputting a reset signal to an external system through the reset signal output interface according to the control information, and specifically comprises:
and the extension unit is used for outputting a low-level reset signal or a high-level reset signal through the reset signal output interface according to the condition that the number written into the register is 0 or 1.
Specifically, the control unit reads address information stored in a register of the extension unit through a bus, writes control information corresponding to a reset signal required by an external system into the register according to the read address information, writes 0 into the register when the reset signal required by the external system is a low-level reset signal, and controls a corresponding reset signal output interface to output the low-level reset signal according to the 0 written into the register by the extension unit; when the reset signal required by the external system is a high-level reset signal, the control unit writes 1 into the register, and the expansion unit controls the corresponding reset signal output interface to output the high-level reset signal according to the 1 written into the register; it is understood that "high" and "low" describe the magnitude of the signal amplitude, and that "high" and "low" are relative terms, for example, the low level reset signal may be a voltage signal with an amplitude of 0V, the high level reset signal may be a voltage signal with an amplitude of 5V, 0V is a low level reset signal with respect to 5V, and 5V is a high level reset signal with respect to 0V.
The control unit writes 0 or 1 into the register through the bus, the extension unit can control the reset signal output interface to output a low-level reset signal or a high-level reset signal according to the 0 or 1 written into the register, and the extension unit is suitable for an external system which resets after receiving the low-level reset signal and also suitable for an external system which resets after receiving the high-level reset signal, so that the universality of different external systems is improved.
In one embodiment, the system further includes a plurality of level shift units, an input end of one of the level shift units is correspondingly connected to one of the reset signal output interfaces, and an output end of the level shift unit is connected to the external system;
the level conversion unit is used for converting the reset signal into a voltage signal.
The reset signal output interface is connected with an external system through the level conversion unit, and the level conversion unit converts the reset signal into a voltage signal, so that the extension unit can be connected with a plurality of external systems which need different voltages to realize reset, and the output of a plurality of paths of reset signals with different levels is realized.
As shown in fig. 2, in one embodiment, the level shift unit includes a power supply, an N-channel MOS transistor, a capacitor C1, and a first resistor;
the drain electrode of the N-channel MOS tube is connected with the reset signal output interface, the grid electrode of the N-channel MOS tube is connected with the power supply, the source electrode of the N-channel MOS tube is respectively connected with the external system, one end of the first resistor and one end of the capacitor, the other end of the first resistor is connected with the power supply, and the other end of the capacitor is connected with the ground end.
The power supply, the N-channel MOS tube, the capacitor and the first resistor form a level conversion unit, so that the aim of converting a reset signal into a voltage signal required by an external system is fulfilled, the circuit structure is simple, and the cost is reduced; in addition, the voltage of the power supply can be set according to different external systems, and the application range is wide.
Specifically, the voltage value range of the power supply VDDn is 0.8V-5V, which can be set according to a voltage signal required by an external system, and can be generally set to common voltage values such as 1V,1.2V,1.5V,1.8V,2.5V,3.3V,5V, and the like; when the reset signal is a high-level reset signal, because the power supply VDDN of the source electrode is less than or equal to 5V, the diode between the drain electrode and the source electrode of the N-channel MOS tube is not conducted, and the voltage signal at one end of the N-channel MOS tube, which is connected with an external system, is pulled up to the voltage VDDN by the first resistor, so that the level conversion unit outputs the voltage signal with the voltage value equal to the voltage value of the power supply VDDN to the external system; when the reset signal is a low-level reset signal, because the voltage of the source is higher than 0.8V, the source of the N-channel MOS tube is conducted to the drain in the forward direction through the diode, and the voltage signal of one end, connected with an external system, of the N-channel MOS tube is pulled down to the low-level reset signal, namely 0V, by the drain.
In one embodiment, the level shift unit further includes a second resistor, and the drain of the N-channel MOS transistor is connected to the reset signal output interface through the second resistor.
In one embodiment, the level shift unit further includes a third resistor, and the source of the N-channel MOS transistor is connected to the external system through the third resistor.
Specifically, the working process and principle of the system for controlling multiple paths of reset signals with different levels based on the bus described in this embodiment are as follows: the control unit is connected with a plurality of expansion units through an I2C bus, each expansion unit is provided with a register, an address configuration interface and a plurality of IO interfaces, the number of the address configuration interfaces is three, each address configuration interface is connected with an external pull-up resistor or pull-down resistor, so that the control unit is connected with 8 expansion units through an I2C bus, the address information range of the 8 expansion units is 000-111, the address information is stored in the register, the number of the IO interfaces of the expansion units can be 16 or 8, and the control unit is specifically determined according to an adopted expansion chip; taking an expansion unit with 8 IO interfaces as an example, the interface number of the 8 IO interfaces is P00-P07, each IO interface is connected with an external system, when the external system needs to be reset, the control unit reads address information stored in the register through the I2C bus, configures the corresponding IO interface into an output state according to the address information, so that the corresponding IO interface is a reset signal output interface, and writes 0 or 1 into the register through the I2C interface according to the read address information and a reset signal required by the external system, so that the expansion unit controls the corresponding reset signal output interface to output a low-level reset signal or a high-level reset signal, when the reset signal output interface outputs the low-level reset signal, because the voltage of the source of the N-channel MOS transistor is higher than 0.8V, the source of the N-channel MOS transistor is forward conducted to the drain through the diode, a voltage signal at one end of the N-channel MOS tube connected with an external system is pulled down to a low level reset signal, namely 0V, by a drain electrode; when the reset signal output interface outputs a high-level reset signal, because the voltage VDDN of the source electrode is less than or equal to 5V, the diode between the drain electrode and the source electrode of the N-channel MOS tube is not conducted, and the voltage signal at one end of the N-channel MOS tube, which is connected with an external system, is pulled up to the voltage VDDN by the first resistor, so that the level conversion unit outputs the voltage signal with the voltage value equal to the voltage VDDN to the external system; the control unit of this embodiment is connected with a plurality of extension units through the I2C bus, thereby realizing that the output of multiple paths of different reset signals can be realized without occupying a plurality of IO interfaces of the control unit.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the technical solutions of the present invention, and are not intended to limit the specific embodiments of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention claims should be included in the protection scope of the present invention claims.
Claims (10)
1. A system for controlling a plurality of paths of reset signals with different levels based on a bus is characterized by comprising a control unit and at least one extension unit;
the extension unit is provided with a plurality of reset signal output interfaces;
the control unit is connected with the extension unit through a bus and used for controlling the extension unit to output a reset signal;
the extension unit is connected with an external system through the reset signal output interface and is used for outputting the reset signal to the external system through the reset signal output interface under the control of the control unit so as to reset the external system according to the reset signal.
2. The system for controlling the multi-path reset signals with different levels based on the bus according to claim 1, wherein the extension unit is provided with a register and a plurality of IO interfaces, the working states of the IO interfaces comprise an input state and an output state, and the register is connected with the control unit;
the control unit is further configured to write the configuration information into the register, where the configuration information is used to set a working state of an IO interface to be configured as the reset signal output interface to an output state;
and the extension unit is further used for configuring the working state of the IO interface according to the configuration information.
3. The system for controlling the multiple paths of reset signals with different levels based on the bus as claimed in claim 1, wherein the extension unit is provided with a register, and the register is connected with the control unit;
the control unit is used for controlling the extension unit to output a reset signal, and specifically comprises:
the control unit is used for writing control information into the register;
the extension unit is used for outputting the reset signal to an external system through the reset signal output interface under the control of the control unit, and specifically comprises:
and the extension unit is used for outputting a reset signal to an external system through the reset signal output interface according to the control information.
4. The system according to claim 3, wherein the control unit is configured to write control information into the register, specifically:
the control unit is used for writing 0 or 1 into the register;
the extension unit is used for outputting a reset signal to an external system through the reset signal output interface according to the control information, and specifically comprises:
and the extension unit is used for outputting a low-level reset signal or a high-level reset signal through the reset signal output interface according to the condition that the number written into the register is 0 or 1.
5. The system for controlling multiple paths of reset signals with different levels based on the bus as claimed in claim 1, wherein the expansion unit is further provided with an address configuration interface, the address configuration interface is used for setting address information of the expansion unit, and different expansion units correspond to different address information;
the control unit is used for controlling the extension unit to output a reset signal, and specifically comprises:
and the control unit is used for controlling the corresponding expansion unit according to the address information so as to enable the corresponding expansion unit to output a reset signal.
6. The system for controlling multiple reset signals with different levels based on the bus according to any one of claims 1-5, further comprising a plurality of level shifting units, wherein the input end of one of the level shifting units is correspondingly connected with one of the reset signal output interfaces, and the output end of the level shifting unit is connected with the external system;
the level conversion unit is used for converting the reset signal into a voltage signal.
7. The system for controlling the multiple different-level reset signals based on the bus of claim 6, wherein the level conversion unit comprises a power supply, an N-channel MOS (metal oxide semiconductor) transistor, a capacitor and a first resistor;
the drain electrode of the N-channel MOS tube is connected with the reset signal output interface, the grid electrode of the N-channel MOS tube is connected with the power supply, the source electrode of the N-channel MOS tube is respectively connected with the external system, one end of the first resistor and one end of the capacitor, the other end of the first resistor is connected with the power supply, and the other end of the capacitor is connected with the ground end.
8. The system according to claim 7, wherein the level shifter unit further comprises a second resistor, and the drain of the N-channel MOS transistor is connected to the reset signal output interface through the second resistor.
9. The system according to claim 7, wherein the level shifter unit further comprises a third resistor, and the source of the N-channel MOS transistor is connected to the external system through the third resistor.
10. A system for controlling multiple different level reset signals according to any one of claims 1-5 and 7-9, wherein said control unit is connected to said expansion unit via an I2C bus.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114326370A (en) * | 2021-12-31 | 2022-04-12 | 上海节卡机器人科技有限公司 | Extended output circuit system and control method |
| CN114564428A (en) * | 2022-01-19 | 2022-05-31 | 中国电子科技集团公司第十研究所 | Airborne electronic equipment I/O port expansion system |
| CN117478114A (en) * | 2023-12-28 | 2024-01-30 | 深圳市森威尔科技开发股份有限公司 | Reset circuit, and multi-path reset circuit and device with single IO port independently controlled |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5742841A (en) * | 1993-12-08 | 1998-04-21 | Packard Bell Nec | Alternate I/O port access to standard register set |
| US5752063A (en) * | 1993-12-08 | 1998-05-12 | Packard Bell Nec | Write inhibited registers |
| CN102957415A (en) * | 2011-08-29 | 2013-03-06 | 中兴通讯股份有限公司 | Level converting method and level converting system |
| JP2015018408A (en) * | 2013-07-11 | 2015-01-29 | コニカミノルタ株式会社 | Input/output control circuit and synchronization control method in input/output control circuit |
| CN205486087U (en) * | 2016-03-29 | 2016-08-17 | 安徽工程大学 | PCI bus interface card based on PCI9052 |
| CN107544300A (en) * | 2017-08-21 | 2018-01-05 | 珠海格力电器股份有限公司 | A kind of interface processing device and its control method |
| CN107659301A (en) * | 2016-07-25 | 2018-02-02 | 国基电子（上海）有限公司 | Level shifting circuit and interface communication systems |
| CN207625572U (en) * | 2017-11-20 | 2018-07-17 | 北京时代民芯科技有限公司 | One kind being used for Ethernet pattern configurations time-sharing multiplex interface circuit |
| US20180293780A1 (en) * | 2017-04-10 | 2018-10-11 | Intel Corporation | Dual path sequential element to reduce toggles in data path |
| CN108923779A (en) * | 2018-07-09 | 2018-11-30 | 威创集团股份有限公司 | Signal multiplexing circuit and method |
| CN109407807A (en) * | 2018-09-29 | 2019-03-01 | 上海东软载波微电子有限公司 | A kind of chip reset circuit, repositioning method and MCU chip |
| CN109491946A (en) * | 2018-11-12 | 2019-03-19 | 郑州云海信息技术有限公司 | A kind of chip and method for I2C bus extension |
| CN110781119A (en) * | 2019-10-22 | 2020-02-11 | 广东高云半导体科技股份有限公司 | I2C bus expansion interface, control method thereof and system on chip |
| CN112051758A (en) * | 2019-06-06 | 2020-12-08 | 广东省大金创新电子有限公司 | IO extension chip |
-
2021
- 2021-08-04 CN CN202110892099.0A patent/CN113704157B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5742841A (en) * | 1993-12-08 | 1998-04-21 | Packard Bell Nec | Alternate I/O port access to standard register set |
| US5752063A (en) * | 1993-12-08 | 1998-05-12 | Packard Bell Nec | Write inhibited registers |
| CN102957415A (en) * | 2011-08-29 | 2013-03-06 | 中兴通讯股份有限公司 | Level converting method and level converting system |
| JP2015018408A (en) * | 2013-07-11 | 2015-01-29 | コニカミノルタ株式会社 | Input/output control circuit and synchronization control method in input/output control circuit |
| CN205486087U (en) * | 2016-03-29 | 2016-08-17 | 安徽工程大学 | PCI bus interface card based on PCI9052 |
| CN107659301A (en) * | 2016-07-25 | 2018-02-02 | 国基电子（上海）有限公司 | Level shifting circuit and interface communication systems |
| US20180293780A1 (en) * | 2017-04-10 | 2018-10-11 | Intel Corporation | Dual path sequential element to reduce toggles in data path |
| CN107544300A (en) * | 2017-08-21 | 2018-01-05 | 珠海格力电器股份有限公司 | A kind of interface processing device and its control method |
| CN207625572U (en) * | 2017-11-20 | 2018-07-17 | 北京时代民芯科技有限公司 | One kind being used for Ethernet pattern configurations time-sharing multiplex interface circuit |
| CN108923779A (en) * | 2018-07-09 | 2018-11-30 | 威创集团股份有限公司 | Signal multiplexing circuit and method |
| CN109407807A (en) * | 2018-09-29 | 2019-03-01 | 上海东软载波微电子有限公司 | A kind of chip reset circuit, repositioning method and MCU chip |
| CN109491946A (en) * | 2018-11-12 | 2019-03-19 | 郑州云海信息技术有限公司 | A kind of chip and method for I2C bus extension |
| CN112051758A (en) * | 2019-06-06 | 2020-12-08 | 广东省大金创新电子有限公司 | IO extension chip |
| CN110781119A (en) * | 2019-10-22 | 2020-02-11 | 广东高云半导体科技股份有限公司 | I2C bus expansion interface, control method thereof and system on chip |
Non-Patent Citations (1)
| Title |
|---|
| 王开然等: ""用SPI器件扩展神经元芯片"", 《传感器世界》, 31 May 2006 (2006-05-31), pages 36 - 40 * |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114326370A (en) * | 2021-12-31 | 2022-04-12 | 上海节卡机器人科技有限公司 | Extended output circuit system and control method |
| CN114326370B (en) * | 2021-12-31 | 2024-04-30 | 节卡机器人股份有限公司 | Extended output circuit system and control method |
| CN114564428A (en) * | 2022-01-19 | 2022-05-31 | 中国电子科技集团公司第十研究所 | Airborne electronic equipment I/O port expansion system |
| CN117478114A (en) * | 2023-12-28 | 2024-01-30 | 深圳市森威尔科技开发股份有限公司 | Reset circuit, and multi-path reset circuit and device with single IO port independently controlled |
| CN117478114B (en) * | 2023-12-28 | 2024-03-08 | 深圳市森威尔科技开发股份有限公司 | Reset circuit, and multi-path reset circuit and device with single IO port independently controlled |
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