CN104617924B - High-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop - Google Patents

High-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop Download PDF

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CN104617924B
CN104617924B CN201510061904.XA CN201510061904A CN104617924B CN 104617924 B CN104617924 B CN 104617924B CN 201510061904 A CN201510061904 A CN 201510061904A CN 104617924 B CN104617924 B CN 104617924B
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circuit
grid
low
input signal
connects
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CN104617924A (en
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胡封林
刘衡竹
鲁建壮
扈啸
万江华
孙书为
陈小文
陈胜刚
雷元武
许邦建
亓磊
刘蓉容
高新军
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National University of Defense Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the master-slave type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption

Abstract

A kind of high-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop, comprising: low power consumpting controling circuit, receives low power consumption control input signal slp, output signal after carrying out buffered to low power consumption control input signal slp; Set control circuit, receives asynchronous set input signal set, outputs signal respectively after carrying out buffered to asynchronous set input signal set; Select control circuit, receive and select data to squeeze into inhibit signal sel, selection data are squeezed into after inhibit signal sel carries out buffered and outputs signal respectively; Main latch, receives data input signal d, non-inverting clock input signal clk, inversion clock input signal nclk, asynchronous reset input signal r, selects data to squeeze into inhibit signal sel and signal sleep, nsleep, s and ns; And export qt after latch process is carried out to data input signal d; Export respectively after latch carries out latch process to qt.The present invention have structure simple, efficiency of transmission can be improved, reduce the advantage such as static leakage current and power consumption.

Description

High-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop
Technical field
The present invention is mainly concerned with large scale integrated circuit design field, refers in particular to a kind of high-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop.
Background technology
Along with improving constantly of technology, current VLSI (very large scale integrated circuit) designs has entered the deep-submicron stage.The reduction of characteristic size, will inevitably bring the reduction of the threshold voltage of MOS device, makes the exponentially form rising along with the reduction of characteristic size of the leakage current of circuit, directly causes circuit leakage current power consumption and increase sharply.The quiescent dissipation brought by leakage current can not be out in the cold.
Be operated in the system within the scope of GHz, its power consumption reaches tens w, or even more than hundreds of w.Excessive power consumption brings a series of problem, has become a significant obstacle of very lagre scale integrated circuit (VLSIC) development.High power consumption result in the high temperature of chip temperature.The fault that the rising of working temperature not only makes the various physical imperfections of circuit cause displays, and high working temperature makes the connection resistances of circuit become large, and line time delay increases, and causes serious delay failure.Meanwhile, the rising of working temperature will cause the increase of leakage current, the work of chip internal easily be lost efficacy, the lost of life etc.These reliabilities that finally result in circuit reduce greatly.There are some researches show, temperature often raises 10 oc, the failure rate of device just improves 2 times.
Low power design technique is through from system-level to the whole Design of Digital System process of device (technique) level.The level of integrated circuit (IC) design can be divided into following level: system-level, functional level (behavior algorithm level), Method at Register Transfer Level (structural level), gate leve (logic circuit stage), domain level (physical level).
Trigger, latch are the elementary cells forming sequential logical circuit, and the power consumption of trigger, latch consumes accounts for 15% ~ 45% of whole chip.For the phenomenon that present clock frequency is more and more higher, the power dissipation ratio of trigger, latch focuses in whole chip also more and more heavier, reduces the power consumption of trigger, has become the mandatory requirements of whole chip design.
Present process-technology-evolutions is to the deep-submicron stage, and the quiescent dissipation that leakage current brings is own through becoming very important power consumption.Reduce leakage power and will reduce leakage current exactly.Leakage current mainly comprises sub-threshold current leakage, pn ties anti-phase leakage current and breakdown current etc., and sub-threshold current leakage is wherein the main part of leakage current.
In current circuit design, the technology of several reduction leakage current is proposed.
1, sub-threshold leakage current control.Multi thresholds cmos circuit (Multi-thresholdCMOS) in a circuit, applies multiple threshold voltage to control subthreshold current, and namely in circuit, the threshold voltage of pipe has different values.Current application many twoly explains threshold voltage, namely adopts at the path of key and lowly explains value metal-oxide-semiconductor, the performance that can obtain, and adopt high threshold metal-oxide-semiconductor at auxiliary channel, to reduce sub-threshold current leakage.
2, dynamic threshold voltage CMOS (DynamicThresholdVoltageCMOS) controls.Dynamic threshold circuit changes threshold value according to the state of circuit.Be estimated and stable leakage current by the negative-feedback circuit of a self-control threshold voltage the earliest, feedback circuit mainly by regulating underlayer voltage to carry out adjusting threshold voltage, which increasing the area of circuit, too increasing certain power consumption.Subsequently, have again practitioner to propose a kind of dynamically metal-oxide-semiconductor, be connected with input by substrate, such underlayer voltage just becomes along with the change of input voltage, without the need to adjunct circuit.This circuit can reduce certain supply voltage further to reduce power consumption, but leakage current differs and reduces surely, and comparison of technology is high.
3, transistor rearrangement method.Transistor rearrangement method is an input vector of first definition circuit, and this vector can reduce the leakage current of circuit.When each door is in high leakage current time, between power supply and ground or on insert leakage current between pull-up network and pulldown network and control transistor and be used for reducing leakage current.This just needs and calculates a predetermined vector, and reduces leakage current by inserting pipe.Although can reduce certain power consumption, this pipe itself also can consume certain energy, and can increase the area of circuit and increase the complexity of circuit design.
Summary of the invention
The technical problem to be solved in the present invention is just: the technical problem existed for prior art, the invention provides a kind ofly to the invention provides the high-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop that a kind of structure is simple, with low cost, can improve efficiency of transmission, reduce static leakage current and power consumption.
For solving the problems of the technologies described above, the present invention by the following technical solutions:
A kind of high-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop, comprising:
Low power consumpting controling circuit, is used for receiving low power consumption control input signal slp, outputs signal respectively: sleep and nsleep to low power consumption control input signal slp after carrying out buffered;
Set control circuit, is used for receiving asynchronous set input signal set, outputs signal respectively: s and ns to asynchronous set input signal set after carrying out buffered;
Select control circuit, be used for receiving and select data to squeeze into inhibit signal sel, selection data are squeezed into after inhibit signal sel carries out buffered and outputs signal respectively: sl and nsl;
Main latch, is used for receiving data input signal d, non-inverting clock input signal clk, inversion clock input signal nclk, asynchronous reset input signal r, selecting data to squeeze into inhibit signal sel and signal sleep, nsleep, s and ns; Described main latch exports qt after data input signal d being carried out to latch process under the control of non-inverting clock input signal clk, inversion clock input signal nclk; Described main latch to sl, nsl process, determines it is squeeze into new data or keep constant from the q value of latch respectively under the control of non-inverting clock input signal clk, inversion clock input signal nclk;
From latch, be used for receiving non-inverting clock input signal clk, inversion clock input signal nclk, asynchronous reset input signal r and signal qt, s, sleep, nsleep; Carry out qt exporting respectively after latch process under the control of non-inverting clock input signal clk, inversion clock input signal nclk from latch: the first output signal q and second output signal nq.
As a further improvement on the present invention: described main latch is not when asynchronous reset signal r is effective by the control of non-inverting clock input signal clk, inversion clock input signal nclk, and exporting qt after process is low level " 0 "; Asynchronous set signal s is Low level effective, ns be high level effective time by non-inverting clock input signal clk, inversion clock input signal nclk control, process after export qt be high level " 1 "; Described main latch is when high level is effective, nsleep is the signal of Low level effective receiving sleep, not by the control of non-inverting clock input signal clk, inversion clock input signal nclk, described main latch enters sleep state, now non-inverting clock input signal clk is low level " 0 ", and inversion clock input signal nclk is high level " 1 ".
As a further improvement on the present invention: the described control not being subject to non-inverting clock input signal clk, inversion clock input signal nclk from latch when asynchronous reset signal r is Low level effective, exporting q after process is low level " 0 ", and nq is high level " 1 "; Asynchronous set signal s be Low level effective, ns be high level effective time by non-inverting clock input signal clk, inversion clock input signal nclk control, process after export q be high level " 1 ", nq is low level " 0 "; Described from latch receive sleep be high level effectively, nsleep be Low level effective signal time, not by the control of non-inverting clock input signal clk, inversion clock input signal nclk, sleep state is entered from latch, now non-inverting clock input signal clk is low level " 0 ", inversion clock input signal nclk is high level " 1 ", output valve q, nq remain unchanged.
As a further improvement on the present invention: described low power consumpting controling circuit has an input and two outputs, and input is slp, be low power consumption control signal, effectively high; Output is sleep, nsleep, non-for what sleep and sleep; Described low power consumpting controling circuit comprises the inverter of a two-stage, and wherein the inverter of the first order is made up of P1PMOS pipe and N1NMOS pipe, and its grid connects slp, exports an output nsleep as low power consumpting controling circuit; The inverter of the second level is managed by P2PMOS and N2NMOS pipe forms, and its grid connects nsleep, exports another output sleep as low power consumpting controling circuit; P1PMOS pipe is connected power supply Vdd with the substrate of P2PMOS pipe, and source electrode connects power supply Vdd; The Substrate ground Vss of N1NMOS pipe and N2NMOS pipe, source electrode connects ground Vss.
As a further improvement on the present invention: described set control circuit has an input and two outputs, and input is set, be synchronous resize control signal, effectively low; Output is s, ns, non-for set and set; Described set control circuit is the inverter of a two-stage, and the inverter of the first order is managed by P1PMOS and N1NMOS pipe forms, and its grid connects set, exports an output ns as set control circuit; The inverter of the second level is managed by P2PMOS and N2NMOS pipe forms, and its grid connects ns, exports another output s as set control circuit; P1PMOS pipe is connected power supply Vdd with the substrate of P2PMOS pipe, and source electrode connects power supply Vdd; The Substrate ground Vss of N1NMOS pipe and N2NMOS pipe, source electrode connects ground Vss.
As a further improvement on the present invention: described selection control circuit has an input and two outputs, and input is sel, for synchronously selecting control signal; Output is sl, nsl, works as sl=1, during nsl=0, selects to squeeze into new data to main latch; Work as sl=0, during nsl=1, select to keep the q value from latch; Described selection control circuit comprises the inverter of a two-stage, and the inverter of the first order is managed by P1PMOS and N1NMOS pipe forms, and its grid connects sel, exports an output nsl as selecting control circuit; The inverter of the second level is managed by P2PMOS and N2NMOS pipe forms, and its grid connects nsl, exports another output sl as selecting control circuit; P1PMOS pipe is connected power supply Vdd with the substrate of P2PMOS pipe, and source electrode connects power supply Vdd; The Substrate ground Vss of N1NMOS pipe and N2NMOS pipe, source electrode connects ground Vss.
As a further improvement on the present invention: described main latch comprises:
G1 circuit, by Low threshold PMOS LP1, Low threshold NMOS tube LN1, Low threshold PMOS LP21, Low threshold NMOS tube LN21, Low threshold PMOS LP22, Low threshold NMOS tube LN22, Low threshold PMOS LP23, Low threshold NMOS tube LN23, high threshold PMOS P9, high threshold NMOS tube N9, high threshold PMOS P21, high threshold NMOS tube N17 form, Low threshold PMOS LP1, the grid connection data d of Low threshold NMOS tube LN1, the grid of high threshold PMOS P9 connects sleep, source electrode connects Vdd, the grid of high threshold NMOS tube N9 connects nsleep, source electrode connects Vss, the grid of high threshold PMOS P21 connects ns, the grid of high threshold NMOS tube N17 connects r, Low threshold PMOS LP21, the grid of Low threshold PMOS LP22 connects nsl, Low threshold PMOS LP23, the grid of Low threshold PMOS LP21 connects sl, Low threshold PMOS LP22, the grid of Low threshold PMOS LP23 connects q, the output of the P pipe logic of G1 circuit connects the source electrode of the cmos transmission gate Low threshold PMOS LP2 of G2 circuit, the output of the N pipe logic of G1 circuit connects the source electrode of the cmos transmission gate Low threshold NMOS tube LN2 of G2 circuit,
G2 circuit, by Low threshold PMOS LP2, Low threshold NMOS tube LN2 forms cmos transmission gate, the grid of Low threshold PMOS LP2 connects drain electrode and the G3 circuit of the cmos transmission gate of grid connection nclk, the G2 circuit of clk, Low threshold NMOS tube LN2, G4 circuit, G6 circuit, G13 circuit is connected;
G3 circuit is a C 2mOS circuit, by high threshold PMOS P10, Low threshold PMOS LP3, Low threshold NMOS tube LN3 and high threshold NMOS tube N10 forms, Low threshold PMOS LP3, the grid of Low threshold NMOS tube LN3 connects the output of the cmos transmission gate drain electrode of G2 circuit, the output of the transmission gate of the output that the high threshold PMOS P17 simultaneously also connecting G13 circuit drains and G6 circuit, the grid of high threshold PMOS P10 connects sleep, source electrode connects Vdd, the grid of high threshold NMOS tube N10 connects nsleep, source electrode connects Vss, the output of G3 circuit is qt, be connected with the output of G4 circuit and the input of G5 circuit simultaneously,
G4 circuit, G5 circuit, G6 circuit forms a feedback holding circuit, and G4 circuit is the NAND gate of high threshold pipe composition, and G5 circuit is the inverter of high threshold pipe composition, and G6 circuit is the cmos transmission gate of Low threshold pipe composition, G4 circuit is a NAND gate, by high threshold PMOS P11, high threshold NMOS tube N11, high threshold PMOS P19, high threshold NMOS tube N19 forms, high threshold PMOS P11, the grid input of high threshold NMOS tube N11 connects the output of the cmos transmission gate drain electrode of G2 circuit, the output of the transmission gate of the output that the high threshold PMOS P17 simultaneously also connecting G13 circuit drains and G6 circuit, the source electrode of high threshold PMOS P11 meets Vdd, high threshold PMOS P19, the grid of high threshold NMOS tube N19 meets s, the source electrode of high threshold PMOS P19 meets Vdd, the source electrode of high threshold NMOS tube N19 meets Vss, the output of G4 circuit is connected with qt, grid simultaneously as G5 circuit inputs, G5 circuit is the inverter of high threshold pipe composition, high threshold PMOS P12, the grid of high threshold NMOS tube N12 connects the output of G4 circuit, the source electrode of high threshold PMOS P12 meets Vdd, the source electrode of high threshold NMOS tube N12 meets Vss, and the output of G5 circuit is connected with the source electrode of the cmos transmission gate of G6 circuit, the source electrode of the cmos transmission gate of G6 circuit is connected with the output of G5 circuit, the output that the drain electrode of the cmos transmission gate of G6 circuit drains with the cmos transmission gate of G2 circuit is connected, be connected with the grid of the Low threshold pipe of G3 circuit simultaneously, be connected with the input of G4 circuit again, the grid of Low threshold PMOS LP4 meets nclk, and the grid of Low threshold NMOS tube LN4 meets clk.
As a further improvement on the present invention: describedly to comprise from latch:
G7 circuit is a C 2mOS circuit, by high threshold PMOS P13, Low threshold PMOS LP5, Low threshold NMOS tube LN5 and high threshold NMOS tube N13 form, Low threshold PMOS LP5, the grid connection data qt of Low threshold NMOS tube LN5, the grid of high threshold PMOS P13 connects sleep, and the grid that source electrode connects Vdd, high threshold NMOS tube N13 connects nsleep, source electrode connects the source electrode of the cmos transmission gate of the output connection G8 circuit of Vss, G7 circuit;
G8 circuit, by Low threshold PMOS LP6, Low threshold NMOS tube LN6 forms cmos transmission gate, the grid of Low threshold PMOS LP6 connects drain electrode and the G9 circuit of the cmos transmission gate of grid connection clk, the G8 circuit of nclk, Low threshold NMOS tube LN6, G10 circuit, G12 circuit is connected;
G9 circuit is a C 2mOS circuit, by high threshold PMOS P14, Low threshold PMOS LP7, Low threshold NMOS tube LN7 and high threshold NMOS tube N14 form, Low threshold PMOS LP7, the grid of Low threshold NMOS tube LN7 connects the output of the cmos transmission gate drain electrode of G8 circuit, and the grid of high threshold PMOS P14 connects sleep, and source electrode connects Vdd, the grid of high threshold NMOS tube N14 connects nsleep, the output that source electrode connects Vss, G9 circuit is q, is connected with the output of G10 circuit and the input of G11 circuit simultaneously;
G10 circuit, G11 circuit, G12 circuit forms a feedback holding circuit, and G10 circuit is the NAND gate of high threshold pipe composition, and G11 circuit is the inverter of high threshold pipe composition, and G12 circuit is the cmos transmission gate of Low threshold pipe composition; G10 circuit is a NAND gate, by high threshold PMOS P15, high threshold NMOS tube N15, high threshold PMOS P20, high threshold NMOS tube N20 forms, high threshold PMOS P15, the grid input of high threshold NMOS tube N15 connects the output of the cmos transmission gate drain electrode of G8 circuit, the source electrode of high threshold PMOS P15 meets Vdd, high threshold PMOS P20, and the grid of high threshold NMOS tube N20 meets s, the source electrode of high threshold PMOS P20 meets Vdd, the source electrode of high threshold NMOS tube N20 meets Vss, and the output of G10 is connected with q, and the grid simultaneously as G11 circuit inputs; The grid of G11 circuit connects the output of G10 circuit, and the source electrode of high threshold PMOS P16 meets Vdd, and the source electrode of high threshold NMOS tube N16 meets Vss, and the output of G11 circuit is nq, is connected with the source electrode of the cmos transmission gate of G12 circuit simultaneously; The source electrode of the cmos transmission gate of G12 circuit is connected with the output of G11 circuit, the output that the drain electrode of the cmos transmission gate of G12 circuit drains with the cmos transmission gate of G8 circuit is connected, be connected with the grid of the Low threshold pipe of G9 circuit simultaneously, input again in G10 circuit is connected, the grid of Low threshold PMOS LP8 meets clk, and the grid of Low threshold NMOS tube LN8 meets nclk.
Compared with prior art, the invention has the advantages that: high-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop of the present invention, structure is simple, with low cost, for a kind of multi thresholds high speed, low-power consumption D flip-flop, while realizing D flip-flop basic function, adopt the concept of multi thresholds, the data path, clock path of Chief use Low threshold device, improves efficiency of transmission.With high threshold device on non-critical path, reduce static leakage current, reduce power consumption.Present invention reduces the voltage magnitude of clock signal clk simultaneously, namely on clock path, adopt Low threshold device, reduce the amplitude of clock voltage, effectively reduce P swichingpower consumption.
Accompanying drawing explanation
Fig. 1 is topological structure principle schematic of the present invention.
Fig. 2 is the structural principle schematic diagram of the present invention's low power consumpting controling circuit in embody rule example.
Fig. 3 is the structural principle schematic diagram of the present invention's set control circuit in embody rule example.
Fig. 4 is the structural principle schematic diagram that the present invention selects control circuit in embody rule example.
Fig. 5 is the structural principle schematic diagram of the present invention's main latch in embody rule example.
Fig. 6 is the present invention's structural principle schematic diagram from latch in embody rule example.
Embodiment
Below with reference to Figure of description and specific embodiment, the present invention is described in further details.
As shown in Figure 1, high-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop of the present invention, comprises low power consumpting controling circuit, set control circuit, selects control circuit, main latch and from latch.Trigger of the present invention has seven inputs and two outputs.Seven inputs are used for connecting respectively: non-inverting clock input signal clk, inversion clock input signal nclk, low power consumption control input signal slp, selection data squeeze into inhibit signal sel, asynchronous reset input signal r, asynchronous set input signal set and data input signal d; Two outputs are used for exporting: the first output signal q and second output signal nq, and the first output signal q and second output signal nq is a pair contrary data-signal.Wherein:
Low power consumpting controling circuit, is used for receiving low power consumption control input signal slp, outputs signal respectively: sleep and nsleep to low power consumption control input signal slp after carrying out buffered.
Set control circuit, is used for receiving asynchronous set input signal set, outputs signal respectively: s and ns to asynchronous set input signal set after carrying out buffered.
Select control circuit, be used for receiving and select data to squeeze into inhibit signal sel, selection data are squeezed into after inhibit signal sel carries out buffered and outputs signal respectively: sl and nsl.
Main latch, is used for receiving data input signal d, non-inverting clock input signal clk, inversion clock input signal nclk, asynchronous reset input signal r, selecting data to squeeze into inhibit signal sel and signal sleep, nsleep, s and ns.Main latch exports qt after data input signal d being carried out to latch process under the control of non-inverting clock input signal clk, inversion clock input signal nclk; Main latch to sl, nsl process, determines it is the q value constant (sl=0, nsl=1) squeezed into new data (sl=1, nsl=0) or keep from latch respectively under the control of non-inverting clock input signal clk, inversion clock input signal nclk; At asynchronous reset signal r(Low level effective) effectively time by the control of non-inverting clock input signal clk, inversion clock input signal nclk, exporting qt after process is low level " 0 "; Asynchronous set signal s(Low level effective), ns(high level is effective) effectively time by the control of non-inverting clock input signal clk, inversion clock input signal nclk, exporting qt after process is high level " 1 "; Main latch is to receive sleep(high level effective), nsleep(Low level effective) signal time, not by the control of non-inverting clock input signal clk, inversion clock input signal nclk, main latch enters sleep state, now requiring that clock control parts export non-inverting clock input signal clk is low level " 0 ", and inversion clock input signal nclk is high level " 1 ".
From latch, be used for receiving non-inverting clock input signal clk, inversion clock input signal nclk, asynchronous reset input signal r and signal qt, s, sleep, nsleep; Carry out qt exporting respectively after latch process under the control of non-inverting clock input signal clk, inversion clock input signal nclk from latch: the first output signal q and second output signal nq.Asynchronous reset signal r(Low level effective) effectively time by the control of non-inverting clock input signal clk, inversion clock input signal nclk, exporting q after process is low level " 0 ", and nq is high level " 1 ".Asynchronous set signal s(Low level effective), ns(high level is effective) effectively time by the control of non-inverting clock input signal clk, inversion clock input signal nclk, exporting q after process is high level " 1 ", and nq is low level " 0 ".From latch to receive sleep(high level effective), nsleep(Low level effective) signal time, not by the control of non-inverting clock input signal clk, inversion clock input signal nclk, sleep state is entered from latch, now require that non-inverting clock input signal clk is low level " 0 ", inversion clock input signal nclk is high level " 1 ", output valve q, nq remain unchanged.
As shown in Figure 2, in the present embodiment, low power consumpting controling circuit has an input and two outputs, and input is slp, is low power consumption control signal, effectively high; Output is sleep, nsleep, non-for what sleep and sleep.Low power consumpting controling circuit comprises the inverter of a two-stage, and wherein the inverter of the first order is made up of P1PMOS pipe and N1NMOS pipe, and its grid connects slp, exports an output nsleep as low power consumpting controling circuit; The inverter of the second level is managed by P2PMOS and N2NMOS pipe forms, and its grid connects nsleep, exports another output sleep as low power consumpting controling circuit.P1PMOS pipe is connected power supply Vdd with the substrate of P2PMOS pipe, and source electrode connects power supply Vdd; The Substrate ground Vss of N1NMOS pipe and N2NMOS pipe, source electrode connects ground Vss.
As shown in Figure 3, in the present embodiment, set control circuit has an input and two outputs, and input is set, is synchronous resize control signal, effectively low; Output is s, ns, non-for set and set.Set control circuit is the inverter of a two-stage, and the inverter of the first order is managed by P1PMOS and N1NMOS pipe forms, and its grid connects set, exports an output ns as set control circuit; The inverter of the second level is managed by P2PMOS and N2NMOS pipe forms, and its grid connects ns, exports another output s as set control circuit.P1PMOS pipe is connected power supply Vdd with the substrate of P2PMOS pipe, and source electrode connects power supply Vdd; The Substrate ground Vss of N1NMOS pipe and N2NMOS pipe, source electrode connects ground Vss.
As shown in Figure 4, in the present embodiment, select control circuit to have an input and two outputs, input is sel, for synchronously selecting control signal.Output is sl, nsl, works as sl=1, during nsl=0, selects to squeeze into new data to main latch; Work as sl=0, during nsl=1, select to keep the q value from latch.Select control circuit to comprise the inverter of a two-stage, the inverter of the first order is managed by P1PMOS and N1NMOS pipe forms, and its grid connects sel, exports an output nsl as selecting control circuit; The inverter of the second level is managed by P2PMOS and N2NMOS pipe forms, and its grid connects nsl, exports another output sl as selecting control circuit.P1PMOS pipe is connected power supply Vdd with the substrate of P2PMOS pipe, and source electrode connects power supply Vdd; The Substrate ground Vss of N1NMOS pipe and N2NMOS pipe, source electrode connects ground Vss.
As shown in Figure 5, in the present embodiment, main latch has ten inputs and an output, and ten inputs are d, clk, nclk, sl, nsl, r, s, ns, sleep, nsleep, and an output is qt.Main latch is made up of 14 PMOS and 13 NMOS tube, wherein has seven Low threshold pipes (LP1, LP2, LP3, LP4, LP21, LP22, LP23) in 14 PMOS, seven high threshold pipes (P9, P10, P11, P12, P17, P19, P21); Seven Low threshold pipes (LN1, LN2, LN3, LN4, LN21, LN22, LN23) are had, six high threshold pipes (N9, N10, N11, N12, N17, N19) in 13 NMOS tube.In main latch, the substrate of all PMOS connects power supply Vdd, the Substrate ground Vss of all NMOS tube.Main latch comprises:
G1 circuit, is made up of LP1, LN1, LP21, LN21, LP22, LN22, LP23, LN23, P9, N9, P21, N17.The grid of the grid connection data d of LP1, LN1, P9 connects sleep, the grid that source electrode connects Vdd, N9 connects nsleep, and source electrode connects Vss, the grid of P21 connects the grid connection nsl of grid connection r, LP21, the LP22 of ns, N17, LP23, the grid of LP21 connects the grid connection q of sl, LP22, LP23, the output of the P pipe logic of G1 circuit connects the source electrode of the cmos transmission gate LP2 of G2 circuit, and the output of the N pipe logic of G1 circuit connects the source electrode of the cmos transmission gate LN2 of G2 circuit.
G2 circuit, forms cmos transmission gate by LP2, LN2, and the grid of LP2 connects drain electrode and the G3 circuit of the cmos transmission gate of grid connection nclk, the G2 circuit of clk, LN2, and G4 circuit, G6 circuit, G13 circuit is connected.
G3 circuit is a C 2mOS circuit, by P10, LP3, LN3 and N10 forms, the grid of LP3, LN3 connects the output of the cmos transmission gate drain electrode of G2 circuit, also connects the output of P17 drain electrode of G13 circuit and the output of the transmission gate of G6 circuit simultaneously, the grid of P10 connects sleep, the grid that source electrode connects Vdd, N10 connects nsleep, and source electrode connects Vss, the output of G3 circuit is qt, is connected with the output of G4 circuit and the input of G5 circuit simultaneously.
G4 circuit, G5 circuit, G6 circuit forms a feedback holding circuit, and G4 circuit is the NAND gate of high threshold pipe composition, and G5 circuit is the inverter of high threshold pipe composition, and G6 circuit is the cmos transmission gate of Low threshold pipe composition.G4 circuit is a NAND gate, by high threshold pipe P11, N11, P19, N19 form, P11, the grid input of N11 connects the output of the cmos transmission gate drain electrode of G2 circuit, and also connect the output of P17 drain electrode of G13 circuit and the output of the transmission gate of G6 circuit, the source electrode of P11 meets Vdd simultaneously, P19, the grid of N19 meets s, and the source electrode of P19 meets Vdd, and the source electrode of N19 meets Vss, the output of G4 circuit is connected with qt, and the grid simultaneously as G5 circuit inputs.G5 circuit is the inverter of high threshold pipe composition, and the grid of P12, N12 connects the output of G4 circuit, and the source electrode of P12 meets Vdd, and the source electrode of N12 meets Vss, and the output of G5 circuit is connected with the source electrode of the cmos transmission gate of G6 circuit.The source electrode (input) of the cmos transmission gate of G6 circuit is connected with the output of G5 circuit, the output that drain electrode (output) and the cmos transmission gate of G2 circuit of the cmos transmission gate of G6 circuit drain is connected, be connected with the grid of the Low threshold pipe of G3 circuit simultaneously, be connected with the input of G4 circuit again, the grid of LP4 meets nclk, and the grid of LN4 meets clk.
As shown in Figure 6, in the present embodiment, have seven inputs and two outputs from latch, seven inputs are qt, clk, nclk, r, s, sleep, nsleep, and two outputs are q and nq.Be made up of ten PMOS and nine NMOS tube from latch, wherein have four Low threshold pipes (LP5, LP6, LP7, LP8) in ten PMOS, six high threshold pipes (P13, P14, P15, P16, P18, P20); Four Low threshold pipes (LN5, LN6, LN7, LN8) are had, five high threshold pipes (N13, N14, N15, N16, N20) in nine NMOS tube.From latch, the substrate of all PMOS connects power supply Vdd, the Substrate ground Vss of all NMOS tube.Comprise from latch:
G7 circuit is a C 2mOS circuit, is made up of P13, LP5, LN5 and N13, the grid of the grid connection data qt of LP5, LN5, P13 connects sleep, and source electrode connects Vdd, the grid of N13 connects nsleep, and source electrode connects the source electrode of the cmos transmission gate of the output connection G8 circuit of Vss, G7 circuit.
G8 circuit, forms cmos transmission gate by LP6, LN6, and the grid of LP6 connects drain electrode and the G9 circuit of the cmos transmission gate of grid connection clk, the G8 circuit of nclk, LN6, and G10 circuit, G12 circuit is connected.
G9 circuit is a C 2mOS circuit, be made up of P14, LP7, LN7 and N14, LP7, the grid of LN7 connects the output of the cmos transmission gate drain electrode of G8 circuit, and the grid of P14 connects sleep, and source electrode connects Vdd, the grid of N14 connects nsleep, the output that source electrode connects Vss, G9 circuit is q, is connected with the output of G10 circuit and the input of G11 circuit simultaneously.
G10 circuit, G11 circuit, G12 circuit forms a feedback holding circuit, and G10 circuit is the NAND gate of high threshold pipe composition, and G11 circuit is the inverter of high threshold pipe composition, and G12 circuit is the cmos transmission gate of Low threshold pipe composition.G10 circuit is a NAND gate, by high threshold pipe P15, N15, P20, N20 form, P15, the grid input of N15 connects the output of the cmos transmission gate drain electrode of G8 circuit, the source electrode of P15 meets Vdd, and the grid of P20, N20 meets s, the source electrode of P20 meets Vdd, the source electrode of N20 meets Vss, and the output of G10 is connected with q, and the grid simultaneously as G11 circuit inputs.The grid of G11 circuit connects the output of G10 circuit, and the source electrode of P16 meets Vdd, and the source electrode of N16 meets Vss, and the output of G11 circuit is nq, is connected with the source electrode of the cmos transmission gate of G12 circuit simultaneously.The source electrode (input) of the cmos transmission gate of G12 circuit is connected with the output of G11 circuit, the output that drain electrode (output) and the cmos transmission gate of G8 circuit of the cmos transmission gate of G12 circuit drain is connected, be connected with the grid of the Low threshold pipe of G9 circuit simultaneously, input again in G10 circuit is connected, the grid of LP8 meets clk, and the grid of LN8 meets nclk.
In sum, high-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop of the present invention is a kind of multi thresholds high speed, low-power consumption D flip-flop, while realizing d type flip flop basic function, adopt the concept of multi thresholds, the data path, clock path of Chief use Low threshold device, improves efficiency of transmission.With high threshold device on non-critical path, reduce static leakage current, reduce power consumption.The power consumption of clock system accounts for 20% ~ 45% of whole chip power-consumption again.In cmos circuitry, total power consumption can be expressed from the next:
P total=P swiching+P short+P leakage
=α（C L·V·V dd·f clk）+I short·V dd+I leakage·V dd
P swichingswitching power loss, when signal saltus step, to the power consumption that load capacitance discharge and recharge produces.α represents that a clock cycle interior nodes voltage is from 0 to V ddaverage transition times, C lfor load capacitance.P shortbe short circuit current power consumption, when signal is imperfect step, the conducting simultaneously of NMOS tube, PMOS, produces the short circuit current I of power supply to ground short, cause short-circuit dissipation P short.P leakagebe leakage power, owing to there is the leakage currents such as pn junction leakage and sub-threshold value in MOS, form the leakage current from source transistor best ground, the power consumption caused thus is leakage power, also referred to as quiescent dissipation.The present invention, by reducing the voltage magnitude of clock signal clk, effectively can reduce P swiching, V in the present invention clk<V dd.
Below be only the preferred embodiment of the present invention, protection scope of the present invention be not only confined to above-described embodiment, all technical schemes belonged under thinking of the present invention all belong to protection scope of the present invention.It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principles of the present invention, should be considered as protection scope of the present invention.

Claims (7)

1. a high-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop, is characterized in that, comprising:
Low power consumpting controling circuit, is used for receiving low power consumption control input signal slp, outputs signal respectively: sleep and nsleep to low power consumption control input signal slp after carrying out buffered; Described low power consumpting controling circuit has an input and two outputs, and input is slp, is low power consumption control signal, effectively high; Output is sleep, nsleep, non-for what sleep and sleep; Described low power consumpting controling circuit comprises the inverter of a two-stage, and wherein the inverter of the first order is made up of P1PMOS pipe and N1NMOS pipe, and its grid connects slp, exports an output nsleep as low power consumpting controling circuit; The inverter of the second level is managed by P2PMOS and N2NMOS pipe forms, and its grid connects nsleep, exports another output sleep as low power consumpting controling circuit; P1PMOS pipe is connected power supply Vdd with the substrate of P2PMOS pipe, and source electrode connects power supply Vdd; The Substrate ground Vss of N1NMOS pipe and N2NMOS pipe, source electrode connects ground Vss;
Set control circuit, is used for receiving asynchronous set input signal set, outputs signal respectively: s and ns to asynchronous set input signal set after carrying out buffered;
Select control circuit, be used for receiving and select data to squeeze into inhibit signal sel, selection data are squeezed into after inhibit signal sel carries out buffered and outputs signal respectively: sl and nsl;
Main latch, is used for receiving data input signal d, non-inverting clock input signal clk, inversion clock input signal nclk, asynchronous reset input signal r, selecting data to squeeze into inhibit signal sel and signal sleep, nsleep, s and ns; Described main latch exports qt after data input signal d being carried out to latch process under the control of non-inverting clock input signal clk, inversion clock input signal nclk; Described main latch to sl, nsl process, determines it is squeeze into new data or keep constant from the q value of latch respectively under the control of non-inverting clock input signal clk, inversion clock input signal nclk;
From latch, be used for receiving non-inverting clock input signal clk, inversion clock input signal nclk, asynchronous reset input signal r and signal qt, s, sleep, nsleep; Carry out qt exporting respectively after latch process under the control of non-inverting clock input signal clk, inversion clock input signal nclk from latch: the first output signal q and second output signal nq.
2. high-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop according to claim 1, it is characterized in that, described main latch is not when asynchronous reset signal r is effective by the control of non-inverting clock input signal clk, inversion clock input signal nclk, and exporting qt after process is low level " 0 "; Asynchronous set signal s is Low level effective, ns be high level effective time by non-inverting clock input signal clk, inversion clock input signal nclk control, process after export qt be high level " 1 "; Described main latch is when high level is effective, nsleep is the signal of Low level effective receiving sleep, not by the control of non-inverting clock input signal clk, inversion clock input signal nclk, described main latch enters sleep state, now non-inverting clock input signal clk is low level " 0 ", and inversion clock input signal nclk is high level " 1 ".
3. high-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop according to claim 1, it is characterized in that, the described control not being subject to non-inverting clock input signal clk, inversion clock input signal nclk from latch when asynchronous reset signal r is Low level effective, exporting q after process is low level " 0 ", and nq is high level " 1 "; Asynchronous set signal s be Low level effective, ns be high level effective time by non-inverting clock input signal clk, inversion clock input signal nclk control, process after export q be high level " 1 ", nq is low level " 0 "; Described from latch receive sleep be high level effectively, nsleep be Low level effective signal time, not by the control of non-inverting clock input signal clk, inversion clock input signal nclk, sleep state is entered from latch, now non-inverting clock input signal clk is low level " 0 ", inversion clock input signal nclk is high level " 1 ", output valve q, nq remain unchanged.
4. the high-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop according to claim 1 or 2 or 3, it is characterized in that, described set control circuit has an input and two outputs, and input is set, for synchronous resize control signal, effectively low; Output is s, ns, non-for set and set; Described set control circuit is the inverter of a two-stage, and the inverter of the first order is managed by P1PMOS and N1NMOS pipe forms, and its grid connects set, exports an output ns as set control circuit; The inverter of the second level is managed by P2PMOS and N2NMOS pipe forms, and its grid connects ns, exports another output s as set control circuit; P1PMOS pipe is connected power supply Vdd with the substrate of P2PMOS pipe, and source electrode connects power supply Vdd; The Substrate ground Vss of N1NMOS pipe and N2NMOS pipe, source electrode connects ground Vss.
5. the high-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop according to claim 1 or 2 or 3, it is characterized in that, described selection control circuit has an input and two outputs, and input is sel, for synchronously selecting control signal; Output is sl, nsl, works as sl=1, during nsl=0, selects to squeeze into new data to main latch; Work as sl=0, during nsl=1, select to keep the q value from latch; Described selection control circuit comprises the inverter of a two-stage, and the inverter of the first order is managed by P1PMOS and N1NMOS pipe forms, and its grid connects sel, exports an output nsl as selecting control circuit; The inverter of the second level is managed by P2PMOS and N2NMOS pipe forms, and its grid connects nsl, exports another output sl as selecting control circuit; P1PMOS pipe is connected power supply Vdd with the substrate of P2PMOS pipe, and source electrode connects power supply Vdd; The Substrate ground Vss of N1NMOS pipe and N2NMOS pipe, source electrode connects ground Vss.
6. the high-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop according to claim 1 or 2 or 3, it is characterized in that, described main latch comprises:
G1 circuit, by Low threshold PMOS LP1, Low threshold NMOS tube LN1, Low threshold PMOS LP21, Low threshold NMOS tube LN21, Low threshold PMOS LP22, Low threshold NMOS tube LN22, Low threshold PMOS LP23, Low threshold NMOS tube LN23, high threshold PMOS P9, high threshold NMOS tube N9, high threshold PMOS P21, high threshold NMOS tube N17 form, Low threshold PMOS LP1, the grid connection data d of Low threshold NMOS tube LN1, the grid of high threshold PMOS P9 connects sleep, source electrode connects Vdd, the grid of high threshold NMOS tube N9 connects nsleep, source electrode connects Vss, the grid of high threshold PMOS P21 connects ns, the grid of high threshold NMOS tube N17 connects r, Low threshold PMOS LP21, the grid of Low threshold PMOS LP22 connects nsl, Low threshold PMOS LP23, the grid of Low threshold PMOS LP21 connects sl, Low threshold PMOS LP22, the grid of Low threshold PMOS LP23 connects q, the output of the P pipe logic of G1 circuit connects the source electrode of the cmos transmission gate Low threshold PMOS LP2 of G2 circuit, the output of the N pipe logic of G1 circuit connects the source electrode of the cmos transmission gate Low threshold NMOS tube LN2 of G2 circuit,
G2 circuit, by Low threshold PMOS LP2, Low threshold NMOS tube LN2 forms cmos transmission gate, the grid of Low threshold PMOS LP2 connects drain electrode and the G3 circuit of the cmos transmission gate of grid connection nclk, the G2 circuit of clk, Low threshold NMOS tube LN2, G4 circuit, G6 circuit, G13 circuit is connected;
G3 circuit is a C 2mOS circuit, by high threshold PMOS P10, Low threshold PMOS LP3, Low threshold NMOS tube LN3 and high threshold NMOS tube N10 forms, Low threshold PMOS LP3, the grid of Low threshold NMOS tube LN3 connects the output of the cmos transmission gate drain electrode of G2 circuit, the output of the transmission gate of the output that the high threshold PMOS P17 simultaneously also connecting G13 circuit drains and G6 circuit, the grid of high threshold PMOS P10 connects sleep, source electrode connects Vdd, the grid of high threshold NMOS tube N10 connects nsleep, source electrode connects Vss, the output of G3 circuit is qt, be connected with the output of G4 circuit and the input of G5 circuit simultaneously,
G4 circuit, G5 circuit, G6 circuit forms a feedback holding circuit, and G4 circuit is the NAND gate of high threshold pipe composition, and G5 circuit is the inverter of high threshold pipe composition, and G6 circuit is the cmos transmission gate of Low threshold pipe composition, G4 circuit is a NAND gate, by high threshold PMOS P11, high threshold NMOS tube N11, high threshold PMOS P19, high threshold NMOS tube N19 forms, high threshold PMOS P11, the grid input of high threshold NMOS tube N11 connects the output of the cmos transmission gate drain electrode of G2 circuit, the output of the transmission gate of the output that the high threshold PMOS P17 simultaneously also connecting G13 circuit drains and G6 circuit, the source electrode of high threshold PMOS P11 meets Vdd, high threshold PMOS P19, the grid of high threshold NMOS tube N19 meets s, the source electrode of high threshold PMOS P19 meets Vdd, the source electrode of high threshold NMOS tube N19 meets Vss, the output of G4 circuit is connected with qt, grid simultaneously as G5 circuit inputs, G5 circuit is the inverter of high threshold pipe composition, high threshold PMOS P12, the grid of high threshold NMOS tube N12 connects the output of G4 circuit, the source electrode of high threshold PMOS P12 meets Vdd, the source electrode of high threshold NMOS tube N12 meets Vss, and the output of G5 circuit is connected with the source electrode of the cmos transmission gate of G6 circuit, the source electrode of the cmos transmission gate of G6 circuit is connected with the output of G5 circuit, the output that the drain electrode of the cmos transmission gate of G6 circuit drains with the cmos transmission gate of G2 circuit is connected, be connected with the grid of the Low threshold pipe of G3 circuit simultaneously, be connected with the input of G4 circuit again, the grid of Low threshold PMOS LP4 meets nclk, and the grid of Low threshold NMOS tube LN4 meets clk.
7. the high-speed low-power-consumption multi thresholds asynchronous set reset maintenance D flip-flop according to claim 1 or 2 or 3, is characterized in that, describedly comprises from latch:
G7 circuit is a C 2mOS circuit, by high threshold PMOS P13, Low threshold PMOS LP5, Low threshold NMOS tube LN5 and high threshold NMOS tube N13 form, Low threshold PMOS LP5, the grid connection data qt of Low threshold NMOS tube LN5, the grid of high threshold PMOS P13 connects sleep, and the grid that source electrode connects Vdd, high threshold NMOS tube N13 connects nsleep, source electrode connects the source electrode of the cmos transmission gate of the output connection G8 circuit of Vss, G7 circuit;
G8 circuit, by Low threshold PMOS LP6, Low threshold NMOS tube LN6 forms cmos transmission gate, the grid of Low threshold PMOS LP6 connects drain electrode and the G9 circuit of the cmos transmission gate of grid connection clk, the G8 circuit of nclk, Low threshold NMOS tube LN6, G10 circuit, G12 circuit is connected;
G9 circuit is a C 2mOS circuit, by high threshold PMOS P14, Low threshold PMOS LP7, Low threshold NMOS tube LN7 and high threshold NMOS tube N14 form, Low threshold PMOS LP7, the grid of Low threshold NMOS tube LN7 connects the output of the cmos transmission gate drain electrode of G8 circuit, and the grid of high threshold PMOS P14 connects sleep, and source electrode connects Vdd, the grid of high threshold NMOS tube N14 connects nsleep, the output that source electrode connects Vss, G9 circuit is q, is connected with the output of G10 circuit and the input of G11 circuit simultaneously;
G10 circuit, G11 circuit, G12 circuit forms a feedback holding circuit, and G10 circuit is the NAND gate of high threshold pipe composition, and G11 circuit is the inverter of high threshold pipe composition, and G12 circuit is the cmos transmission gate of Low threshold pipe composition; G10 circuit is a NAND gate, by high threshold PMOS P15, high threshold NMOS tube N15, high threshold PMOS P20, high threshold NMOS tube N20 forms, high threshold PMOS P15, the grid input of high threshold NMOS tube N15 connects the output of the cmos transmission gate drain electrode of G8 circuit, the source electrode of high threshold PMOS P15 meets Vdd, high threshold PMOS P20, and the grid of high threshold NMOS tube N20 meets s, the source electrode of high threshold PMOS P20 meets Vdd, the source electrode of high threshold NMOS tube N20 meets Vss, and the output of G10 is connected with q, and the grid simultaneously as G11 circuit inputs; The grid of G11 circuit connects the output of G10 circuit, and the source electrode of high threshold PMOS P16 meets Vdd, and the source electrode of high threshold NMOS tube N16 meets Vss, and the output of G11 circuit is nq, is connected with the source electrode of the cmos transmission gate of G12 circuit simultaneously; The source electrode of the cmos transmission gate of G12 circuit is connected with the output of G11 circuit, the output that the drain electrode of the cmos transmission gate of G12 circuit drains with the cmos transmission gate of G8 circuit is connected, be connected with the grid of the Low threshold pipe of G9 circuit simultaneously, input again in G10 circuit is connected, the grid of Low threshold PMOS LP8 meets clk, and the grid of Low threshold NMOS tube LN8 meets nclk.
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